drivers/gpu/drm/amd/amdgpu/amdgpu.h

1416

u32 tmp = RREG32_SMC(_Reg); \

drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c

66

return RREG32_SMC(index);

drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c

776

value = RREG32_SMC(*pos);

drivers/gpu/drm/amd/amdgpu/cik.c

1464

tmp = RREG32_SMC(cntl_reg);

drivers/gpu/drm/amd/amdgpu/cik.c

1471

if (RREG32_SMC(status_reg) & CG_DCLK_STATUS__DCLK_STATUS_MASK)

drivers/gpu/drm/amd/amdgpu/cik.c

1506

if (RREG32_SMC(ixCG_ECLK_STATUS) & CG_ECLK_STATUS__ECLK_STATUS_MASK)

drivers/gpu/drm/amd/amdgpu/cik.c

1513

tmp = RREG32_SMC(ixCG_ECLK_CNTL);

drivers/gpu/drm/amd/amdgpu/cik.c

1520

if (RREG32_SMC(ixCG_ECLK_STATUS) & CG_ECLK_STATUS__ECLK_STATUS_MASK)

drivers/gpu/drm/amd/amdgpu/cik.c

1791

orig = data = RREG32_SMC(ixTHM_CLK_CNTL);

drivers/gpu/drm/amd/amdgpu/cik.c

1799

orig = data = RREG32_SMC(ixMISC_CLK_CTRL);

drivers/gpu/drm/amd/amdgpu/cik.c

1807

orig = data = RREG32_SMC(ixCG_CLKPIN_CNTL);

drivers/gpu/drm/amd/amdgpu/cik.c

1812

orig = data = RREG32_SMC(ixCG_CLKPIN_CNTL_2);

drivers/gpu/drm/amd/amdgpu/cik.c

1817

orig = data = RREG32_SMC(ixMPLL_BYPASSCLK_SEL);

drivers/gpu/drm/amd/amdgpu/cik.c

1939

clock_cntl = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);

drivers/gpu/drm/amd/amdgpu/cik.c

1940

pc = RREG32_SMC(ixSMC_PC_C);

drivers/gpu/drm/amd/amdgpu/cik.c

922

if (RREG32_SMC(ixGENERAL_PWRMGT) & GENERAL_PWRMGT__GPU_COUNTER_CLK_MASK)

drivers/gpu/drm/amd/amdgpu/cik.c

925

if (RREG32_SMC(ixCG_CLKPIN_CNTL) & CG_CLKPIN_CNTL__XTALIN_DIVIDE_MASK)

drivers/gpu/drm/amd/amdgpu/cik.c

982

rom_cntl = RREG32_SMC(ixROM_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

799

data = RREG32_SMC(ixCG_ACLK_CNTL);

drivers/gpu/drm/amd/amdgpu/si.c

1890

if ((RREG32_SMC(CG_VCEPLL_FUNC_CNTL) & mask) == mask)

drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c

733

if (!(RREG32_SMC(ixCURRENT_PG_STATUS) &

drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c

744

if (RREG32_SMC(ixCURRENT_PG_STATUS) &

drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c

847

if (RREG32_SMC(ixCURRENT_PG_STATUS) &

drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

1511

data = RREG32_SMC(ixCURRENT_PG_STATUS_APU);

drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

1513

data = RREG32_SMC(ixCURRENT_PG_STATUS);

drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

365

(RREG32_SMC(ixCC_HARVEST_FUSES) & CC_HARVEST_FUSES__UVD_DISABLE_MASK))

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

373

tmp = (RREG32_SMC(ixVCE_HARVEST_FUSE_MACRO__ADDRESS) &

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

377

tmp = (RREG32_SMC(ixCC_HARVEST_FUSES) &

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

844

data = RREG32_SMC(ixCURRENT_PG_STATUS_APU);

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

846

data = RREG32_SMC(ixCURRENT_PG_STATUS);

drivers/gpu/drm/amd/amdgpu/vi.c

1004

tmp = RREG32_SMC(status_reg);

drivers/gpu/drm/amd/amdgpu/vi.c

1080

if (RREG32_SMC(reg_status) & status_mask)

drivers/gpu/drm/amd/amdgpu/vi.c

1088

tmp = RREG32_SMC(reg_ctrl);

drivers/gpu/drm/amd/amdgpu/vi.c

1094

if (RREG32_SMC(reg_status) & status_mask)

drivers/gpu/drm/amd/amdgpu/vi.c

1186

orig = data = RREG32_SMC(ixTHM_CLK_CNTL);

drivers/gpu/drm/amd/amdgpu/vi.c

1193

orig = data = RREG32_SMC(ixMISC_CLK_CTRL);

drivers/gpu/drm/amd/amdgpu/vi.c

1202

orig = data = RREG32_SMC(ixCG_CLKPIN_CNTL);

drivers/gpu/drm/amd/amdgpu/vi.c

1207

orig = data = RREG32_SMC(ixCG_CLKPIN_CNTL_2);

drivers/gpu/drm/amd/amdgpu/vi.c

1212

orig = data = RREG32_SMC(ixMPLL_BYPASSCLK_SEL);

drivers/gpu/drm/amd/amdgpu/vi.c

1303

return (RREG32_SMC(ATI_REV_ID_FUSE_MACRO__ADDRESS) & ATI_REV_ID_FUSE_MACRO__MASK)

drivers/gpu/drm/amd/amdgpu/vi.c

1418

clock_cntl = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);

drivers/gpu/drm/amd/amdgpu/vi.c

1419

pc = RREG32_SMC(ixSMC_PC_C);

drivers/gpu/drm/amd/amdgpu/vi.c

1812

temp = data = RREG32_SMC(ixCGTT_ROM_CLK_CTRL0);

drivers/gpu/drm/amd/amdgpu/vi.c

2015

data = RREG32_SMC(ixCGTT_ROM_CLK_CTRL0);

drivers/gpu/drm/amd/amdgpu/vi.c

554

tmp = RREG32_SMC(ixCG_CLKPIN_CNTL_2);

drivers/gpu/drm/amd/amdgpu/vi.c

558

tmp = RREG32_SMC(ixCG_CLKPIN_CNTL);

drivers/gpu/drm/amd/amdgpu/vi.c

604

rom_cntl = RREG32_SMC(ixROM_CNTL);

drivers/gpu/drm/amd/amdgpu/vi.c

993

tmp = RREG32_SMC(cntl_reg);

drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c

2499

nbdpmconfig1 = RREG32_SMC(ixNB_DPM_CONFIG_1);

drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c

2528

tmp = RREG32_SMC(ixCG_THERMAL_INT_CTRL);

drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c

2859

(RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &

drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c

2869

tmp = (RREG32_SMC(ixSMU_VOLTAGE_STATUS) &

drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c

2946

temp = RREG32_SMC(0xC0300E0C);

drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c

3127

cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT_CTRL);

drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c

3132

cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT_CTRL);

drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c

3144

cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT_CTRL);

drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c

3149

cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT_CTRL);

drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c

3265

(RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &

drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c

416

data = RREG32_SMC(config_regs->offset);

drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c

717

u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT);

drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c

732

u32 sclk_pwrmgt_cntl = RREG32_SMC(ixSCLK_PWRMGT_CNTL);

drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c

743

u32 sclk_pwrmgt_cntl = RREG32_SMC(ixSCLK_PWRMGT_CNTL);

drivers/gpu/drm/amd/pm/legacy-dpm/kv_smc.c

63

*enable_mask = RREG32_SMC(ixSMC_SYSCON_MSG_ARG_0);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

2856

data = RREG32_SMC(offset);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

7606

cg_thermal_int = RREG32_SMC(mmCG_THERMAL_INT);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

7611

cg_thermal_int = RREG32_SMC(mmCG_THERMAL_INT);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

7623

cg_thermal_int = RREG32_SMC(mmCG_THERMAL_INT);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

7628

cg_thermal_int = RREG32_SMC(mmCG_THERMAL_INT);

drivers/gpu/drm/amd/pm/legacy-dpm/si_smc.c

119

u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);

drivers/gpu/drm/amd/pm/legacy-dpm/si_smc.c

135

tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL) |

drivers/gpu/drm/amd/pm/legacy-dpm/si_smc.c

149

u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);

drivers/gpu/drm/amd/pm/legacy-dpm/si_smc.c

161

u32 rst = RREG32_SMC(SMC_SYSCON_RESET_CNTL);

drivers/gpu/drm/amd/pm/legacy-dpm/si_smc.c

162

u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);

drivers/gpu/drm/amd/pm/legacy-dpm/si_smc.c

222

tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);

drivers/gpu/drm/radeon/ci_dpm.c

1054

duty100 = (RREG32_SMC(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;

drivers/gpu/drm/radeon/ci_dpm.c

1055

duty = (RREG32_SMC(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT;

drivers/gpu/drm/radeon/ci_dpm.c

1087

duty100 = (RREG32_SMC(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;

drivers/gpu/drm/radeon/ci_dpm.c

1096

tmp = RREG32_SMC(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;

drivers/gpu/drm/radeon/ci_dpm.c

1127

tmp = RREG32_SMC(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;

drivers/gpu/drm/radeon/ci_dpm.c

1144

tach_period = (RREG32_SMC(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT;

drivers/gpu/drm/radeon/ci_dpm.c

1173

tmp = RREG32_SMC(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK;

drivers/gpu/drm/radeon/ci_dpm.c

1189

tmp = RREG32_SMC(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;

drivers/gpu/drm/radeon/ci_dpm.c

1193

tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TMIN_MASK;

drivers/gpu/drm/radeon/ci_dpm.c

1213

tmp = RREG32_SMC(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK;

drivers/gpu/drm/radeon/ci_dpm.c

1218

tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;

drivers/gpu/drm/radeon/ci_dpm.c

1374

tmp = RREG32_SMC(GENERAL_PWRMGT);

drivers/gpu/drm/radeon/ci_dpm.c

1381

tmp = RREG32_SMC(GENERAL_PWRMGT);

drivers/gpu/drm/radeon/ci_dpm.c

1491

tmp = RREG32_SMC(GENERAL_PWRMGT);

drivers/gpu/drm/radeon/ci_dpm.c

1495

tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);

drivers/gpu/drm/radeon/ci_dpm.c

1552

tmp = RREG32_SMC(GENERAL_PWRMGT);

drivers/gpu/drm/radeon/ci_dpm.c

1556

tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);

drivers/gpu/drm/radeon/ci_dpm.c

1579

u32 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);

drivers/gpu/drm/radeon/ci_dpm.c

1763

if (RREG32_SMC(FIRMWARE_FLAGS) & INTERRUPTS_ENABLED)

drivers/gpu/drm/radeon/ci_dpm.c

1833

RREG32_SMC(CG_SPLL_FUNC_CNTL);

drivers/gpu/drm/radeon/ci_dpm.c

1835

RREG32_SMC(CG_SPLL_FUNC_CNTL_2);

drivers/gpu/drm/radeon/ci_dpm.c

1837

RREG32_SMC(CG_SPLL_FUNC_CNTL_3);

drivers/gpu/drm/radeon/ci_dpm.c

1839

RREG32_SMC(CG_SPLL_FUNC_CNTL_4);

drivers/gpu/drm/radeon/ci_dpm.c

1841

RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM);

drivers/gpu/drm/radeon/ci_dpm.c

1843

RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM_2);

drivers/gpu/drm/radeon/ci_dpm.c

1865

u32 tmp = RREG32_SMC(GENERAL_PWRMGT);

drivers/gpu/drm/radeon/ci_dpm.c

1876

u32 tmp = RREG32_SMC(GENERAL_PWRMGT);

drivers/gpu/drm/radeon/ci_dpm.c

1945

u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL);

drivers/gpu/drm/radeon/ci_dpm.c

1984

tmp = RREG32_SMC(GENERAL_PWRMGT);

drivers/gpu/drm/radeon/ci_dpm.c

1989

tmp = RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM);

drivers/gpu/drm/radeon/ci_dpm.c

1993

tmp = RREG32_SMC(GENERAL_PWRMGT);

drivers/gpu/drm/radeon/ci_dpm.c

2006

u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL);

drivers/gpu/drm/radeon/ci_dpm.c

2019

tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);

drivers/gpu/drm/radeon/ci_dpm.c

2037

tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);

drivers/gpu/drm/radeon/ci_dpm.c

2057

if (RREG32_SMC(RCU_UC_EVENTS) & BOOT_SEQ_DONE)

drivers/gpu/drm/radeon/ci_dpm.c

2443

tmp = (RREG32_SMC(SMC_SCRATCH9) & 0x0000ff00) >> 8;

drivers/gpu/drm/radeon/ci_dpm.c

4040

tmp = RREG32_SMC(DPM_TABLE_475);

drivers/gpu/drm/radeon/ci_dpm.c

4078

tmp = RREG32_SMC(DPM_TABLE_475);

drivers/gpu/drm/radeon/ci_dpm.c

4108

tmp = RREG32_SMC(DPM_TABLE_475);

drivers/gpu/drm/radeon/ci_dpm.c

4175

tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) &

drivers/gpu/drm/radeon/ci_dpm.c

4194

tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &

drivers/gpu/drm/radeon/ci_dpm.c

4213

tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &

drivers/gpu/drm/radeon/ci_dpm.c

4230

tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &

drivers/gpu/drm/radeon/ci_dpm.c

4245

tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &

drivers/gpu/drm/radeon/ci_dpm.c

4260

tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) &

drivers/gpu/drm/radeon/ci_dpm.c

4741

u32 tmp = RREG32_SMC(GENERAL_PWRMGT);

drivers/gpu/drm/radeon/ci_dpm.c

554

data = RREG32_SMC(config_regs->offset);

drivers/gpu/drm/radeon/ci_dpm.c

5801

u32 tmp = RREG32_SMC(CNB_PWRMGT_CNTL);

drivers/gpu/drm/radeon/ci_dpm.c

856

tmp = RREG32_SMC(CG_THERMAL_INT);

drivers/gpu/drm/radeon/ci_dpm.c

864

tmp = RREG32_SMC(CG_THERMAL_CTRL);

drivers/gpu/drm/radeon/ci_dpm.c

879

u32 thermal_int = RREG32_SMC(CG_THERMAL_INT);

drivers/gpu/drm/radeon/ci_dpm.c

911

tmp = (RREG32_SMC(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;

drivers/gpu/drm/radeon/ci_dpm.c

913

tmp = (RREG32_SMC(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;

drivers/gpu/drm/radeon/ci_dpm.c

918

tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TMIN_MASK;

drivers/gpu/drm/radeon/ci_dpm.c

922

tmp = RREG32_SMC(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;

drivers/gpu/drm/radeon/ci_dpm.c

943

duty100 = (RREG32_SMC(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;

drivers/gpu/drm/radeon/ci_dpm.c

987

tmp = (RREG32_SMC(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;

drivers/gpu/drm/radeon/ci_smc.c

116

u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);

drivers/gpu/drm/radeon/ci_smc.c

124

u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);

drivers/gpu/drm/radeon/ci_smc.c

139

u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);

drivers/gpu/drm/radeon/ci_smc.c

148

u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);

drivers/gpu/drm/radeon/ci_smc.c

157

u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);

drivers/gpu/drm/radeon/ci_smc.c

158

u32 pc_c = RREG32_SMC(SMC_PC_C);

drivers/gpu/drm/radeon/ci_smc.c

176

tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);

drivers/gpu/drm/radeon/cik.c

1710

if (RREG32_SMC(GENERAL_PWRMGT) & GPU_COUNTER_CLK)

drivers/gpu/drm/radeon/cik.c

1713

if (RREG32_SMC(CG_CLKPIN_CNTL) & XTALIN_DIVIDE)

drivers/gpu/drm/radeon/cik.c

207

temp = (RREG32_SMC(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >>

drivers/gpu/drm/radeon/cik.c

224

temp = RREG32_SMC(0xC0300E0C);

drivers/gpu/drm/radeon/cik.c

9437

tmp = RREG32_SMC(cntl_reg);

drivers/gpu/drm/radeon/cik.c

9443

if (RREG32_SMC(status_reg) & DCLK_STATUS)

drivers/gpu/drm/radeon/cik.c

9477

if (RREG32_SMC(CG_ECLK_STATUS) & ECLK_STATUS)

drivers/gpu/drm/radeon/cik.c

9484

tmp = RREG32_SMC(CG_ECLK_CNTL);

drivers/gpu/drm/radeon/cik.c

9490

if (RREG32_SMC(CG_ECLK_STATUS) & ECLK_STATUS)

drivers/gpu/drm/radeon/cik.c

9756

orig = data = RREG32_SMC(THM_CLK_CNTL);

drivers/gpu/drm/radeon/cik.c

9762

orig = data = RREG32_SMC(MISC_CLK_CTRL);

drivers/gpu/drm/radeon/cik.c

9768

orig = data = RREG32_SMC(CG_CLKPIN_CNTL);

drivers/gpu/drm/radeon/cik.c

9773

orig = data = RREG32_SMC(CG_CLKPIN_CNTL_2);

drivers/gpu/drm/radeon/cik.c

9778

orig = data = RREG32_SMC(MPLL_BYPASSCLK_SEL);

drivers/gpu/drm/radeon/kv_dpm.c

1018

thermal_int = RREG32_SMC(CG_THERMAL_INT_CTRL);

drivers/gpu/drm/radeon/kv_dpm.c

173

data = RREG32_SMC(config_regs->offset);

drivers/gpu/drm/radeon/kv_dpm.c

2237

nbdpmconfig1 = RREG32_SMC(NB_DPM_CONFIG_1);

drivers/gpu/drm/radeon/kv_dpm.c

2264

tmp = RREG32_SMC(CG_THERMAL_INT_CTRL);

drivers/gpu/drm/radeon/kv_dpm.c

2601

(RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_SCLK_INDEX_MASK) >>

drivers/gpu/drm/radeon/kv_dpm.c

2610

tmp = (RREG32_SMC(SMU_VOLTAGE_STATUS) & SMU_VOLTAGE_CURRENT_LEVEL_MASK) >>

drivers/gpu/drm/radeon/kv_dpm.c

2624

(RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_SCLK_INDEX_MASK) >>

drivers/gpu/drm/radeon/kv_dpm.c

487

u32 tmp = RREG32_SMC(GENERAL_PWRMGT);

drivers/gpu/drm/radeon/kv_dpm.c

502

u32 sclk_pwrmgt_cntl = RREG32_SMC(SCLK_PWRMGT_CNTL);

drivers/gpu/drm/radeon/kv_dpm.c

512

u32 sclk_pwrmgt_cntl = RREG32_SMC(SCLK_PWRMGT_CNTL);

drivers/gpu/drm/radeon/kv_smc.c

60

*enable_mask = RREG32_SMC(SMC_SYSCON_MSG_ARG_0);

drivers/gpu/drm/radeon/ni.c

856

u32 temp = RREG32_SMC(TN_CURRENT_GNB_TEMP) & 0x7ff;

drivers/gpu/drm/radeon/radeon.h

2553

uint32_t tmp_ = RREG32_SMC(reg); \

drivers/gpu/drm/radeon/si.c

7444

if ((RREG32_SMC(CG_VCEPLL_FUNC_CNTL) & mask) == mask)

drivers/gpu/drm/radeon/si_dpm.c

2686

data = RREG32_SMC(offset);

drivers/gpu/drm/radeon/si_smc.c

115

u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);

drivers/gpu/drm/radeon/si_smc.c

131

tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);

drivers/gpu/drm/radeon/si_smc.c

145

u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);

drivers/gpu/drm/radeon/si_smc.c

154

u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);

drivers/gpu/drm/radeon/si_smc.c

163

u32 rst = RREG32_SMC(SMC_SYSCON_RESET_CNTL);

drivers/gpu/drm/radeon/si_smc.c

164

u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);

drivers/gpu/drm/radeon/si_smc.c

202

tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);

drivers/gpu/drm/radeon/trinity_dpm.c

1132

(RREG32_SMC(CC_SMU_MISC_FUSES) & MinSClkDid_MASK) >> MinSClkDid_SHIFT;

drivers/gpu/drm/radeon/trinity_dpm.c

1143

nbpsconfig = RREG32_SMC(NB_PSTATE_CONFIG);

drivers/gpu/drm/radeon/trinity_dpm.c

1265

u32 svi_mode = (RREG32_SMC(PM_CONFIG) & SVI_Mode) ? 1 : 0;

drivers/gpu/drm/radeon/trinity_dpm.c

1594

(RREG32_SMC(GPU_CAC_AVRG_CNTL) & WINDOW_SIZE_MASK) >> WINDOW_SIZE_SHIFT;

drivers/gpu/drm/radeon/trinity_dpm.c

330

value = RREG32_SMC(GFX_POWER_GATING_CNTL);

drivers/gpu/drm/radeon/trinity_dpm.c

458

if (RREG32_SMC(CC_SMU_TST_EFUSE1_MISC) & RB_BACKEND_DISABLE_MASK)

drivers/gpu/drm/radeon/trinity_dpm.c

459

WREG32_SMC(SMU_SCRATCH_A, (RREG32_SMC(SMU_SCRATCH_A) | 0x01));

drivers/gpu/drm/radeon/trinity_dpm.c

474

value = RREG32_SMC(PM_I_CNTL_1);

drivers/gpu/drm/radeon/trinity_dpm.c

479

value = RREG32_SMC(SMU_S_PG_CNTL);

drivers/gpu/drm/radeon/trinity_dpm.c

484

value = RREG32_SMC(SMU_S_PG_CNTL);

drivers/gpu/drm/radeon/trinity_dpm.c

488

value = RREG32_SMC(PM_I_CNTL_1);

drivers/gpu/drm/radeon/trinity_dpm.c

548

value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix);

drivers/gpu/drm/radeon/trinity_dpm.c

558

value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_PG_CNTL + ix);

drivers/gpu/drm/radeon/trinity_dpm.c

570

value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix);

drivers/gpu/drm/radeon/trinity_dpm.c

582

value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix);

drivers/gpu/drm/radeon/trinity_dpm.c

595

value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix);

drivers/gpu/drm/radeon/trinity_dpm.c

600

value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix);

drivers/gpu/drm/radeon/trinity_dpm.c

612

value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_3 + ix);

drivers/gpu/drm/radeon/trinity_dpm.c

624

value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_3 + ix);

drivers/gpu/drm/radeon/trinity_dpm.c

636

value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix);

drivers/gpu/drm/radeon/trinity_dpm.c

648

value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix);

drivers/gpu/drm/radeon/trinity_dpm.c

660

value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_AT + ix);

drivers/gpu/drm/radeon/trinity_dpm.c

691

value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix);

drivers/gpu/drm/radeon/trinity_dpm.c

700

if (RREG32_SMC(SMU_SCLK_DPM_CNTL) & SCLK_DPM_EN(1))

drivers/gpu/drm/radeon/trinity_dpm.c

708

u32 value = RREG32_SMC(SMU_SCLK_DPM_CNTL);

drivers/gpu/drm/radeon/trinity_dpm.c

747

sclk_dpm_cntl = RREG32_SMC(SMU_SCLK_DPM_CNTL);

drivers/gpu/drm/radeon/trinity_dpm.c

837

u32 tp = RREG32_SMC(PM_TP);

drivers/gpu/drm/radeon/trinity_dpm.c

960

u32 value = RREG32_SMC(SMU_SCLK_DPM_TTT);

drivers/gpu/drm/radeon/trinity_dpm.c

970

u32 value = RREG32_SMC(SMU_SCLK_DPM_TT_CNTL);

drivers/gpu/drm/radeon/trinity_dpm.c

980

u32 tp = RREG32_SMC(PM_TP);

drivers/gpu/drm/radeon/trinity_dpm.c

989

value = RREG32_SMC(PM_I_CNTL_1);