drivers/gpu/drm/amd/amdgpu/amdgpu.h

1408

uint32_t tmp_ = RREG32_PLL(reg); \

drivers/gpu/drm/radeon/r100.c

2719

tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);

drivers/gpu/drm/radeon/r100.c

3893

tmp = RREG32_PLL(R_00000D_SCLK_CNTL);

drivers/gpu/drm/radeon/r100.c

391

sclk_cntl = RREG32_PLL(SCLK_CNTL);

drivers/gpu/drm/radeon/r100.c

392

sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);

drivers/gpu/drm/radeon/r100.c

394

sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);

drivers/gpu/drm/radeon/r300.c

1364

tmp = RREG32_PLL(R_00000D_SCLK_CNTL);

drivers/gpu/drm/radeon/r420.c

200

sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL);

drivers/gpu/drm/radeon/radeon.h

2546

uint32_t tmp_ = RREG32_PLL(reg); \

drivers/gpu/drm/radeon/radeon_clocks.c

122

p1pll->reference_div = RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;

drivers/gpu/drm/radeon/radeon_clocks.c

152

RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &

drivers/gpu/drm/radeon/radeon_clocks.c

200

u32 tmp = RREG32_PLL(RADEON_PPLL_REF_DIV);

drivers/gpu/drm/radeon/radeon_clocks.c

216

RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &

drivers/gpu/drm/radeon/radeon_clocks.c

242

RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;

drivers/gpu/drm/radeon/radeon_clocks.c

268

RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &

drivers/gpu/drm/radeon/radeon_clocks.c

360

RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &

drivers/gpu/drm/radeon/radeon_clocks.c

400

tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL);

drivers/gpu/drm/radeon/radeon_clocks.c

404

tmp = RREG32_PLL(RADEON_SCLK_CNTL);

drivers/gpu/drm/radeon/radeon_clocks.c

410

tmp = RREG32_PLL(RADEON_SPLL_CNTL);

drivers/gpu/drm/radeon/radeon_clocks.c

416

tmp = RREG32_PLL(RADEON_SPLL_CNTL);

drivers/gpu/drm/radeon/radeon_clocks.c

422

tmp = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV);

drivers/gpu/drm/radeon/radeon_clocks.c

428

tmp = RREG32_PLL(RADEON_SPLL_CNTL);

drivers/gpu/drm/radeon/radeon_clocks.c

436

tmp = RREG32_PLL(RADEON_SPLL_CNTL);

drivers/gpu/drm/radeon/radeon_clocks.c

442

tmp = RREG32_PLL(RADEON_SPLL_CNTL);

drivers/gpu/drm/radeon/radeon_clocks.c

448

tmp = RREG32_PLL(RADEON_SCLK_CNTL);

drivers/gpu/drm/radeon/radeon_clocks.c

45

fb_div = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV);

drivers/gpu/drm/radeon/radeon_clocks.c

469

tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL);

drivers/gpu/drm/radeon/radeon_clocks.c

482

tmp = RREG32_PLL(RADEON_SCLK_CNTL);

drivers/gpu/drm/radeon/radeon_clocks.c

500

tmp = RREG32_PLL(RADEON_SCLK_CNTL);

drivers/gpu/drm/radeon/radeon_clocks.c

51

RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK;

drivers/gpu/drm/radeon/radeon_clocks.c

521

tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);

drivers/gpu/drm/radeon/radeon_clocks.c

526

tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);

drivers/gpu/drm/radeon/radeon_clocks.c

531

tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);

drivers/gpu/drm/radeon/radeon_clocks.c

547

tmp = RREG32_PLL(R300_SCLK_CNTL2);

drivers/gpu/drm/radeon/radeon_clocks.c

556

tmp = RREG32_PLL(RADEON_SCLK_CNTL);

drivers/gpu/drm/radeon/radeon_clocks.c

574

tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);

drivers/gpu/drm/radeon/radeon_clocks.c

579

tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);

drivers/gpu/drm/radeon/radeon_clocks.c

58

post_div = RREG32_PLL(RADEON_SCLK_CNTL) & RADEON_SCLK_SRC_SEL_MASK;

drivers/gpu/drm/radeon/radeon_clocks.c

584

tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);

drivers/gpu/drm/radeon/radeon_clocks.c

600

tmp = RREG32_PLL(RADEON_MCLK_MISC);

drivers/gpu/drm/radeon/radeon_clocks.c

605

tmp = RREG32_PLL(RADEON_MCLK_CNTL);

drivers/gpu/drm/radeon/radeon_clocks.c

620

tmp = RREG32_PLL(RADEON_MCLK_CNTL);

drivers/gpu/drm/radeon/radeon_clocks.c

637

tmp = RREG32_PLL(RADEON_SCLK_CNTL);

drivers/gpu/drm/radeon/radeon_clocks.c

643

tmp = RREG32_PLL(R300_SCLK_CNTL2);

drivers/gpu/drm/radeon/radeon_clocks.c

650

tmp = RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);

drivers/gpu/drm/radeon/radeon_clocks.c

661

tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL);

drivers/gpu/drm/radeon/radeon_clocks.c

669

tmp = RREG32_PLL(RADEON_SCLK_CNTL);

drivers/gpu/drm/radeon/radeon_clocks.c

692

tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);

drivers/gpu/drm/radeon/radeon_clocks.c

713

tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);

drivers/gpu/drm/radeon/radeon_clocks.c

720

tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);

drivers/gpu/drm/radeon/radeon_clocks.c

732

tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);

drivers/gpu/drm/radeon/radeon_clocks.c

742

tmp = RREG32_PLL(RADEON_SCLK_CNTL);

drivers/gpu/drm/radeon/radeon_clocks.c

75

fb_div = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV);

drivers/gpu/drm/radeon/radeon_clocks.c

753

tmp = RREG32_PLL(RADEON_SCLK_CNTL);

drivers/gpu/drm/radeon/radeon_clocks.c

764

tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);

drivers/gpu/drm/radeon/radeon_clocks.c

768

tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);

drivers/gpu/drm/radeon/radeon_clocks.c

774

tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);

drivers/gpu/drm/radeon/radeon_clocks.c

792

tmp = RREG32_PLL(R300_SCLK_CNTL2);

drivers/gpu/drm/radeon/radeon_clocks.c

797

tmp = RREG32_PLL(RADEON_SCLK_CNTL);

drivers/gpu/drm/radeon/radeon_clocks.c

808

tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);

drivers/gpu/drm/radeon/radeon_clocks.c

81

RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK;

drivers/gpu/drm/radeon/radeon_clocks.c

812

tmp = RREG32_PLL(RADEON_MCLK_CNTL);

drivers/gpu/drm/radeon/radeon_clocks.c

819

tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);

drivers/gpu/drm/radeon/radeon_clocks.c

825

tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);

drivers/gpu/drm/radeon/radeon_clocks.c

842

tmp = RREG32_PLL(RADEON_SCLK_CNTL);

drivers/gpu/drm/radeon/radeon_clocks.c

873

tmp = RREG32_PLL(R300_SCLK_CNTL2);

drivers/gpu/drm/radeon/radeon_clocks.c

88

post_div = RREG32_PLL(RADEON_MCLK_CNTL) & 0x7;

drivers/gpu/drm/radeon/radeon_clocks.c

882

tmp = RREG32_PLL(RADEON_MCLK_CNTL);

drivers/gpu/drm/radeon/radeon_clocks.c

892

tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);

drivers/gpu/drm/radeon/radeon_clocks.c

898

tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);

drivers/gpu/drm/radeon/radeon_clocks.c

910

tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);

drivers/gpu/drm/radeon/radeon_combios.c

1131

ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);

drivers/gpu/drm/radeon/radeon_combios.c

1136

RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;

drivers/gpu/drm/radeon/radeon_combios.c

2971

val = RREG32_PLL(reg);

drivers/gpu/drm/radeon/radeon_combios.c

3050

(RREG32_PLL

drivers/gpu/drm/radeon/radeon_combios.c

3100

tmp = RREG32_PLL(addr);

drivers/gpu/drm/radeon/radeon_combios.c

3118

(RREG32_PLL

drivers/gpu/drm/radeon/radeon_combios.c

3126

if (RREG32_PLL

drivers/gpu/drm/radeon/radeon_combios.c

3134

RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);

drivers/gpu/drm/radeon/radeon_combios.c

3138

RREG32_PLL

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

224

RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

232

while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

251

RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

259

while (RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

844

uint32_t pixclks_cntl = ((RREG32_PLL(RADEON_PIXCLKS_CNTL) &

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

893

RREG32_PLL(RADEON_P2PLL_CNTL));

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

912

pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

924

if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) &&

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

925

(pll_fb_post_div == (RREG32_PLL(RADEON_PPLL_DIV_3) &

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

999

RREG32_PLL(RADEON_PPLL_CNTL));

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

120

pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1576

pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

653

vclk_ecp_cntl = RREG32_PLL(RADEON_VCLK_ECP_CNTL);

drivers/gpu/drm/radeon/radeon_legacy_tv.c

285

save_pll_test = RREG32_PLL(RADEON_PLL_TEST_CNTL);

drivers/gpu/drm/radeon/rs600.c

259

dyn_pwrmgt_sclk_length = RREG32_PLL(DYN_PWRMGT_SCLK_LENGTH);

drivers/gpu/drm/radeon/rs600.c

276

dyn_sclk_vol_cntl = RREG32_PLL(DYN_SCLK_VOL_CNTL);

drivers/gpu/drm/radeon/rs600.c

288

hdp_dyn_cntl = RREG32_PLL(HDP_DYN_CNTL);

drivers/gpu/drm/radeon/rs600.c

296

mc_host_dyn_cntl = RREG32_PLL(MC_HOST_DYN_CNTL);

drivers/gpu/drm/radeon/rs600.c

303

dyn_backbias_cntl = RREG32_PLL(DYN_BACKBIAS_CNTL);

drivers/gpu/drm/radeon/rv515.c

480

RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1));

drivers/gpu/drm/radeon/rv515.c

482

RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1));

drivers/gpu/drm/radeon/rv515.c

484

RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1));