RREG32_PCIE
return RREG32_PCIE(index);
value = RREG32_PCIE(*pos);
data = RREG32_PCIE(xgmi_pcs_err_status_reg_arct[i]);
data = RREG32_PCIE(wafl_pcs_err_status_reg_arct[i]);
data = RREG32_PCIE(xgmi_pcs_err_status_reg_vg20[i]);
data = RREG32_PCIE(wafl_pcs_err_status_reg_vg20[i]);
data = RREG32_PCIE(xgmi3x16_pcs_err_status_reg_aldebaran[i]);
RREG32_PCIE(xgmi3x16_pcs_err_noncorrectable_mask_reg_aldebaran[i]);
data = RREG32_PCIE(walf_pcs_err_status_reg_aldebaran[i]);
RREG32_PCIE(walf_pcs_err_noncorrectable_mask_reg_aldebaran[i]);
data = RREG32_PCIE(xgmi3x16_pcs_err_status_reg_v6_4[i]);
RREG32_PCIE(xgmi3x16_pcs_err_noncorrectable_mask_reg_v6_4[i]);
regdata->value = RREG32_PCIE(smn_addr);
speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL);
tmp = RREG32_PCIE(ixPCIE_LC_STATUS1);
tmp = RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL);
tmp = RREG32_PCIE(ixPCIE_LC_CNTL4);
tmp = RREG32_PCIE(ixPCIE_LC_CNTL4);
tmp = RREG32_PCIE(ixPCIE_LC_CNTL4);
speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL);
speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL);
orig = data = RREG32_PCIE(ixPCIE_LC_N_FTS_CNTL);
orig = data = RREG32_PCIE(ixPCIE_LC_CNTL3);
orig = data = RREG32_PCIE(ixPCIE_P_CNTL);
orig = data = RREG32_PCIE(ixPCIE_LC_CNTL);
orig = data = RREG32_PCIE(ixPB0_PIF_PWRDOWN_0);
orig = data = RREG32_PCIE(ixPB0_PIF_PWRDOWN_1);
orig = data = RREG32_PCIE(ixPB1_PIF_PWRDOWN_0);
orig = data = RREG32_PCIE(ixPB1_PIF_PWRDOWN_1);
orig = data = RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL);
orig = data = RREG32_PCIE(ixPCIE_LC_CNTL2);
orig = data = RREG32_PCIE(ixPCIE_CNTL2);
data = RREG32_PCIE(ixPCIE_LC_N_FTS_CNTL);
data = RREG32_PCIE(ixPCIE_LC_STATUS1);
orig = data = RREG32_PCIE(ixPCIE_LC_CNTL);
tmp = RREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK);
*count0 = RREG32_PCIE(ixPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
*count1 = RREG32_PCIE(ixPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
nak_r = RREG32_PCIE(ixPCIE_RX_NUM_NAK);
nak_g = RREG32_PCIE(ixPCIE_RX_NUM_NAK_GENERATED);
orig = data = RREG32_PCIE(ixPCIE_CNTL2);
orig = data = RREG32_PCIE(ixPCIE_CNTL2);
def = data = RREG32_PCIE(smnCPM_CONTROL);
def = data = RREG32_PCIE(smnPCIE_CNTL2);
data = RREG32_PCIE(smnCPM_CONTROL);
data = RREG32_PCIE(smnPCIE_CNTL2);
def = data = RREG32_PCIE(smnPCIE_CONFIG_CNTL);
def = data = RREG32_PCIE(smnPCIE_LC_CNTL);
def = data = RREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL);
def = data = RREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2);
def = data = RREG32_PCIE(smnPCIE_LC_CNTL);
def = data = RREG32_PCIE(smnPCIE_LC_CNTL7);
def = data = RREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK);
def = data = RREG32_PCIE(smnPCIE_LC_CNTL3);
def = data = RREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2);
def = data = RREG32_PCIE(smnPSWUSP0_PCIE_LC_CNTL2);
def = data = RREG32_PCIE(smnPCIE_LC_CNTL6);
def = data = RREG32_PCIE(smnPCIE_LC_CNTL);
def = data = RREG32_PCIE(smnPCIE_LC_CNTL3);
reg_data = RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL);
reg_data = RREG32_PCIE(smnPCIE_LC_CNTL6);
reg_data = RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL);
def = data = RREG32_PCIE(smnCPM_CONTROL);
def = data = RREG32_PCIE(smnPCIE_CNTL2);
data = RREG32_PCIE(smnCPM_CONTROL);
data = RREG32_PCIE(smnPCIE_CNTL2);
def = data = RREG32_PCIE(smnPCIE_CONFIG_CNTL);
def = data = RREG32_PCIE(smnPCIE_CI_CNTL);
def = data = RREG32_PCIE(smnRCC_BIF_STRAP2);
def = data = RREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL);
def = data = RREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2);
def = data = RREG32_PCIE(smnPCIE_LC_CNTL);
def = data = RREG32_PCIE(smnPCIE_LC_CNTL7);
def = data = RREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK);
def = data = RREG32_PCIE(smnPCIE_LC_CNTL3);
def = data = RREG32_PCIE(smnRCC_BIF_STRAP3);
def = data = RREG32_PCIE(smnRCC_BIF_STRAP5);
def = data = RREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2);
def = data = RREG32_PCIE(smnPSWUSP0_PCIE_LC_CNTL2);
def = data = RREG32_PCIE(smnPCIE_LC_CNTL6);
def = data = RREG32_PCIE(smnRCC_BIF_STRAP3);
def = data = RREG32_PCIE(smnRCC_BIF_STRAP5);
def = data = RREG32_PCIE(smnPCIE_LC_CNTL);
def = data = RREG32_PCIE(smnPCIE_LC_CNTL3);
def = data = RREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK);
def = data = RREG32_PCIE(smnPCIE_CNTL2);
data = RREG32_PCIE(smnCPM_CONTROL);
data = RREG32_PCIE(smnPCIE_CNTL2);
def = data = RREG32_PCIE(smnPCIE_CNTL2);
data = RREG32_PCIE(smnCPM_CONTROL);
data = RREG32_PCIE(smnPCIE_CNTL2);
global_sts = RREG32_PCIE(smnRAS_GLOBAL_STATUS_LO_ALDE);
global_sts = RREG32_PCIE(smnRAS_GLOBAL_STATUS_LO);
parity_sts = RREG32_PCIE(smnPARITY_ERROR_STATUS_UNCORR_GRP2_ALDE);
parity_sts = RREG32_PCIE(smnPARITY_ERROR_STATUS_UNCORR_GRP2);
central_sts = RREG32_PCIE(smnBIFL_RAS_CENTRAL_STATUS);
int_eoi = RREG32_PCIE(smnIOHC_INTERRUPT_EOI);
def = data = RREG32_PCIE(smnRCC_BIF_STRAP2);
def = data = RREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL);
def = data = RREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2);
def = data = RREG32_PCIE(smnPCIE_LC_CNTL);
def = data = RREG32_PCIE(smnPCIE_LC_CNTL7);
def = data = RREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK);
def = data = RREG32_PCIE(smnPCIE_LC_CNTL3);
def = data = RREG32_PCIE(smnRCC_BIF_STRAP3);
def = data = RREG32_PCIE(smnRCC_BIF_STRAP5);
def = data = RREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2);
def = data = RREG32_PCIE(smnPSWUSP0_PCIE_LC_CNTL2);
def = data = RREG32_PCIE(smnPCIE_LC_CNTL6);
def = data = RREG32_PCIE(smnRCC_BIF_STRAP3);
def = data = RREG32_PCIE(smnRCC_BIF_STRAP5);
def = data = RREG32_PCIE(smnPCIE_LC_CNTL);
def = data = RREG32_PCIE(smnPCIE_LC_CNTL3);
reg = RREG32_PCIE(smnMP1_FIRMWARE_FLAGS | 0x03b00000);
tmp = RREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK);
*count0 = RREG32_PCIE(ixPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
*count1 = RREG32_PCIE(ixPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
nak_r = RREG32_PCIE(ixPCIE_RX_NUM_NAK);
nak_g = RREG32_PCIE(ixPCIE_RX_NUM_NAK_GENERATED);
tmp = RREG32_PCIE(ixPCIE_LC_STATUS1);
orig = data = RREG32_PCIE(ixPCIE_P_CNTL);
orig = data = RREG32_PCIE(ixPCIE_CNTL2);
data = RREG32_PCIE(ixPCIE_LC_STATUS1);
tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK);
*count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
*count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3);
*count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) | (cnt0_of << 32);
*count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK3) | (cnt1_of << 32);
nak_r = RREG32_PCIE(smnPCIE_RX_NUM_NAK);
nak_g = RREG32_PCIE(smnPCIE_RX_NUM_NAK_GENERATED);
ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr +
ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr +
ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4);
ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4);
ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4);
ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4);
rsmu_umc_val = RREG32_PCIE(rsmu_umc_addr * 4);
rsmu_umc_val = RREG32_PCIE(rsmu_umc_addr * 4);
rsmu_umc_val = RREG32_PCIE(rsmu_umc_addr * 4);
ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4);
ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4);
ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4);
ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr +
ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr +
ecc_ctrl = RREG32_PCIE((ecc_ctrl_addr +
ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4);
ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4);
ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4);
ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4);
ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr +
ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr +
ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4);
ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4);
ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4);
ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4);
orig = data = RREG32_PCIE(ixPCIE_LC_CNTL);
orig = data = RREG32_PCIE(ixPCIE_LC_CNTL);
orig = data = RREG32_PCIE(ixPCIE_LC_N_FTS_CNTL);
orig = data = RREG32_PCIE(ixPCIE_LC_CNTL3);
orig = data = RREG32_PCIE(ixPCIE_P_CNTL);
data = RREG32_PCIE(ixPCIE_LC_L1_PM_SUBSTATE);
orig = data = RREG32_PCIE(ixPCIE_LC_CNTL6);
orig = data = RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL);
orig = data = RREG32_PCIE(ixCPM_CONTROL);
orig = data = RREG32_PCIE(ixPCIE_CONFIG_CNTL);
orig = data = RREG32_PCIE(ixPCIE_LC_CNTL7);
orig = data = RREG32_PCIE(ixPCIE_HW_DEBUG);
orig = data = RREG32_PCIE(ixPCIE_LC_CNTL2);
data = RREG32_PCIE(ixPCIE_LC_N_FTS_CNTL);
data1 = RREG32_PCIE(ixPCIE_LC_STATUS1);
orig = data = RREG32_PCIE(ixPCIE_LC_CNTL);
orig = data = RREG32_PCIE(ixPCIE_LC_TRAINING_CNTL);
tmp = RREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK);
*count0 = RREG32_PCIE(ixPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
*count1 = RREG32_PCIE(ixPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
nak_r = RREG32_PCIE(ixPCIE_RX_NUM_NAK);
nak_g = RREG32_PCIE(ixPCIE_RX_NUM_NAK_GENERATED);
temp = data = RREG32_PCIE(ixPCIE_CNTL2);
data = RREG32_PCIE(ixPCIE_CNTL2);
return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
mp1_fw_flags = RREG32_PCIE(MP1_Public |
mp1_fw_flags = RREG32_PCIE(MP1_Public |
esm_ctrl = RREG32_PCIE(smnPCIE_ESM_CTRL);
mp0_fw_intf = RREG32_PCIE(MP0_Public |
reg = RREG32_PCIE(MP1_Public | smnMP1_PMI_3_START);
reg = RREG32_PCIE(MP1_Public | smnMP1_PMI_3_FIFO);
*p++ = cpu_to_le32(RREG32_PCIE(MP1_Public | smnMP1_PMI_3));
mp1_fw_flags = RREG32_PCIE(MP1_Public |
mp1_fw_flags = RREG32_PCIE(MP1_Public |
return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
mp1_fw_flags = RREG32_PCIE(MP1_Public |
esm_ctrl = RREG32_PCIE(smnPCIE_ESM_CTRL);
mp1_fw_flags = RREG32_PCIE(MP1_Public |
return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
ret = RREG32_PCIE(MP1_Public |
mp1_fw_flags = RREG32_PCIE(MP1_Public |
mp1_fw_flags = RREG32_PCIE(MP1_Public |
RREG32_PCIE(MP1_Public | (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
return REG_GET_FIELD(RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL),
esm_ctrl = RREG32_PCIE(smnPCIE_ESM_CTRL);
speed_level = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
mp1_fw_flags = RREG32_PCIE(MP1_Public |
mp1_fw_flags = RREG32_PCIE(MP1_Public |
mp1_fw_flags = RREG32_PCIE(MP1_Public |
mp1_fw_flags = RREG32_PCIE(MP1_Public |
mp1_fw_flags = RREG32_PCIE(MP1_Public |
mp1_fw_flags = RREG32_PCIE(MP1_Public |
mp1_fw_flags = RREG32_PCIE(MP1_Public |
tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE);
tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO);
tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI);
tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO);
tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI);
tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR);
tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
(void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
tmp = RREG32_PCIE(PCIE_P_CNTL);
tmp = RREG32_PCIE(PCIE_P_CNTL);
orig = data = RREG32_PCIE(PCIE_CNTL2);
tmp = RREG32_PCIE(PCIE_LC_STATUS1);
orig = data = RREG32_PCIE(PCIE_P_CNTL);
orig = data = RREG32_PCIE(PCIE_CNTL2);
data = RREG32_PCIE(PCIE_LC_STATUS1);