drivers/accel/habanalabs/common/command_submission.c

2550

RREG32(prop->hbw_flush_reg);

drivers/accel/habanalabs/common/decoder.c

53

irq_status = RREG32(dec->base_addr + VCMD_IRQ_STATUS_OFFSET);

drivers/accel/habanalabs/common/decoder.c

63

RREG32(dec->base_addr + VCMD_IRQ_STATUS_OFFSET);

drivers/accel/habanalabs/common/device.c

300

*val = RREG32(addr - cfg_region->region_base);

drivers/accel/habanalabs/common/device.c

306

val_l = RREG32(addr - cfg_region->region_base);

drivers/accel/habanalabs/common/device.c

307

val_h = RREG32(addr + sizeof(u32) - cfg_region->region_base);

drivers/accel/habanalabs/common/firmware_if.c

1577

reg_val = RREG32(pre_fw_load->sts_boot_dev_sts0_reg);

drivers/accel/habanalabs/common/firmware_if.c

1583

reg_val = RREG32(pre_fw_load->sts_boot_dev_sts1_reg);

drivers/accel/habanalabs/common/firmware_if.c

1615

ver_off = RREG32(static_loader->boot_fit_version_offset_reg);

drivers/accel/habanalabs/common/firmware_if.c

1621

ver_off = RREG32(static_loader->preboot_version_offset_reg);

drivers/accel/habanalabs/common/firmware_if.c

2440

RREG32(cpu_boot_dev_sts0_reg);

drivers/accel/habanalabs/common/firmware_if.c

2451

RREG32(cpu_boot_dev_sts1_reg);

drivers/accel/habanalabs/common/firmware_if.c

2636

prop->fw_app_cpu_boot_dev_sts0 = RREG32(cpu_boot_dev_sts0_reg);

drivers/accel/habanalabs/common/firmware_if.c

2655

prop->fw_app_cpu_boot_dev_sts1 = RREG32(cpu_boot_dev_sts1_reg);

drivers/accel/habanalabs/common/firmware_if.c

844

err_val = RREG32(boot_err0_reg);

drivers/accel/habanalabs/common/firmware_if.c

845

status_val = RREG32(cpu_boot_dev_status0_reg);

drivers/accel/habanalabs/common/firmware_if.c

848

err_val = RREG32(boot_err1_reg);

drivers/accel/habanalabs/common/firmware_if.c

849

status_val = RREG32(cpu_boot_dev_status1_reg);

drivers/accel/habanalabs/common/firmware_if.c

923

prop->fw_app_cpu_boot_dev_sts0 = RREG32(sts_boot_dev_sts0_reg);

drivers/accel/habanalabs/common/firmware_if.c

930

prop->fw_app_cpu_boot_dev_sts1 = RREG32(sts_boot_dev_sts1_reg);

drivers/accel/habanalabs/common/habanalabs.h

2635

u32 tmp_ = RREG32(reg); \

drivers/accel/habanalabs/common/habanalabs.h

2647

#define RREG32_MASK(reg, mask) ((RREG32(reg) & mask) >> __ffs(mask))

drivers/accel/habanalabs/common/habanalabs.h

2652

WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & \

drivers/accel/habanalabs/common/habanalabs.h

2673

(val) = RREG32(lower_32_bits(addr)); \

drivers/accel/habanalabs/common/habanalabs.h

2684

(val) = RREG32(lower_32_bits(addr)); \

drivers/accel/habanalabs/common/habanalabs.h

2733

__read_val = RREG32(lower_32_bits(addr_arr[__arr_idx])); \

drivers/accel/habanalabs/common/security.c

233

cause = RREG32(block_base + HL_BLOCK_GLBL_ERR_CAUSE);

drivers/accel/habanalabs/common/security.c

235

addr = RREG32(block_base + HL_BLOCK_GLBL_ERR_ADDR);

drivers/accel/habanalabs/common/security.c

694

cause_val = RREG32(glbl_err_cause);

drivers/accel/habanalabs/common/security.c

699

addr_val = RREG32(glbl_err_addr);

drivers/accel/habanalabs/common/state_dump.c

280

sync_objects[i] = RREG32(base_addr + i * sizeof(u32));

drivers/accel/habanalabs/common/state_dump.c

466

RREG32(base_addr + sds->props[SP_MON_OBJ_WR_ADDR_LOW] +

drivers/accel/habanalabs/common/state_dump.c

470

RREG32(base_addr + sds->props[SP_MON_OBJ_WR_ADDR_HIGH] +

drivers/accel/habanalabs/common/state_dump.c

474

RREG32(base_addr + sds->props[SP_MON_OBJ_WR_DATA] +

drivers/accel/habanalabs/common/state_dump.c

478

RREG32(base_addr + sds->props[SP_MON_OBJ_ARM_DATA] +

drivers/accel/habanalabs/common/state_dump.c

482

RREG32(base_addr + sds->props[SP_MON_OBJ_STATUS] +

drivers/accel/habanalabs/gaudi/gaudi.c

3878

prop->fw_app_cpu_boot_dev_sts0 = RREG32(mmCPU_BOOT_DEV_STS0);

drivers/accel/habanalabs/gaudi/gaudi.c

3880

prop->fw_app_cpu_boot_dev_sts1 = RREG32(mmCPU_BOOT_DEV_STS1);

drivers/accel/habanalabs/gaudi/gaudi.c

3889

RREG32(mmHW_STATE);

drivers/accel/habanalabs/gaudi/gaudi.c

3902

RREG32(mmPCIE_WRAP_LBW_PROT_OVR);

drivers/accel/habanalabs/gaudi/gaudi.c

3989

RREG32(mmHW_STATE);

drivers/accel/habanalabs/gaudi/gaudi.c

4132

status = RREG32(mmPSOC_GLOBAL_CONF_BTM_FSM);

drivers/accel/habanalabs/gaudi/gaudi.c

5616

err_cause = RREG32(mmDMA0_CORE_ERR_CAUSE);

drivers/accel/habanalabs/gaudi/gaudi.c

5640

err_cause = RREG32(mmDMA0_CORE_ERR_CAUSE);

drivers/accel/habanalabs/gaudi/gaudi.c

5921

err_cause = RREG32(mmDMA0_CORE_ERR_CAUSE + dma_offset);

drivers/accel/habanalabs/gaudi/gaudi.c

5956

dma_core_sts0 = RREG32(mmDMA0_CORE_STS0 + dma_offset);

drivers/accel/habanalabs/gaudi/gaudi.c

5957

qm_glbl_sts0 = RREG32(mmDMA0_QM_GLBL_STS0 + qm_offset);

drivers/accel/habanalabs/gaudi/gaudi.c

5958

qm_cgm_sts = RREG32(mmDMA0_QM_CGM_STS + qm_offset);

drivers/accel/habanalabs/gaudi/gaudi.c

5966

dma_core_sts0 = RREG32(mmDMA0_CORE_STS0 + dma_offset);

drivers/accel/habanalabs/gaudi/gaudi.c

5967

qm_glbl_sts0 = RREG32(mmDMA0_QM_GLBL_STS0 + qm_offset);

drivers/accel/habanalabs/gaudi/gaudi.c

5968

qm_cgm_sts = RREG32(mmDMA0_QM_CGM_STS + qm_offset);

drivers/accel/habanalabs/gaudi/gaudi.c

5980

cfg1 = RREG32(mmDMA0_QM_GLBL_CFG1 + qm_offset);

drivers/accel/habanalabs/gaudi/gaudi.c

5991

err_cause = RREG32(mmDMA0_CORE_ERR_CAUSE + dma_offset);

drivers/accel/habanalabs/gaudi/gaudi.c

6477

err_cause[i] = RREG32(mmDMA0_CORE_ERR_CAUSE + dma_offset);

drivers/accel/habanalabs/gaudi/gaudi.c

6544

val = is_write ? RREG32(mmMMU_UP_RAZWI_WRITE_ID) :

drivers/accel/habanalabs/gaudi/gaudi.c

6545

RREG32(mmMMU_UP_RAZWI_READ_ID);

drivers/accel/habanalabs/gaudi/gaudi.c

6660

if (RREG32(mmMMU_UP_RAZWI_WRITE_VLD)) {

drivers/accel/habanalabs/gaudi/gaudi.c

6668

if (RREG32(mmMMU_UP_RAZWI_READ_VLD)) {

drivers/accel/habanalabs/gaudi/gaudi.c

6685

val = RREG32(mmMMU_UP_PAGE_ERROR_CAPTURE);

drivers/accel/habanalabs/gaudi/gaudi.c

6689

*addr |= RREG32(mmMMU_UP_PAGE_ERROR_CAPTURE_VA);

drivers/accel/habanalabs/gaudi/gaudi.c

6697

val = RREG32(mmMMU_UP_ACCESS_ERROR_CAPTURE);

drivers/accel/habanalabs/gaudi/gaudi.c

6701

*addr |= RREG32(mmMMU_UP_ACCESS_ERROR_CAPTURE_VA);

drivers/accel/habanalabs/gaudi/gaudi.c

6751

err_word = RREG32(err_addr);

drivers/accel/habanalabs/gaudi/gaudi.c

6768

RREG32(params->block_address + GAUDI_ECC_ADDRESS_OFFSET);

drivers/accel/habanalabs/gaudi/gaudi.c

6770

RREG32(params->block_address + GAUDI_ECC_SYNDROME_OFFSET);

drivers/accel/habanalabs/gaudi/gaudi.c

6773

reg = RREG32(params->block_address + GAUDI_ECC_MEM_INFO_CLR_OFFSET);

drivers/accel/habanalabs/gaudi/gaudi.c

6827

cq_ptr = (((u64) RREG32(cq_ptr_hi)) << 32) | RREG32(cq_ptr_lo);

drivers/accel/habanalabs/gaudi/gaudi.c

6828

size = RREG32(cq_tsize);

drivers/accel/habanalabs/gaudi/gaudi.c

6873

ci = RREG32(pq_ci);

drivers/accel/habanalabs/gaudi/gaudi.c

6964

glbl_sts_val = RREG32(glbl_sts_addr + 4 * i);

drivers/accel/habanalabs/gaudi/gaudi.c

7000

arb_err_val = RREG32(arb_err_addr);

drivers/accel/habanalabs/gaudi/gaudi.c

7404

val2 = RREG32(base + ch * 0x1000 + 0x060);

drivers/accel/habanalabs/gaudi/gaudi.c

7408

RREG32(base + ch * 0x1000 + 0x064),

drivers/accel/habanalabs/gaudi/gaudi.c

7424

val2 = RREG32(base + ch * 0x1000 + 0x070);

drivers/accel/habanalabs/gaudi/gaudi.c

7428

RREG32(base + ch * 0x1000 + 0x074),

drivers/accel/habanalabs/gaudi/gaudi.c

7443

val = RREG32(base + 0x8F30);

drivers/accel/habanalabs/gaudi/gaudi.c

7444

val2 = RREG32(base + 0x8F34);

drivers/accel/habanalabs/gaudi/gaudi.c

7451

val = RREG32(base + 0x8F40);

drivers/accel/habanalabs/gaudi/gaudi.c

7452

val2 = RREG32(base + 0x8F44);

drivers/accel/habanalabs/gaudi/gaudi.c

7492

tpc_interrupts_cause = RREG32(mmTPC0_CFG_TPC_INTR_CAUSE + tpc_offset) &

drivers/accel/habanalabs/gaudi/gaudi.c

798

return RREG32(mmHW_STATE);

drivers/accel/habanalabs/gaudi/gaudi.c

8047

qm_glbl_sts0 = RREG32(mmDMA0_QM_GLBL_STS0 + offset);

drivers/accel/habanalabs/gaudi/gaudi.c

8048

qm_cgm_sts = RREG32(mmDMA0_QM_CGM_STS + offset);

drivers/accel/habanalabs/gaudi/gaudi.c

8049

dma_core_sts0 = RREG32(mmDMA0_CORE_STS0 + offset);

drivers/accel/habanalabs/gaudi/gaudi.c

8069

qm_glbl_sts0 = RREG32(mmTPC0_QM_GLBL_STS0 + offset);

drivers/accel/habanalabs/gaudi/gaudi.c

8070

qm_cgm_sts = RREG32(mmTPC0_QM_CGM_STS + offset);

drivers/accel/habanalabs/gaudi/gaudi.c

8071

tpc_cfg_sts = RREG32(mmTPC0_CFG_STATUS + offset);

drivers/accel/habanalabs/gaudi/gaudi.c

8091

mme_arch_sts = RREG32(mmMME0_CTRL_ARCH_STATUS + offset);

drivers/accel/habanalabs/gaudi/gaudi.c

8097

qm_glbl_sts0 = RREG32(mmMME0_QM_GLBL_STS0 + offset);

drivers/accel/habanalabs/gaudi/gaudi.c

8098

qm_cgm_sts = RREG32(mmMME0_QM_CGM_STS + offset);

drivers/accel/habanalabs/gaudi/gaudi.c

8127

qm_glbl_sts0 = RREG32(mmNIC0_QM0_GLBL_STS0 + offset);

drivers/accel/habanalabs/gaudi/gaudi.c

8128

qm_cgm_sts = RREG32(mmNIC0_QM0_CGM_STS + offset);

drivers/accel/habanalabs/gaudi/gaudi.c

8142

qm_glbl_sts0 = RREG32(mmNIC0_QM1_GLBL_STS0 + offset);

drivers/accel/habanalabs/gaudi/gaudi.c

8143

qm_cgm_sts = RREG32(mmNIC0_QM1_CGM_STS + offset);

drivers/accel/habanalabs/gaudi/gaudi.c

8778

u64 device_time = ((u64) RREG32(mmPSOC_TIMESTAMP_CNTCVU)) << 32;

drivers/accel/habanalabs/gaudi/gaudi.c

8780

return device_time | RREG32(mmPSOC_TIMESTAMP_CNTCVL);

drivers/accel/habanalabs/gaudi/gaudi.c

8866

reg_value = RREG32(sds->props[SP_TPC0_CFG_SO] +

drivers/accel/habanalabs/gaudi/gaudi.c

8879

reg_value = RREG32(sds->props[SP_MME_CFG_SO] +

drivers/accel/habanalabs/gaudi/gaudi.c

8893

reg_value = RREG32(sds->props[SP_DMA_CFG_SO] +

drivers/accel/habanalabs/gaudi/gaudi.c

9004

statuses[i] = RREG32(status_base_offset + i * sizeof(u32));

drivers/accel/habanalabs/gaudi/gaudi.c

9008

fences[i] = RREG32(base_offset + i * sizeof(u32));

drivers/accel/habanalabs/gaudi/gaudi.c

929

div_fctr = RREG32(mmPSOC_CPU_PLL_DIV_FACTOR_2);

drivers/accel/habanalabs/gaudi/gaudi.c

930

div_sel = RREG32(mmPSOC_CPU_PLL_DIV_SEL_2);

drivers/accel/habanalabs/gaudi/gaudi.c

931

nr = RREG32(mmPSOC_CPU_PLL_NR);

drivers/accel/habanalabs/gaudi/gaudi.c

932

nf = RREG32(mmPSOC_CPU_PLL_NF);

drivers/accel/habanalabs/gaudi/gaudi.c

933

od = RREG32(mmPSOC_CPU_PLL_OD);

drivers/accel/habanalabs/gaudi/gaudi_coresight.c

485

val = RREG32(base_reg + 0x20);

drivers/accel/habanalabs/gaudi/gaudi_coresight.c

490

val = RREG32(base_reg + 0x304);

drivers/accel/habanalabs/gaudi/gaudi_coresight.c

588

val = RREG32(mmPSOC_ETR_CTL);

drivers/accel/habanalabs/gaudi/gaudi_coresight.c

595

val = RREG32(mmPSOC_ETR_FFCR);

drivers/accel/habanalabs/gaudi/gaudi_coresight.c

686

rwp = RREG32(mmPSOC_ETR_RWP);

drivers/accel/habanalabs/gaudi/gaudi_coresight.c

687

rwphi = RREG32(mmPSOC_ETR_RWPHI) & 0xff;

drivers/accel/habanalabs/gaudi/gaudi_coresight.c

688

msb = RREG32(mmPSOC_GLOBAL_CONF_TRACE_ADDR) &

drivers/accel/habanalabs/gaudi/gaudi_coresight.c

850

output[i] = RREG32(base_reg + i * 8);

drivers/accel/habanalabs/gaudi/gaudi_coresight.c

852

output[overflow_idx] = RREG32(base_reg + 0xCC0);

drivers/accel/habanalabs/gaudi/gaudi_coresight.c

854

output[cycle_cnt_idx] = RREG32(base_reg + 0xFC);

drivers/accel/habanalabs/gaudi/gaudi_coresight.c

856

output[cycle_cnt_idx] |= RREG32(base_reg + 0xF8);

drivers/accel/habanalabs/gaudi/gaudi_coresight.c

898

RREG32(mmHW_STATE);

drivers/accel/habanalabs/gaudi2/gaudi2.c

10720

old_mmubp = RREG32(mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_MMU_BP);

drivers/accel/habanalabs/gaudi2/gaudi2.c

10942

val = RREG32(mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0 + offset);

drivers/accel/habanalabs/gaudi2/gaudi2.c

10961

RREG32(mmPDMA0_QM_ARB_CFG_0);

drivers/accel/habanalabs/gaudi2/gaudi2.c

10980

RREG32(mmPDMA0_QM_ARB_CFG_0);

drivers/accel/habanalabs/gaudi2/gaudi2.c

11486

u64 device_time = ((u64) RREG32(mmPSOC_TIMESTAMP_CNTCVU)) << 32;

drivers/accel/habanalabs/gaudi2/gaudi2.c

11488

return device_time | RREG32(mmPSOC_TIMESTAMP_CNTCVL);

drivers/accel/habanalabs/gaudi2/gaudi2.c

3028

bar_addr_high = RREG32(mmPCIE_DBI_BAR1_REG + STM_FLASH_ALIGNED_OFF);

drivers/accel/habanalabs/gaudi2/gaudi2.c

3029

bar_addr_low = RREG32(mmPCIE_DBI_BAR0_REG + STM_FLASH_ALIGNED_OFF) & ~0xF;

drivers/accel/habanalabs/gaudi2/gaudi2.c

3071

return RREG32(mmHW_STATE);

drivers/accel/habanalabs/gaudi2/gaudi2.c

5359

prop->fw_app_cpu_boot_dev_sts0 = RREG32(mmCPU_BOOT_DEV_STS0);

drivers/accel/habanalabs/gaudi2/gaudi2.c

5362

prop->fw_app_cpu_boot_dev_sts1 = RREG32(mmCPU_BOOT_DEV_STS1);

drivers/accel/habanalabs/gaudi2/gaudi2.c

6494

RREG32(mmHW_STATE);

drivers/accel/habanalabs/gaudi2/gaudi2.c

6555

RREG32(mmHW_STATE);

drivers/accel/habanalabs/gaudi2/gaudi2.c

6600

cpu_boot_status = RREG32(mmPSOC_GLOBAL_CONF_CPU_BOOT_STATUS);

drivers/accel/habanalabs/gaudi2/gaudi2.c

7530

dma_core_sts0 = RREG32(mmDCORE0_EDMA0_CORE_STS0 + offset);

drivers/accel/habanalabs/gaudi2/gaudi2.c

7531

dma_core_sts1 = RREG32(mmDCORE0_EDMA0_CORE_STS1 + offset);

drivers/accel/habanalabs/gaudi2/gaudi2.c

7533

qm_glbl_sts0 = RREG32(mmDCORE0_EDMA0_QM_GLBL_STS0 + offset);

drivers/accel/habanalabs/gaudi2/gaudi2.c

7534

qm_glbl_sts1 = RREG32(mmDCORE0_EDMA0_QM_GLBL_STS1 + offset);

drivers/accel/habanalabs/gaudi2/gaudi2.c

7535

qm_cgm_sts = RREG32(mmDCORE0_EDMA0_QM_CGM_STS + offset);

drivers/accel/habanalabs/gaudi2/gaudi2.c

7571

dma_core_sts0 = RREG32(mmPDMA0_CORE_STS0 + offset);

drivers/accel/habanalabs/gaudi2/gaudi2.c

7572

dma_core_sts1 = RREG32(mmPDMA0_CORE_STS1 + offset);

drivers/accel/habanalabs/gaudi2/gaudi2.c

7574

qm_glbl_sts0 = RREG32(mmPDMA0_QM_GLBL_STS0 + offset);

drivers/accel/habanalabs/gaudi2/gaudi2.c

7575

qm_glbl_sts1 = RREG32(mmPDMA0_QM_GLBL_STS1 + offset);

drivers/accel/habanalabs/gaudi2/gaudi2.c

7576

qm_cgm_sts = RREG32(mmPDMA0_QM_CGM_STS + offset);

drivers/accel/habanalabs/gaudi2/gaudi2.c

7621

qm_glbl_sts0 = RREG32(mmNIC0_QM0_GLBL_STS0 + offset);

drivers/accel/habanalabs/gaudi2/gaudi2.c

7622

qm_glbl_sts1 = RREG32(mmNIC0_QM0_GLBL_STS1 + offset);

drivers/accel/habanalabs/gaudi2/gaudi2.c

7623

qm_cgm_sts = RREG32(mmNIC0_QM0_CGM_STS + offset);

drivers/accel/habanalabs/gaudi2/gaudi2.c

7658

qm_glbl_sts0 = RREG32(mmDCORE0_MME_QM_GLBL_STS0 + offset);

drivers/accel/habanalabs/gaudi2/gaudi2.c

7659

qm_glbl_sts1 = RREG32(mmDCORE0_MME_QM_GLBL_STS1 + offset);

drivers/accel/habanalabs/gaudi2/gaudi2.c

7660

qm_cgm_sts = RREG32(mmDCORE0_MME_QM_CGM_STS + offset);

drivers/accel/habanalabs/gaudi2/gaudi2.c

7665

mme_arch_sts = RREG32(mmDCORE0_MME_CTRL_LO_ARCH_STATUS + offset);

drivers/accel/habanalabs/gaudi2/gaudi2.c

7696

tpc_cfg_sts = RREG32(mmDCORE0_TPC0_CFG_STATUS + offset);

drivers/accel/habanalabs/gaudi2/gaudi2.c

7697

qm_glbl_sts0 = RREG32(mmDCORE0_TPC0_QM_GLBL_STS0 + offset);

drivers/accel/habanalabs/gaudi2/gaudi2.c

7698

qm_glbl_sts1 = RREG32(mmDCORE0_TPC0_QM_GLBL_STS1 + offset);

drivers/accel/habanalabs/gaudi2/gaudi2.c

7699

qm_cgm_sts = RREG32(mmDCORE0_TPC0_QM_CGM_STS + offset);

drivers/accel/habanalabs/gaudi2/gaudi2.c

7771

dec_swreg15 = RREG32(mmDCORE0_DEC0_CMD_SWREG15 + offset);

drivers/accel/habanalabs/gaudi2/gaudi2.c

7797

dec_swreg15 = RREG32(mmPCIE_DEC0_CMD_SWREG15 + offset);

drivers/accel/habanalabs/gaudi2/gaudi2.c

7832

qm_glbl_sts0 = RREG32(mmROT0_QM_GLBL_STS0 + offset);

drivers/accel/habanalabs/gaudi2/gaudi2.c

7833

qm_glbl_sts1 = RREG32(mmROT0_QM_GLBL_STS1 + offset);

drivers/accel/habanalabs/gaudi2/gaudi2.c

7834

qm_cgm_sts = RREG32(mmROT0_QM_CGM_STS + offset);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8268

cp_sts = RREG32(qman_base + QM_CP_STS_4_OFFSET);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8272

lo = RREG32(qman_base + QM_ARC_CQ_PTR_LO_STS_OFFSET);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8273

hi = RREG32(qman_base + QM_ARC_CQ_PTR_HI_STS_OFFSET);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8275

cq_size = RREG32(qman_base + QM_ARC_CQ_TSIZE_STS_OFFSET);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8277

lo = RREG32(qman_base + QM_CQ_PTR_LO_STS_4_OFFSET);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8278

hi = RREG32(qman_base + QM_CQ_PTR_HI_STS_4_OFFSET);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8280

cq_size = RREG32(qman_base + QM_CQ_TSIZE_STS_4_OFFSET);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8283

lo = RREG32(qman_base + QM_CP_CURRENT_INST_LO_4_OFFSET);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8284

hi = RREG32(qman_base + QM_CP_CURRENT_INST_HI_4_OFFSET);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8314

glbl_sts_val = RREG32(glbl_sts_addr + 4 * i);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8346

arb_err_val = RREG32(arb_err_addr);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8373

razwi_hi = RREG32(rtr_mstr_if_base_addr + RR_SHRD_HBW_AW_RAZWI_HI);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8374

razwi_lo = RREG32(rtr_mstr_if_base_addr + RR_SHRD_HBW_AW_RAZWI_LO);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8375

razwi_xy = RREG32(rtr_mstr_if_base_addr + RR_SHRD_HBW_AW_RAZWI_XY);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8378

razwi_hi = RREG32(rtr_mstr_if_base_addr + RR_SHRD_HBW_AR_RAZWI_HI);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8379

razwi_lo = RREG32(rtr_mstr_if_base_addr + RR_SHRD_HBW_AR_RAZWI_LO);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8380

razwi_xy = RREG32(rtr_mstr_if_base_addr + RR_SHRD_HBW_AR_RAZWI_XY);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8402

razwi_addr += RREG32(rtr_mstr_if_base_addr + RR_SHRD_LBW_AW_RAZWI);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8403

razwi_xy = RREG32(rtr_mstr_if_base_addr + RR_SHRD_LBW_AW_RAZWI_XY);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8406

razwi_addr += RREG32(rtr_mstr_if_base_addr + RR_SHRD_LBW_AR_RAZWI);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8407

razwi_xy = RREG32(rtr_mstr_if_base_addr + RR_SHRD_LBW_AR_RAZWI_XY);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8585

hbw_shrd_aw = RREG32(hbw_rtr_mstr_if_base_addr + RR_SHRD_HBW_AW_RAZWI_HAPPENED);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8586

hbw_shrd_ar = RREG32(hbw_rtr_mstr_if_base_addr + RR_SHRD_HBW_AR_RAZWI_HAPPENED);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8587

lbw_shrd_aw = RREG32(lbw_rtr_mstr_if_base_addr + RR_SHRD_LBW_AW_RAZWI_HAPPENED);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8588

lbw_shrd_ar = RREG32(lbw_rtr_mstr_if_base_addr + RR_SHRD_LBW_AR_RAZWI_HAPPENED);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8718

if (RREG32(base[i] + DEC_RAZWI_HBW_AW_SET)) {

drivers/accel/habanalabs/gaudi2/gaudi2.c

8719

addr_hi = RREG32(base[i] + DEC_RAZWI_HBW_AW_ADDR_HI);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8720

addr_lo = RREG32(base[i] + DEC_RAZWI_HBW_AW_ADDR_LO);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8732

if (RREG32(base[i] + DEC_RAZWI_HBW_AR_SET)) {

drivers/accel/habanalabs/gaudi2/gaudi2.c

8733

addr_hi = RREG32(base[i] + DEC_RAZWI_HBW_AR_ADDR_HI);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8734

addr_lo = RREG32(base[i] + DEC_RAZWI_HBW_AR_ADDR_LO);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8746

if (RREG32(base[i] + DEC_RAZWI_LBW_AW_SET)) {

drivers/accel/habanalabs/gaudi2/gaudi2.c

8747

addr_lo = RREG32(base[i] + DEC_RAZWI_LBW_AW_ADDR);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8758

if (RREG32(base[i] + DEC_RAZWI_LBW_AR_SET)) {

drivers/accel/habanalabs/gaudi2/gaudi2.c

8759

addr_lo = RREG32(base[i] + DEC_RAZWI_LBW_AR_ADDR);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8788

razwi_intr = RREG32(mmPSOC_GLOBAL_CONF_RAZWI_INTERRUPT);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8793

razwi_mask_info = RREG32(mmPSOC_GLOBAL_CONF_RAZWI_MASK_INFO);

drivers/accel/habanalabs/gaudi2/gaudi2.c

8821

sts_val = RREG32(qman_base + QM_SEI_STATUS_OFFSET);

drivers/accel/habanalabs/gaudi2/gaudi2.c

9027

sts_val = RREG32(mmARC_FARM_ARC0_AUX_ARC_SEI_INTR_STS +

drivers/accel/habanalabs/gaudi2/gaudi2.c

9053

sts_val = RREG32(mmCPU_IF_CPU_SEI_INTR_STS);

drivers/accel/habanalabs/gaudi2/gaudi2.c

9131

sts_val = RREG32(sts_addr);

drivers/accel/habanalabs/gaudi2/gaudi2.c

9161

sts_val = RREG32(sts_addr);

drivers/accel/habanalabs/gaudi2/gaudi2.c

9204

sts_val = RREG32(sts_addr);

drivers/accel/habanalabs/gaudi2/gaudi2.c

9270

if (RREG32(razwi_happened_addr)) {

drivers/accel/habanalabs/gaudi2/gaudi2.c

9277

if (RREG32(razwi_happened_addr)) {

drivers/accel/habanalabs/gaudi2/gaudi2.c

9284

if (RREG32(razwi_happened_addr)) {

drivers/accel/habanalabs/gaudi2/gaudi2.c

9291

if (RREG32(razwi_happened_addr)) {

drivers/accel/habanalabs/gaudi2/gaudi2.c

9365

valid = RREG32(mmu_base + MMU_OFFSET(mmDCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID));

drivers/accel/habanalabs/gaudi2/gaudi2.c

9370

val = RREG32(mmu_base + MMU_OFFSET(mmDCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE));

drivers/accel/habanalabs/gaudi2/gaudi2.c

9373

addr |= RREG32(mmu_base + MMU_OFFSET(mmDCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE_VA));

drivers/accel/habanalabs/gaudi2/gaudi2.c

9394

valid = RREG32(mmu_base + MMU_OFFSET(mmDCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID));

drivers/accel/habanalabs/gaudi2/gaudi2.c

9399

val = RREG32(mmu_base + MMU_OFFSET(mmDCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE));

drivers/accel/habanalabs/gaudi2/gaudi2.c

9402

addr |= RREG32(mmu_base + MMU_OFFSET(mmDCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE_VA));

drivers/accel/habanalabs/gaudi2/gaudi2.c

9418

spi_sei_cause = RREG32(mmu_base + MMU_SPI_SEI_CAUSE_OFFSET);

drivers/accel/habanalabs/gaudi2/gaudi2.c

9455

sei_cause_val = RREG32(sei_cause_addr);

drivers/accel/habanalabs/gaudi2/gaudi2.c

9457

cq_intr_val = RREG32(cq_intr_addr);

drivers/accel/habanalabs/gaudi2/gaudi2.c

9881

p2p_intr = RREG32(mmPCIE_WRAP_P2P_INTR);

drivers/accel/habanalabs/gaudi2/gaudi2.c

9882

msix_gw_intr = RREG32(mmPCIE_WRAP_MSIX_GW_INTR);

drivers/accel/habanalabs/gaudi2/gaudi2.c

9887

RREG32(mmPCIE_WRAP_P2P_REQ_ID));

drivers/accel/habanalabs/gaudi2/gaudi2.c

9896

RREG32(mmPCIE_WRAP_MSIX_GW_VEC));

drivers/accel/habanalabs/gaudi2/gaudi2_coresight.c

1997

read_reg = RREG32(base_reg + mmSTM_STMDMAIDR_OFFSET);

drivers/accel/habanalabs/gaudi2/gaudi2_coresight.c

2014

RREG32(base_reg + mmSTM_STMTCSR_OFFSET);

drivers/accel/habanalabs/gaudi2/gaudi2_coresight.c

2087

read_reg = RREG32(base_reg + mmETF_STS_OFFSET);

drivers/accel/habanalabs/gaudi2/gaudi2_coresight.c

2095

val = RREG32(base_reg + mmETF_CTL_OFFSET);

drivers/accel/habanalabs/gaudi2/gaudi2_coresight.c

2100

val = RREG32(base_reg + mmETF_FFCR_OFFSET);

drivers/accel/habanalabs/gaudi2/gaudi2_coresight.c

2128

val = RREG32(base_reg + mmETF_RSZ_OFFSET) << 2;

drivers/accel/habanalabs/gaudi2/gaudi2_coresight.c

2204

val = RREG32(mmPSOC_ETR_CTL);

drivers/accel/habanalabs/gaudi2/gaudi2_coresight.c

2209

val = RREG32(mmPSOC_ETR_FFCR);

drivers/accel/habanalabs/gaudi2/gaudi2_coresight.c

2290

rwp = RREG32(mmPSOC_ETR_RWP);

drivers/accel/habanalabs/gaudi2/gaudi2_coresight.c

2291

rwphi = RREG32(mmPSOC_ETR_RWPHI) & 0xff;

drivers/accel/habanalabs/gaudi2/gaudi2_coresight.c

2292

msb = RREG32(mmPSOC_GLOBAL_CONF_TRACE_ADDR);

drivers/accel/habanalabs/gaudi2/gaudi2_coresight.c

2326

read_reg = RREG32(base_reg + mmFUNNEL_DEVID_OFFSET);

drivers/accel/habanalabs/gaudi2/gaudi2_coresight.c

2365

read_reg = RREG32(base_reg + mmBMON_CR_OFFSET);

drivers/accel/habanalabs/gaudi2/gaudi2_coresight.c

2372

RREG32(base_reg + mmBMON_ATTREN_OFFSET);

drivers/accel/habanalabs/gaudi2/gaudi2_coresight.c

2467

read_reg = RREG32(base_reg + mmSPMU_PMCR_EL0_OFFSET);

drivers/accel/habanalabs/gaudi2/gaudi2_coresight.c

2487

RREG32(base_reg);

drivers/accel/habanalabs/gaudi2/gaudi2_coresight.c

2527

output[i] = RREG32(performance_counter_offset);

drivers/accel/habanalabs/gaudi2/gaudi2_coresight.c

2530

output[overflow_idx] = RREG32(base_reg + mmSPMU_PMOVSSET_EL0_OFFSET);

drivers/accel/habanalabs/gaudi2/gaudi2_coresight.c

2531

output[cycle_cnt_idx] = RREG32(base_reg + mmSPMU_PMCCNTR_H_EL0_OFFSET);

drivers/accel/habanalabs/gaudi2/gaudi2_coresight.c

2533

output[cycle_cnt_idx] |= RREG32(base_reg + mmSPMU_PMCCNTR_L_EL0_OFFSET);

drivers/accel/habanalabs/goya/goya.c

1216

status = RREG32(cp_sts_reg);

drivers/accel/habanalabs/goya/goya.c

1384

prop->fw_app_cpu_boot_dev_sts0 = RREG32(mmCPU_BOOT_DEV_STS0);

drivers/accel/habanalabs/goya/goya.c

1387

prop->fw_app_cpu_boot_dev_sts1 = RREG32(mmCPU_BOOT_DEV_STS1);

drivers/accel/habanalabs/goya/goya.c

1453

val = RREG32(mmTPC0_CFG_FUNC_MBIST_CNTRL + tpc_offset);

drivers/accel/habanalabs/goya/goya.c

1499

val = RREG32(tpc_slm_offset);

drivers/accel/habanalabs/goya/goya.c

2721

RREG32(mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG);

drivers/accel/habanalabs/goya/goya.c

2772

RREG32(mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG);

drivers/accel/habanalabs/goya/goya.c

2828

status = RREG32(mmPSOC_GLOBAL_CONF_BTM_FSM);

drivers/accel/habanalabs/goya/goya.c

4192

i = RREG32(mmSYNC_MNGR_SOB_OBJ_0);

drivers/accel/habanalabs/goya/goya.c

4423

if (RREG32(mmDMA_MACRO_RAZWI_LBW_WT_VLD)) {

drivers/accel/habanalabs/goya/goya.c

4428

if (RREG32(mmDMA_MACRO_RAZWI_LBW_RD_VLD)) {

drivers/accel/habanalabs/goya/goya.c

4433

if (RREG32(mmDMA_MACRO_RAZWI_HBW_WT_VLD)) {

drivers/accel/habanalabs/goya/goya.c

4438

if (RREG32(mmDMA_MACRO_RAZWI_HBW_RD_VLD)) {

drivers/accel/habanalabs/goya/goya.c

4453

val = RREG32(mmMMU_PAGE_ERROR_CAPTURE);

drivers/accel/habanalabs/goya/goya.c

4457

addr |= RREG32(mmMMU_PAGE_ERROR_CAPTURE_VA);

drivers/accel/habanalabs/goya/goya.c

4941

RREG32(mmCPU_IF_AWUSER_OVR_EN);

drivers/accel/habanalabs/goya/goya.c

5138

qm_glbl_sts0 = RREG32(mmDMA_QM_0_GLBL_STS0 + i * offset);

drivers/accel/habanalabs/goya/goya.c

5139

dma_core_sts0 = RREG32(mmDMA_CH_0_STS0 + i * offset);

drivers/accel/habanalabs/goya/goya.c

5159

qm_glbl_sts0 = RREG32(mmTPC0_QM_GLBL_STS0 + i * offset);

drivers/accel/habanalabs/goya/goya.c

5160

cmdq_glbl_sts0 = RREG32(mmTPC0_CMDQ_GLBL_STS0 + i * offset);

drivers/accel/habanalabs/goya/goya.c

5161

tpc_cfg_sts = RREG32(mmTPC0_CFG_STATUS + i * offset);

drivers/accel/habanalabs/goya/goya.c

5179

qm_glbl_sts0 = RREG32(mmMME_QM_GLBL_STS0);

drivers/accel/habanalabs/goya/goya.c

5180

cmdq_glbl_sts0 = RREG32(mmMME_CMDQ_GLBL_STS0);

drivers/accel/habanalabs/goya/goya.c

5181

mme_arch_sts = RREG32(mmMME_ARCH_STATUS);

drivers/accel/habanalabs/goya/goya.c

5287

u64 device_time = ((u64) RREG32(mmPSOC_TIMESTAMP_CNTCVU)) << 32;

drivers/accel/habanalabs/goya/goya.c

5289

return device_time | RREG32(mmPSOC_TIMESTAMP_CNTCVL);

drivers/accel/habanalabs/goya/goya.c

593

return RREG32(mmHW_STATE);

drivers/accel/habanalabs/goya/goya.c

685

val = RREG32(mmPSOC_GLOBAL_CONF_BOOT_STRAP_PINS);

drivers/accel/habanalabs/goya/goya.c

735

RREG32(mmDMA_QM_0_GLBL_PROT);

drivers/accel/habanalabs/goya/goya.c

765

div_fctr = RREG32(mmPSOC_PCI_PLL_DIV_FACTOR_1);

drivers/accel/habanalabs/goya/goya.c

766

div_sel = RREG32(mmPSOC_PCI_PLL_DIV_SEL_1);

drivers/accel/habanalabs/goya/goya.c

767

nr = RREG32(mmPSOC_PCI_PLL_NR);

drivers/accel/habanalabs/goya/goya.c

768

nf = RREG32(mmPSOC_PCI_PLL_NF);

drivers/accel/habanalabs/goya/goya.c

769

od = RREG32(mmPSOC_PCI_PLL_OD);

drivers/accel/habanalabs/goya/goya_coresight.c

318

val = RREG32(base_reg + 0x20);

drivers/accel/habanalabs/goya/goya_coresight.c

323

val = RREG32(base_reg + 0x304);

drivers/accel/habanalabs/goya/goya_coresight.c

394

val = RREG32(mmPSOC_ETR_CTL);

drivers/accel/habanalabs/goya/goya_coresight.c

399

val = RREG32(mmPSOC_ETR_FFCR);

drivers/accel/habanalabs/goya/goya_coresight.c

475

rwp = RREG32(mmPSOC_ETR_RWP);

drivers/accel/habanalabs/goya/goya_coresight.c

476

rwphi = RREG32(mmPSOC_ETR_RWPHI) & 0xff;

drivers/accel/habanalabs/goya/goya_coresight.c

645

output[i] = RREG32(base_reg + i * 8);

drivers/accel/habanalabs/goya/goya_coresight.c

647

output[overflow_idx] = RREG32(base_reg + 0xCC0);

drivers/accel/habanalabs/goya/goya_coresight.c

649

output[cycle_cnt_idx] = RREG32(base_reg + 0xFC);

drivers/accel/habanalabs/goya/goya_coresight.c

651

output[cycle_cnt_idx] |= RREG32(base_reg + 0xF8);

drivers/accel/habanalabs/goya/goya_coresight.c

693

RREG32(mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG);

drivers/gpu/drm/amd/amdgpu/amdgpu.h

1399

uint32_t tmp_ = RREG32(reg); \

drivers/gpu/drm/amd/amdgpu/amdgpu.h

1435

WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))

drivers/gpu/drm/amd/amdgpu/amdgpu.h

1438

WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c

142

data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c

234

sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c

254

temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c

259

temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c

271

RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL) |

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c

274

m->sdmax_rlcx_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c

276

RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c

328

data = RREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CONFIG));

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c

59

(*dump)[i++][1] = RREG32(addr); \

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

141

(*dump)[i++][1] = RREG32(addr); \

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

175

sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_CNTL);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

195

temp = RREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_CNTL);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

200

temp = RREG32(sdma_rlc_reg_offset + regSDMA_RLC0_CONTEXT_STATUS);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

212

RREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_CNTL) |

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

216

RREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

218

RREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_RPTR_HI);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

246

while (!(RREG32(SOC15_REG_OFFSET(ATHUB, 0,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

260

reg = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_LUT_INDEX));

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

516

uint32_t status = RREG32(regSDMA_RLC0_CONTEXT_STATUS + reg_offset);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

517

uint32_t doorbell_off = RREG32(regSDMA_RLC0_DOORBELL_OFFSET + reg_offset);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

78

data = RREG32(sdma_rlc_reg_offset + regSDMA_RLC0_CONTEXT_STATUS);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

1021

*wait_times = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_IQ_WAIT_TIME2));

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

116

while (!(RREG32(SOC15_REG_OFFSET(

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

392

data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

505

sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

562

temp = RREG32(mmCP_HQD_IQ_TIMER);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

591

temp = RREG32(mmCP_HQD_DEQUEUE_REQUEST);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

638

temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

643

temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

655

RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL) |

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

658

m->sdmax_rlcx_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

660

RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

670

value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

738

uint32_t data = RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL));

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

750

RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL));

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

837

wave_cntl_prev = RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL));

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

841

data = RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK));

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

378

data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

492

sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

562

temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

567

temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

579

RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL) |

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

582

m->sdmax_rlcx_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

584

RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

618

value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

187

value = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_CP_SCHEDULERS));

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

323

(*dump)[i++][1] = RREG32(addr); \

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

363

data = RREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_CONTEXT_STATUS);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

457

act = RREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_ACTIVE));

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

462

if (low == RREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_PQ_BASE)) &&

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

463

high == RREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_PQ_BASE_HI)))

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

480

sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_RB_CNTL);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

519

temp = RREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_ACTIVE));

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

547

temp = RREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_RB_CNTL);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

552

temp = RREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_CONTEXT_STATUS);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

564

RREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_RB_CNTL) |

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

567

m->sdmax_rlcx_rb_rptr = RREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

569

RREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_RB_RPTR_HI);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

115

(*dump)[i++][1] = RREG32(addr); \

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c

118

(*dump)[i++][1] = RREG32(addr); \

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

107

while (!(RREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS) & (1U << vmid)))

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

214

(*dump)[i++][1] = RREG32(addr); \

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

255

data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

329

act = RREG32(mmCP_HQD_ACTIVE);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

334

if (low == RREG32(mmCP_HQD_PQ_BASE) &&

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

335

high == RREG32(mmCP_HQD_PQ_BASE_HI))

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

351

sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

397

temp = RREG32(mmCP_HQD_IQ_TIMER);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

426

temp = RREG32(mmCP_HQD_DEQUEUE_REQUEST);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

445

temp = RREG32(mmCP_HQD_ACTIVE);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

471

temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

476

temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

488

RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL) |

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

491

m->sdma_rlc_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

525

value = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

559

uint32_t status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

102

while (!(RREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS) & (1U << vmid)))

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

177

value = RREG32(mmRLC_CP_SCHEDULERS);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

238

(*dump)[i++][1] = RREG32(addr); \

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

278

data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

361

act = RREG32(mmCP_HQD_ACTIVE);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

366

if (low == RREG32(mmCP_HQD_PQ_BASE) &&

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

367

high == RREG32(mmCP_HQD_PQ_BASE_HI))

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

383

sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

432

temp = RREG32(mmCP_HQD_IQ_TIMER);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

461

temp = RREG32(mmCP_HQD_DEQUEUE_REQUEST);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

480

temp = RREG32(mmCP_HQD_ACTIVE);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

506

temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

511

temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

523

RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL) |

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

526

m->sdmax_rlcx_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

536

value = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

123

while (!(RREG32(SOC15_REG_OFFSET(

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

140

while (!(RREG32(SOC15_REG_OFFSET(

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

363

(*dump)[i++][1] = RREG32(addr); \

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

403

data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

516

sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

588

temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

593

temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

605

RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL) |

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

608

m->sdmax_rlcx_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

610

RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

620

value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

676

uint32_t data = RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL));

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

691

RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL));

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

771

wave_cntl_prev = RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL));

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

775

data = RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK));

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

1562

bios_6_scratch = RREG32(adev->bios_scratch_reg_offset + 6);

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

1581

bios_2_scratch = RREG32(adev->bios_scratch_reg_offset + 2);

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

1582

bios_6_scratch = RREG32(adev->bios_scratch_reg_offset + 6);

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

1600

u32 tmp = RREG32(adev->bios_scratch_reg_offset + 3);

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

1613

u32 tmp = RREG32(adev->bios_scratch_reg_offset + 2);

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

1624

u32 tmp = RREG32(adev->bios_scratch_reg_offset + 7);

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

1803

r = RREG32(reg);

drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c

486

mem_vendor = RREG32(adev->bios_scratch_reg_offset + 4) & 0xF;

drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c

504

module_id = (RREG32(adev->bios_scratch_reg_offset + 4) & 0x00ff0000) >> 16;

drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c

588

dw_ptr[i] = RREG32(rom_data_offset);

drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c

47

return RREG32(offset);

drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c

151

value = RREG32(*pos >> 2);

drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c

278

value = RREG32(offset >> 2);

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

1662

tmp = RREG32(reg);

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

7411

(void)RREG32(address);

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

7412

r = RREG32(data);

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

7427

(void)RREG32(address);

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

7429

(void)RREG32(data);

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

7621

uint32_t tmp_ = RREG32(reg_addr);

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

7630

tmp_ = RREG32(reg_addr);

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

1869

vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20;

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

300

msg = RREG32(mmMP0_SMN_C2PMSG_33);

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

307

vram_size = RREG32(mmRCC_CONFIG_MEMSIZE);

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

670

(RREG32(mmIP_DISCOVERY_VERSION) == 4))

drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c

108

val = RREG32(rec->y_clk_reg);

drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c

123

val = RREG32(rec->y_data_reg);

drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c

137

val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;

drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c

150

val = RREG32(rec->en_data_reg) & ~rec->en_data_mask;

drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c

50

temp = RREG32(rec->mask_clk_reg);

drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c

56

temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask;

drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c

59

temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask;

drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c

63

temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;

drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c

66

temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask;

drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c

70

temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask;

drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c

72

temp = RREG32(rec->mask_clk_reg);

drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c

74

temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask;

drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c

76

temp = RREG32(rec->mask_data_reg);

drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c

89

temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask;

drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c

91

temp = RREG32(rec->mask_clk_reg);

drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c

93

temp = RREG32(rec->mask_data_reg) & ~rec->mask_data_mask;

drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c

95

temp = RREG32(rec->mask_data_reg);

drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c

169

RREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch[ring->pipe]);

drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c

176

tmp = RREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch[ring->pipe]);

drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c

253

tmp = RREG32(adev->jpeg.inst[ring->me].external.jpeg_pitch[ring->pipe]);

drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c

503

RREG32(SOC15_REG_ENTRY_OFFSET_INST(adev->jpeg.reg_list[0],

drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c

510

RREG32(SOC15_REG_ENTRY_OFFSET_INST(adev->jpeg.reg_list[j],

drivers/gpu/drm/amd/amdgpu/amdgpu_lsdma.c

37

val = RREG32(reg_index);

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

603

val = RREG32(reg_index);

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

633

val = RREG32(reg_index);

drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

5233

err_status_lo_data = RREG32(err_status_lo_offset);

drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

5257

err_status_hi_data = RREG32(err_status_hi_offset);

drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c

82

return RREG32(umsch->rb_rptr);

drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c

90

return RREG32(umsch->rb_wptr);

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c

1596

RREG32(SOC15_REG_ENTRY_OFFSET_INST(adev->vcn.reg_list[0], i));

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c

1604

RREG32(SOC15_REG_ENTRY_OFFSET_INST(adev->vcn.reg_list[j], i));

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c

575

tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9);

drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c

1605

return RREG32(offset);

drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c

830

reg = RREG32(mmBIF_IOV_FUNC_IDENTIFIER);

drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c

840

reg = RREG32(mmRCC_IOV_FUNC_IDENTIFIER);

drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c

958

vram_size = RREG32(mmRCC_CONFIG_MEMSIZE);

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

135

dpm_ctl = RREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_enable));

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

213

dpm_ctl = RREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_enable));

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

342

return RREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_request_lv));

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

712

rptr = RREG32(vpe_get_reg_offset(vpe, ring->me, vpe->regs.queue0_rb_rptr_hi));

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

714

rptr |= RREG32(vpe_get_reg_offset(vpe, ring->me, vpe->regs.queue0_rb_rptr_lo));

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

731

wptr = RREG32(vpe_get_reg_offset(vpe, ring->me, vpe->regs.queue0_rb_wptr_hi));

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

733

wptr |= RREG32(vpe_get_reg_offset(vpe, ring->me, vpe->regs.queue0_rb_wptr_lo));

drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c

885

context_notify = RREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.context_indicator));

drivers/gpu/drm/amd/amdgpu/atombios_encoders.c

1731

bios_0_scratch = RREG32(mmBIOS_SCRATCH_0);

drivers/gpu/drm/amd/amdgpu/atombios_encoders.c

1776

bios_0_scratch = RREG32(mmBIOS_SCRATCH_0);

drivers/gpu/drm/amd/amdgpu/atombios_encoders.c

1824

bios_0_scratch = RREG32(mmBIOS_SCRATCH_0);

drivers/gpu/drm/amd/amdgpu/atombios_encoders.c

1825

bios_3_scratch = RREG32(mmBIOS_SCRATCH_3);

drivers/gpu/drm/amd/amdgpu/atombios_encoders.c

1826

bios_6_scratch = RREG32(mmBIOS_SCRATCH_6);

drivers/gpu/drm/amd/amdgpu/atombios_encoders.c

48

bios_2_scratch = RREG32(mmBIOS_SCRATCH_2);

drivers/gpu/drm/amd/amdgpu/atombios_encoders.c

62

bios_2_scratch = RREG32(mmBIOS_SCRATCH_2);

drivers/gpu/drm/amd/amdgpu/cik.c

1037

dw_ptr[i] = RREG32(mmSMC_IND_DATA_0);

drivers/gpu/drm/amd/amdgpu/cik.c

1146

val = RREG32(reg_offset);

drivers/gpu/drm/amd/amdgpu/cik.c

1213

return RREG32(reg_offset);

drivers/gpu/drm/amd/amdgpu/cik.c

1246

save->gmcon_reng_execute = RREG32(mmGMCON_RENG_EXECUTE);

drivers/gpu/drm/amd/amdgpu/cik.c

1247

save->gmcon_misc = RREG32(mmGMCON_MISC);

drivers/gpu/drm/amd/amdgpu/cik.c

1248

save->gmcon_misc3 = RREG32(mmGMCON_MISC3);

drivers/gpu/drm/amd/amdgpu/cik.c

1359

if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff) {

drivers/gpu/drm/amd/amdgpu/cik.c

1448

return RREG32(mmCONFIG_MEMSIZE);

drivers/gpu/drm/amd/amdgpu/cik.c

159

(void)RREG32(mmPCIE_INDEX);

drivers/gpu/drm/amd/amdgpu/cik.c

160

r = RREG32(mmPCIE_DATA);

drivers/gpu/drm/amd/amdgpu/cik.c

171

(void)RREG32(mmPCIE_INDEX);

drivers/gpu/drm/amd/amdgpu/cik.c

173

(void)RREG32(mmPCIE_DATA);

drivers/gpu/drm/amd/amdgpu/cik.c

184

r = RREG32(mmSMC_IND_DATA_0);

drivers/gpu/drm/amd/amdgpu/cik.c

1854

return (RREG32(mmCC_DRM_ID_STRAPS) & CC_DRM_ID_STRAPS__ATI_REV_ID_MASK)

drivers/gpu/drm/amd/amdgpu/cik.c

1862

RREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL);

drivers/gpu/drm/amd/amdgpu/cik.c

1873

RREG32(mmHDP_DEBUG0);

drivers/gpu/drm/amd/amdgpu/cik.c

206

r = RREG32(mmUVD_CTX_DATA);

drivers/gpu/drm/amd/amdgpu/cik.c

228

r = RREG32(mmDIDT_IND_DATA);

drivers/gpu/drm/amd/amdgpu/cik.c

959

tmp = RREG32(mmCONFIG_CNTL);

drivers/gpu/drm/amd/amdgpu/cik.c

976

bus_cntl = RREG32(mmBUS_CNTL);

drivers/gpu/drm/amd/amdgpu/cik.c

978

d1vga_control = RREG32(mmD1VGA_CONTROL);

drivers/gpu/drm/amd/amdgpu/cik.c

979

d2vga_control = RREG32(mmD2VGA_CONTROL);

drivers/gpu/drm/amd/amdgpu/cik.c

980

vga_render_control = RREG32(mmVGA_RENDER_CONTROL);

drivers/gpu/drm/amd/amdgpu/cik_ih.c

117

interrupt_cntl = RREG32(mmINTERRUPT_CNTL);

drivers/gpu/drm/amd/amdgpu/cik_ih.c

210

tmp = RREG32(mmIH_RB_CNTL);

drivers/gpu/drm/amd/amdgpu/cik_ih.c

363

u32 tmp = RREG32(mmSRBM_STATUS);

drivers/gpu/drm/amd/amdgpu/cik_ih.c

379

tmp = RREG32(mmSRBM_STATUS) & SRBM_STATUS__IH_BUSY_MASK;

drivers/gpu/drm/amd/amdgpu/cik_ih.c

392

u32 tmp = RREG32(mmSRBM_STATUS);

drivers/gpu/drm/amd/amdgpu/cik_ih.c

398

tmp = RREG32(mmSRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/cik_ih.c

402

tmp = RREG32(mmSRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/cik_ih.c

408

tmp = RREG32(mmSRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/cik_ih.c

62

u32 ih_cntl = RREG32(mmIH_CNTL);

drivers/gpu/drm/amd/amdgpu/cik_ih.c

63

u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);

drivers/gpu/drm/amd/amdgpu/cik_ih.c

81

u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);

drivers/gpu/drm/amd/amdgpu/cik_ih.c

82

u32 ih_cntl = RREG32(mmIH_CNTL);

drivers/gpu/drm/amd/amdgpu/cik_sdma.c

1025

u32 tmp = RREG32(mmSRBM_STATUS2);

drivers/gpu/drm/amd/amdgpu/cik_sdma.c

1054

tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);

drivers/gpu/drm/amd/amdgpu/cik_sdma.c

1060

tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);

drivers/gpu/drm/amd/amdgpu/cik_sdma.c

1066

tmp = RREG32(mmSRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/cik_sdma.c

1070

tmp = RREG32(mmSRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/cik_sdma.c

1076

tmp = RREG32(mmSRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/cik_sdma.c

1096

sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);

drivers/gpu/drm/amd/amdgpu/cik_sdma.c

1101

sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);

drivers/gpu/drm/amd/amdgpu/cik_sdma.c

1112

sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);

drivers/gpu/drm/amd/amdgpu/cik_sdma.c

1117

sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);

drivers/gpu/drm/amd/amdgpu/cik_sdma.c

181

return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) & 0x3fffc) >> 2;

drivers/gpu/drm/amd/amdgpu/cik_sdma.c

314

rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);

drivers/gpu/drm/amd/amdgpu/cik_sdma.c

371

f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);

drivers/gpu/drm/amd/amdgpu/cik_sdma.c

409

me_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);

drivers/gpu/drm/amd/amdgpu/cik_sdma.c

882

orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET);

drivers/gpu/drm/amd/amdgpu/cik_sdma.c

887

orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET);

drivers/gpu/drm/amd/amdgpu/cik_sdma.c

900

orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);

drivers/gpu/drm/amd/amdgpu/cik_sdma.c

905

orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);

drivers/gpu/drm/amd/amdgpu/cik_sdma.c

910

orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);

drivers/gpu/drm/amd/amdgpu/cik_sdma.c

915

orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);

drivers/gpu/drm/amd/amdgpu/cz_ih.c

117

interrupt_cntl = RREG32(mmINTERRUPT_CNTL);

drivers/gpu/drm/amd/amdgpu/cz_ih.c

148

ih_cntl = RREG32(mmIH_CNTL);

drivers/gpu/drm/amd/amdgpu/cz_ih.c

207

wptr = RREG32(mmIH_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/cz_ih.c

221

tmp = RREG32(mmIH_RB_CNTL);

drivers/gpu/drm/amd/amdgpu/cz_ih.c

357

u32 tmp = RREG32(mmSRBM_STATUS);

drivers/gpu/drm/amd/amdgpu/cz_ih.c

373

tmp = RREG32(mmSRBM_STATUS);

drivers/gpu/drm/amd/amdgpu/cz_ih.c

385

u32 tmp = RREG32(mmSRBM_STATUS);

drivers/gpu/drm/amd/amdgpu/cz_ih.c

392

tmp = RREG32(mmSRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/cz_ih.c

396

tmp = RREG32(mmSRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/cz_ih.c

402

tmp = RREG32(mmSRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/cz_ih.c

62

u32 ih_cntl = RREG32(mmIH_CNTL);

drivers/gpu/drm/amd/amdgpu/cz_ih.c

63

u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);

drivers/gpu/drm/amd/amdgpu/cz_ih.c

81

u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);

drivers/gpu/drm/amd/amdgpu/cz_ih.c

82

u32 ih_cntl = RREG32(mmIH_CNTL);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1125

wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1128

tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1135

tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1219

tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1485

tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1488

tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1492

tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1495

tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1499

tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1502

tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1550

tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1594

tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1600

tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1627

tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1633

tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1640

tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1645

tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1652

tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1659

tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1664

tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1677

tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1681

tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1685

tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1717

tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1724

tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1728

tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

180

r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1820

vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

2008

tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

202

return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

2029

tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

2089

tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

2108

tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

2113

tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

2117

tmp = RREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

2121

tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

2150

tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

2156

tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

2161

tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

2166

tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

2176

tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

2275

cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

2289

tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

2305

tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

242

tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

256

RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

265

*vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

266

*position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

2686

fb_format = RREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

288

if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) &

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

2975

tmp = RREG32(mmSRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

2979

tmp = RREG32(mmSRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

2985

tmp = RREG32(mmSRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

3006

lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

3012

lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

3035

lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

3041

lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

3065

tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

3070

tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

312

tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

3141

reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

3169

if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

3215

tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

3230

tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

3245

tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

3255

uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

3301

disp_int = RREG32(interrupt_status_offsets[hpd].reg);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

349

tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

355

tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

359

tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

398

tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

420

tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

422

crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

430

tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

449

tmp = RREG32(mmVGA_HDP_CONTROL);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

457

tmp = RREG32(mmVGA_RENDER_CONTROL);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

491

crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

495

tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

628

tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

632

tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

637

tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

670

u32 tmp = RREG32(mmMC_SHARED_CHMAP);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1012

arb_control3 = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1021

tmp = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1096

if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

143

r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1470

tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1487

tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1493

tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1496

tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1500

tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1503

tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1507

tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1510

tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1551

tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1572

tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1600

tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1604

tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1608

tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1612

tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1621

tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1625

tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1630

tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1644

tmp = RREG32(mmHDMI_GC + dig->afmt->offset);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1658

tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

166

return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1665

tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1669

tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1673

tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1680

tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1695

tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1699

tmp = RREG32(mmDP_SEC_TIMESTAMP + dig->afmt->offset);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1703

tmp = RREG32(mmDP_SEC_CNTL + dig->afmt->offset);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1864

vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

220

RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

2248

cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

229

*vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

230

*position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

252

if (RREG32(mmDC_HPD1_INT_STATUS + hpd_offsets[hpd]) &

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

2653

fb_format = RREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

276

tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

2913

tmp = RREG32(mmSRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

2917

tmp = RREG32(mmSRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

2923

tmp = RREG32(mmSRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

294

tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

2968

interrupt_mask = RREG32(mmINT_MASK + reg_block);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

2973

interrupt_mask = RREG32(mmINT_MASK + reg_block);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

3003

dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

3008

dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

3072

uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

3116

reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

3144

if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

3193

disp_int = RREG32(interrupt_status_offsets[hpd].reg);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

321

tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

332

tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

367

tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

388

if (RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK) {

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

389

crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

397

tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

415

RREG32(mmVGA_RENDER_CONTROL) & ~VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

443

crtc_enabled = RREG32(mmCRTC_CONTROL + crtc_offsets[i]) &

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

447

tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

523

u32 tmp = RREG32(mmMC_SHARED_CHMAP);

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

1078

wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

1087

tmp = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

131

r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

153

return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

1566

val = RREG32(mmHDMI_CONTROL + offset);

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

1767

vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

204

RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

213

*vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

214

*position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

2196

cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

236

if (RREG32(mmDC_HPD1_INT_STATUS + hpd_offsets[hpd]) &

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

260

tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

2612

fb_format = RREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset);

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

278

tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

2885

tmp = RREG32(mmSRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

2889

tmp = RREG32(mmSRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

2895

tmp = RREG32(mmSRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

2940

lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

2945

lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

2991

lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

2996

lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

3019

dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

3024

dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

305

tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

3088

uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

3132

reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

316

tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

3160

if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

3209

disp_int = RREG32(interrupt_status_offsets[hpd].reg);

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

351

tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

372

if (RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK) {

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

373

crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

381

tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

400

tmp = RREG32(mmVGA_HDP_CONTROL);

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

408

tmp = RREG32(mmVGA_RENDER_CONTROL);

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

449

crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

453

tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

590

if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

623

u32 tmp = RREG32(mmMC_SHARED_CHMAP);

drivers/gpu/drm/amd/amdgpu/df_v3_6.c

107

*lo_val = RREG32(data);

drivers/gpu/drm/amd/amdgpu/df_v3_6.c

109

*hi_val = RREG32(data);

drivers/gpu/drm/amd/amdgpu/df_v3_6.c

153

lo_val_rb = RREG32(data);

drivers/gpu/drm/amd/amdgpu/df_v3_6.c

155

hi_val_rb = RREG32(data);

drivers/gpu/drm/amd/amdgpu/df_v3_6.c

59

ficadl_val = RREG32(data);

drivers/gpu/drm/amd/amdgpu/df_v3_6.c

62

ficadh_val = RREG32(data);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

4056

tmp = RREG32(scratch);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

8225

reg_data = RREG32(reg_idx);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

8233

reg_data = RREG32(reg_idx);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

8242

reg_data = RREG32(reg_idx);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

8309

pre_data = RREG32(reg);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

9719

adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_10_1[i]));

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

9738

RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME2_HEADER_DUMP));

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

9741

RREG32(SOC15_REG_ENTRY_OFFSET(

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

9767

RREG32(SOC15_REG_ENTRY_OFFSET(

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2313

tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL));

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5594

pre_data = RREG32(reg);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

590

tmp = RREG32(scratch);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

6812

r = (RREG32(SOC15_REG_OFFSET(GC, 0, regCP_GFX_RS64_INSTR_PNTR1)) << 2) -

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

6977

r = RREG32(SOC15_REG_OFFSET(GC, 0, regCP_MEC1_INSTR_PNTR));

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

7103

adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_11_0[i]));

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

7123

RREG32(SOC15_REG_OFFSET(GC, 0,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

7127

RREG32(SOC15_REG_ENTRY_OFFSET(

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

7153

RREG32(SOC15_REG_ENTRY_OFFSET(

drivers/gpu/drm/amd/amdgpu/gfx_v11_0_3.c

44

rlc_status0 = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_RLCS_FED_STATUS_0));

drivers/gpu/drm/amd/amdgpu/gfx_v11_0_3.c

45

rlc_status1 = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_RLCS_FED_STATUS_1));

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

1972

tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL));

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

3974

data = RREG32(reg);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

479

tmp = RREG32(scratch);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

5172

adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_12_0[i]));

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

5189

RREG32(SOC15_REG_ENTRY_OFFSET(

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

5215

RREG32(SOC15_REG_ENTRY_OFFSET(

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

5275

r = (RREG32(SOC15_REG_OFFSET(GC, 0, regCP_GFX_RS64_INSTR_PNTR1)) << 2) -

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1614

tmp = RREG32(SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SRM_CNTL));

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

272

tmp = RREG32(scratch_reg0_offset);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

293

tmp = RREG32(scratch_reg0_offset);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2961

data = RREG32(reg);

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

1333

data = RREG32(mmCC_RB_BACKEND_DISABLE) |

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

1334

RREG32(mmGC_USER_RB_BACKEND_DISABLE);

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

1509

RREG32(mmCC_RB_BACKEND_DISABLE);

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

1511

RREG32(mmGC_USER_RB_BACKEND_DISABLE);

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

1513

RREG32(mmPA_SC_RASTER_CONFIG);

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

1538

data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG) |

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

1539

RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

1556

data = RREG32(mmSPI_STATIC_THREAD_MGMT_3);

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

1684

adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

1747

sx_debug_1 = RREG32(mmSX_DEBUG_1);

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

1779

hdp_host_path_cntl = RREG32(mmHDP_HOST_PATH_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

1807

tmp = RREG32(mmSCRATCH_REG0);

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

1924

tmp = RREG32(mmSCRATCH_REG0);

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

2133

return RREG32(mmCP_RB0_WPTR);

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

2135

return RREG32(mmCP_RB1_WPTR);

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

2137

return RREG32(mmCP_RB2_WPTR);

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

2147

(void)RREG32(mmCP_RB0_WPTR);

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

2156

(void)RREG32(mmCP_RB1_WPTR);

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

2159

(void)RREG32(mmCP_RB2_WPTR);

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

2239

u32 tmp = RREG32(mmCP_INT_CNTL_RING0);

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

2253

tmp = RREG32(mmDB_DEPTH_INFO);

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

2257

if ((RREG32(mmRLC_STAT) & mask) == (GFX_CLOCK_STATUS | GFX_POWER_STATUS))

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

2425

if (RREG32(mmRLC_SERDES_MASTER_BUSY_0) == 0)

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

2431

if (RREG32(mmRLC_SERDES_MASTER_BUSY_1) == 0)

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

2441

tmp = RREG32(mmRLC_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

2450

orig = data = RREG32(mmRLC_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

2492

tmp = RREG32(mmMC_SEQ_MISC0);

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

2551

orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL);

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

2573

RREG32(mmCB_CGTT_SCLK_CTRL);

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

2574

RREG32(mmCB_CGTT_SCLK_CTRL);

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

2575

RREG32(mmCB_CGTT_SCLK_CTRL);

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

2576

RREG32(mmCB_CGTT_SCLK_CTRL);

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

2592

orig = data = RREG32(mmCGTS_SM_CTRL_REG);

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

2598

orig = data = RREG32(mmCP_MEM_SLP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

2604

orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

2617

orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

2622

data = RREG32(mmCP_MEM_SLP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

2627

orig = data = RREG32(mmCGTS_SM_CTRL_REG);

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

2671

orig = data = RREG32(mmRLC_PG_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

2760

(void)RREG32(mmDB_RENDER_CONTROL);

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

2770

tmp = RREG32(mmRLC_MAX_PG_CU);

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

2781

orig = data = RREG32(mmRLC_PG_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

2795

orig = data = RREG32(mmRLC_PG_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

2812

tmp = RREG32(mmRLC_AUTO_PG_CTRL);

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

2927

clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

2928

((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

2950

return RREG32(mmSQ_IND_DATA);

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

2965

*(out++) = RREG32(mmSQ_IND_DATA);

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

3173

if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

3199

cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

3204

cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

3221

cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1);

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

3226

cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2);

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

3234

cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1);

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

3239

cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2);

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

3262

cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

3267

cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

3287

cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

3292

cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1596

data = RREG32(mmCC_RB_BACKEND_DISABLE);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1597

data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1800

RREG32(mmCC_RB_BACKEND_DISABLE);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1802

RREG32(mmGC_USER_RB_BACKEND_DISABLE);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1804

RREG32(mmPA_SC_RASTER_CONFIG);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1806

RREG32(mmPA_SC_RASTER_CONFIG_1);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1962

tmp = RREG32(mmSPI_CONFIG_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1970

tmp = RREG32(mmDB_DEBUG2) & ~0xf00fffff;

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1974

tmp = RREG32(mmDB_DEBUG3) & ~0x0002021c;

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1978

tmp = RREG32(mmCB_HW_CONTROL) & ~0x00010000;

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

2011

tmp = RREG32(mmSPI_ARB_PRIORITY);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

2051

tmp = RREG32(mmSCRATCH_REG0);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

2321

tmp = RREG32(mmSCRATCH_REG0);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

2596

return RREG32(mmCP_RB0_WPTR);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

2604

(void)RREG32(mmCP_RB0_WPTR);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

2782

tmp = RREG32(mmCP_HPD_EOP_CONTROL);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

2796

if (RREG32(mmCP_HQD_ACTIVE) & 1) {

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

2799

if (!(RREG32(mmCP_HQD_ACTIVE) & 1))

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

2834

RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

2845

mqd->cp_mqd_control = RREG32(mmCP_MQD_CONTROL);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

2854

mqd->cp_hqd_pq_control = RREG32(mmCP_HQD_PQ_CONTROL);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

2889

RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

2908

mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

2914

mqd->cp_hqd_ib_control = RREG32(mmCP_HQD_IB_CONTROL);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

2915

mqd->cp_hqd_ib_base_addr_lo = RREG32(mmCP_HQD_IB_BASE_ADDR);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

2916

mqd->cp_hqd_ib_base_addr_hi = RREG32(mmCP_HQD_IB_BASE_ADDR_HI);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

2917

mqd->cp_hqd_ib_rptr = RREG32(mmCP_HQD_IB_RPTR);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

2918

mqd->cp_hqd_persistent_state = RREG32(mmCP_HQD_PERSISTENT_STATE);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

2919

mqd->cp_hqd_sema_cmd = RREG32(mmCP_HQD_SEMA_CMD);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

2920

mqd->cp_hqd_msg_type = RREG32(mmCP_HQD_MSG_TYPE);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

2921

mqd->cp_hqd_atomic0_preop_lo = RREG32(mmCP_HQD_ATOMIC0_PREOP_LO);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

2922

mqd->cp_hqd_atomic0_preop_hi = RREG32(mmCP_HQD_ATOMIC0_PREOP_HI);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

2923

mqd->cp_hqd_atomic1_preop_lo = RREG32(mmCP_HQD_ATOMIC1_PREOP_LO);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

2924

mqd->cp_hqd_atomic1_preop_hi = RREG32(mmCP_HQD_ATOMIC1_PREOP_HI);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

2925

mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

2926

mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

2927

mqd->cp_hqd_pipe_priority = RREG32(mmCP_HQD_PIPE_PRIORITY);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

2928

mqd->cp_hqd_queue_priority = RREG32(mmCP_HQD_QUEUE_PRIORITY);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

2929

mqd->cp_hqd_iq_rptr = RREG32(mmCP_HQD_IQ_RPTR);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

2945

tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

3006

tmp = RREG32(mmCP_CPF_DEBUG);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

3057

u32 tmp = RREG32(mmCP_INT_CNTL_RING0);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

3249

tmp = RREG32(mmRLC_LB_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

3267

if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

3281

if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

3291

tmp = RREG32(mmRLC_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

3300

orig = data = RREG32(mmRLC_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

3309

if ((RREG32(mmRLC_GPM_STAT) & RLC_GPM_STAT__RLC_BUSY_MASK) == 0)

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

3335

if ((RREG32(mmRLC_GPM_STAT) & mask) == mask)

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

3341

if ((RREG32(mmRLC_GPR_REG2) & 0x1) == 0)

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

3389

u32 tmp = RREG32(mmGRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

3427

tmp = RREG32(mmRLC_CGCG_CGLS_CTRL) & 0xfffffffc;

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

3473

data = RREG32(mmRLC_SPM_VMID);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

3487

orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

3513

RREG32(mmCB_CGTT_SCLK_CTRL);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

3514

RREG32(mmCB_CGTT_SCLK_CTRL);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

3515

RREG32(mmCB_CGTT_SCLK_CTRL);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

3516

RREG32(mmCB_CGTT_SCLK_CTRL);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

3533

orig = data = RREG32(mmCP_MEM_SLP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

3540

orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

3560

orig = data = RREG32(mmCGTS_SM_CTRL_REG);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

3575

orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

3580

data = RREG32(mmRLC_MEM_SLP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

3586

data = RREG32(mmCP_MEM_SLP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

3592

orig = data = RREG32(mmCGTS_SM_CTRL_REG);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

3631

orig = data = RREG32(mmRLC_PG_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

3645

orig = data = RREG32(mmRLC_PG_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

3658

orig = data = RREG32(mmRLC_PG_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

3671

orig = data = RREG32(mmRLC_PG_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

3694

orig = data = RREG32(mmRLC_PG_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

3699

orig = data = RREG32(mmRLC_AUTO_PG_CTRL);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

3704

orig = data = RREG32(mmRLC_PG_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

3709

orig = data = RREG32(mmRLC_AUTO_PG_CTRL);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

3714

data = RREG32(mmDB_RENDER_CONTROL);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

3736

data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

3737

data |= RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

3753

tmp = RREG32(mmRLC_MAX_PG_CU);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

3764

orig = data = RREG32(mmRLC_PG_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

3778

orig = data = RREG32(mmRLC_PG_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

3811

orig = data = RREG32(mmRLC_PG_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

3819

data = RREG32(mmCP_RB_WPTR_POLL_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

3827

data = RREG32(mmRLC_PG_DELAY_2);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

3832

data = RREG32(mmRLC_AUTO_PG_CTRL);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

3948

clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

3949

((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

4012

return RREG32(mmSQ_IND_DATA);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

4027

*(out++) = RREG32(mmSQ_IND_DATA);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

4243

adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

4255

tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

4259

tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

4514

if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

4528

tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK;

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

4544

tmp = RREG32(mmGRBM_STATUS);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

4560

tmp = RREG32(mmGRBM_STATUS2);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

4565

tmp = RREG32(mmSRBM_STATUS);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

4584

tmp = RREG32(mmGRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

4588

tmp = RREG32(mmGRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

4594

tmp = RREG32(mmGRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

4598

tmp = RREG32(mmSRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

4602

tmp = RREG32(mmSRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

4608

tmp = RREG32(mmSRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

4623

cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

4628

cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

4674

mec_int_cntl = RREG32(mec_int_cntl_reg);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

4679

mec_int_cntl = RREG32(mec_int_cntl_reg);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

4697

cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

4702

cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

4722

cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

4727

cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

5044

adev->gds.gds_size = RREG32(mmGDS_VMID0_SIZE);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

5047

adev->gds.gds_compute_max_wave_id = RREG32(mmGDS_COMPUTE_MAX_WAVE_ID);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

1492

tmp = RREG32(mmGB_EDC_MODE);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

1622

tmp = RREG32(mmCC_GC_EDC_CONFIG);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

1629

RREG32(sec_ded_counter_registers[i]);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

1781

adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

1793

tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

1797

tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

3421

data = RREG32(mmCC_RB_BACKEND_DISABLE) |

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

3422

RREG32(mmGC_USER_RB_BACKEND_DISABLE);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

3626

RREG32(mmCC_RB_BACKEND_DISABLE);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

3628

RREG32(mmGC_USER_RB_BACKEND_DISABLE);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

3630

RREG32(mmPA_SC_RASTER_CONFIG);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

3632

RREG32(mmPA_SC_RASTER_CONFIG_1);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

3794

tmp = RREG32(mmSPI_ARB_PRIORITY);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

3815

if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

3837

if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

3846

u32 tmp = RREG32(mmCP_INT_CNTL_RING0);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4086

u32 tmp = RREG32(mmCP_ME_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4200

tmp = RREG32(mmCP_RB_DOORBELL_CONTROL);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4298

tmp = RREG32(mmRLC_CP_SCHEDULERS);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4369

if (RREG32(mmCP_HQD_ACTIVE) & CP_HQD_ACTIVE__ACTIVE_MASK) {

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4372

if (!(RREG32(mmCP_HQD_ACTIVE) & CP_HQD_ACTIVE__ACTIVE_MASK))

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4422

tmp = RREG32(mmCP_HQD_EOP_CONTROL);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4429

tmp = REG_SET_FIELD(RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL),

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4441

tmp = RREG32(mmCP_MQD_CONTROL);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4451

tmp = RREG32(mmCP_HQD_PQ_CONTROL);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4479

tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4496

mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4501

tmp = RREG32(mmCP_HQD_PERSISTENT_STATE);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4506

tmp = RREG32(mmCP_HQD_IB_CONTROL);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4511

tmp = RREG32(mmCP_HQD_IQ_TIMER);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4515

tmp = RREG32(mmCP_HQD_CTX_SAVE_CONTROL);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4520

mqd->cp_hqd_eop_rptr = RREG32(mmCP_HQD_EOP_RPTR);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4521

mqd->cp_hqd_eop_wptr = RREG32(mmCP_HQD_EOP_WPTR);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4522

mqd->cp_hqd_ctx_save_base_addr_lo = RREG32(mmCP_HQD_CTX_SAVE_BASE_ADDR_LO);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4523

mqd->cp_hqd_ctx_save_base_addr_hi = RREG32(mmCP_HQD_CTX_SAVE_BASE_ADDR_HI);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4524

mqd->cp_hqd_cntl_stack_offset = RREG32(mmCP_HQD_CNTL_STACK_OFFSET);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4525

mqd->cp_hqd_cntl_stack_size = RREG32(mmCP_HQD_CNTL_STACK_SIZE);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4526

mqd->cp_hqd_wg_state_offset = RREG32(mmCP_HQD_WG_STATE_OFFSET);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4527

mqd->cp_hqd_ctx_save_size = RREG32(mmCP_HQD_CTX_SAVE_SIZE);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4528

mqd->cp_hqd_eop_done_events = RREG32(mmCP_HQD_EOP_EVENTS);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4529

mqd->cp_hqd_error = RREG32(mmCP_HQD_ERROR);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4530

mqd->cp_hqd_eop_wptr_mem = RREG32(mmCP_HQD_EOP_WPTR_MEM);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4531

mqd->cp_hqd_eop_dones = RREG32(mmCP_HQD_EOP_DONES);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4535

mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4802

if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE)

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4803

|| RREG32(mmGRBM_STATUS2) != 0x8)

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4813

if (RREG32(mmGRBM_STATUS2) != 0x8)

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4897

tmp = RREG32(mmGRBM_STATUS);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4914

tmp = RREG32(mmGRBM_STATUS2);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4933

tmp = RREG32(mmSRBM_STATUS);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

5007

tmp = RREG32(mmGMCON_DEBUG);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

5015

tmp = RREG32(mmGRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

5019

tmp = RREG32(mmGRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

5025

tmp = RREG32(mmGRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

5029

tmp = RREG32(mmSRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

5033

tmp = RREG32(mmSRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

5039

tmp = RREG32(mmSRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

5043

tmp = RREG32(mmGMCON_DEBUG);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

5110

clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

5111

((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

5162

return RREG32(mmSQ_IND_DATA);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

5177

*(out++) = RREG32(mmSQ_IND_DATA);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

5348

RREG32(mmDB_RENDER_CONTROL);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

5444

data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

5449

data = RREG32(mmRLC_CGCG_CGLS_CTRL);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

5458

data = RREG32(mmCGTS_SM_CTRL_REG);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

5467

data = RREG32(mmRLC_MEM_SLP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

5472

data = RREG32(mmCP_MEM_SLP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

5487

data = RREG32(mmRLC_SERDES_WR_CTRL);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

5529

rlc_setting = RREG32(mmRLC_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

5540

data = RREG32(mmRLC_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

5548

if ((RREG32(mmRLC_GPM_STAT) &

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

5557

if (!REG_GET_FIELD(RREG32(mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

5568

data = RREG32(mmRLC_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

5574

if (!REG_GET_FIELD(RREG32(mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

5590

data = RREG32(mmRLC_SPM_VMID);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

5635

temp = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

5657

temp = data = RREG32(mmCGTS_SM_CTRL_REG);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

5676

temp = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

5685

data = RREG32(mmRLC_MEM_SLP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

5692

data = RREG32(mmCP_MEM_SLP_CNTL);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

5699

temp = data = RREG32(mmCGTS_SM_CTRL_REG);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

5723

temp = data = RREG32(mmRLC_CGCG_CGLS_CTRL);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

5726

temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

5750

temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

5771

temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

5778

RREG32(mmCB_CGTT_SCLK_CTRL);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

5779

RREG32(mmCB_CGTT_SCLK_CTRL);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

5780

RREG32(mmCB_CGTT_SCLK_CTRL);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

5781

RREG32(mmCB_CGTT_SCLK_CTRL);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

6019

return RREG32(mmCP_RB0_WPTR);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

6032

(void)RREG32(mmCP_RB0_WPTR);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

6429

mec_int_cntl = RREG32(mec_int_cntl_reg);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

6434

mec_int_cntl = RREG32(mec_int_cntl_reg);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

6703

sq_edc_source = REG_GET_FIELD(RREG32(mmSQ_EDC_INFO), SQ_EDC_INFO, SOURCE);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

7040

adev->gds.gds_size = RREG32(mmGDS_VMID0_SIZE);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

7043

adev->gds.gds_compute_max_wave_id = RREG32(mmGDS_COMPUTE_MAX_WAVE_ID);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

7064

data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG) |

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

7065

RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

856

tmp = RREG32(mmSCRATCH_REG0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

1213

tmp = RREG32(scratch);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

2851

tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

2935

default_data = data = RREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS));

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

2963

data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL));

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

2976

data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2));

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

2981

data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3));

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

2986

data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL));

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3003

default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3017

default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3031

default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3044

default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3057

default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3066

data = RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_RENDER_CONTROL));

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3074

default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3087

default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

7021

RREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_0_edc_counter_regs[i]));

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

7084

RREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_0_edc_counter_regs[i]));

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

7391

adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_9[i]));

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

7410

RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME2_HEADER_DUMP));

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

7413

RREG32(SOC15_REG_ENTRY_OFFSET(

drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c

886

reg_value = RREG32(SOC15_REG_ENTRY_OFFSET(

drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c

920

RREG32(SOC15_REG_ENTRY_OFFSET(

drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c

990

reg_value = RREG32(SOC15_REG_ENTRY_OFFSET(

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c

1527

data = RREG32(SOC15_REG_ENTRY_OFFSET(

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c

1634

data = RREG32(SOC15_REG_ENTRY_OFFSET(blk->data_reg));

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c

1696

value = RREG32(SOC15_REG_ENTRY_OFFSET(

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c

1726

reg_value = RREG32(SOC15_REG_ENTRY_OFFSET(

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1679

pre_data = RREG32(reg);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

428

tmp = RREG32(scratch_reg0_offset);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

440

tmp = RREG32(scratch_reg0_offset);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

4644

RREG32(SOC15_REG_ENTRY_OFFSET_INST(gc_reg_list_9_4_3[i],

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

4672

RREG32(SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id),

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

4678

RREG32(SOC15_REG_ENTRY_OFFSET_INST(

drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c

134

RREG32(hub->vm_l2_pro_fault_status);

drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c

136

status = RREG32(hub->vm_l2_pro_fault_status);

drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c

211

value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)

drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c

131

RREG32(hub->vm_l2_pro_fault_status);

drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c

133

status = RREG32(hub->vm_l2_pro_fault_status);

drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c

205

*p_pasid = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid) & 0xffff;

drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c

127

RREG32(hub->vm_l2_pro_fault_status);

drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c

129

status = RREG32(hub->vm_l2_pro_fault_status);

drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c

201

*p_pasid = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid) & 0xffff;

drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c

213

RREG32(hub->vm_l2_pro_fault_status);

drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c

215

status = RREG32(hub->vm_l2_pro_fault_status);

drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c

245

*p_pasid = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid) & 0xffff;

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

1009

tmp = RREG32(mmSRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

1013

tmp = RREG32(mmSRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

1019

tmp = RREG32(mmSRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

1045

tmp = RREG32(mmVM_CONTEXT0_CNTL);

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

1048

tmp = RREG32(mmVM_CONTEXT1_CNTL);

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

1053

tmp = RREG32(mmVM_CONTEXT0_CNTL);

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

1056

tmp = RREG32(mmVM_CONTEXT1_CNTL);

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

1079

addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

1080

status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

131

if (((RREG32(mmMC_SEQ_MISC0) & 0xff000000) >> 24) == 0x58)

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

168

running = RREG32(mmMC_SEQ_SUP_CNTL) & MC_SEQ_SUP_CNTL__RUN_MASK;

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

192

if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0_MASK)

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

197

if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1_MASK)

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

210

u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

246

tmp = RREG32(mmVGA_HDP_CONTROL);

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

251

tmp = RREG32(mmVGA_RENDER_CONTROL);

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

277

tmp = RREG32(mmMC_ARB_RAMCFG);

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

285

tmp = RREG32(mmMC_SHARED_CHMAP);

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

318

adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

319

adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

399

tmp = RREG32(mmVM_CONTEXT1_CNTL);

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

430

tmp = RREG32(mmVM_PRT_CNTL);

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

673

orig = data = RREG32(mc_cg_registers[i]);

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

690

orig = data = RREG32(mc_cg_registers[i]);

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

728

orig = data = RREG32(mmHDP_HOST_PATH_CNTL);

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

744

orig = data = RREG32(mmHDP_MEM_POWER_LS);

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

75

blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

797

u32 d1vga_control = RREG32(mmD1VGA_CONTROL);

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

803

u32 viewport = RREG32(mmVIEWPORT_SIZE);

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

822

u32 tmp = RREG32(mmMC_SEQ_MISC0);

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

878

u64 tmp = RREG32(mmMC_VM_FB_OFFSET);

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

94

tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

962

u32 tmp = RREG32(mmSRBM_STATUS);

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

990

u32 tmp = RREG32(mmSRBM_STATUS);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

1059

u64 tmp = RREG32(mmMC_VM_FB_OFFSET);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

1149

u32 tmp = RREG32(mmSRBM_STATUS);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

117

tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

1176

u32 tmp = RREG32(mmSRBM_STATUS);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

1194

tmp = RREG32(mmSRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

1198

tmp = RREG32(mmSRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

1204

tmp = RREG32(mmSRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

1232

tmp = RREG32(mmVM_CONTEXT0_CNTL);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

1236

tmp = RREG32(mmVM_CONTEXT1_CNTL);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

1242

tmp = RREG32(mmVM_CONTEXT0_CNTL);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

1246

tmp = RREG32(mmVM_CONTEXT1_CNTL);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

1269

addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

1270

status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

1271

mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

199

running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

222

if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

228

if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

241

u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

283

tmp = RREG32(mmVGA_HDP_CONTROL);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

288

tmp = RREG32(mmVGA_RENDER_CONTROL);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

307

tmp = RREG32(mmHDP_MISC_CNTL);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

311

tmp = RREG32(mmHDP_HOST_PATH_CNTL);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

334

tmp = RREG32(mmMC_ARB_RAMCFG);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

340

tmp = RREG32(mmMC_SHARED_CHMAP);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

374

adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

375

adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

389

adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

442

u32 tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

450

RREG32(mmVM_INVALIDATE_RESPONSE);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

527

tmp = RREG32(mmVM_CONTEXT1_CNTL);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

558

tmp = RREG32(mmVM_PRT_CNTL);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

626

tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

634

tmp = RREG32(mmVM_L2_CNTL);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

648

tmp = RREG32(mmVM_L2_CNTL3);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

660

tmp = RREG32(mmVM_CONTEXT0_CNTL);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

690

tmp = RREG32(mmVM_CONTEXT1_CNTL);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

702

tmp = RREG32(mmCHUB_CONTROL);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

746

tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

752

tmp = RREG32(mmVM_L2_CNTL);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

833

orig = data = RREG32(mc_cg_registers[i]);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

850

orig = data = RREG32(mc_cg_registers[i]);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

888

orig = data = RREG32(mmHDP_HOST_PATH_CNTL);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

904

orig = data = RREG32(mmHDP_MEM_POWER_LS);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

968

u32 d1vga_control = RREG32(mmD1VGA_CONTROL);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

974

u32 viewport = RREG32(mmVIEWPORT_SIZE);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

99

blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

994

u32 tmp = RREG32(mmMC_SEQ_MISC0);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

1076

u32 d1vga_control = RREG32(mmD1VGA_CONTROL);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

1082

u32 viewport = RREG32(mmVIEWPORT_SIZE);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

1108

tmp = RREG32(mmMC_SEQ_MISC0_FIJI);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

1110

tmp = RREG32(mmMC_SEQ_MISC0);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

1174

u64 tmp = RREG32(mmMC_VM_FB_OFFSET);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

1272

u32 tmp = RREG32(mmSRBM_STATUS);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

1289

tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

1307

u32 tmp = RREG32(mmSRBM_STATUS);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

1356

tmp = RREG32(mmSRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

1360

tmp = RREG32(mmSRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

1366

tmp = RREG32(mmSRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

1403

tmp = RREG32(mmVM_CONTEXT0_CNTL);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

1407

tmp = RREG32(mmVM_CONTEXT1_CNTL);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

1413

tmp = RREG32(mmVM_CONTEXT0_CNTL);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

1417

tmp = RREG32(mmVM_CONTEXT1_CNTL);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

1447

addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

1448

status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

1449

mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

1514

data = RREG32(mmMC_HUB_MISC_HUB_CG);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

1518

data = RREG32(mmMC_HUB_MISC_SIP_CG);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

1522

data = RREG32(mmMC_HUB_MISC_VM_CG);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

1526

data = RREG32(mmMC_XPB_CLK_GAT);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

1530

data = RREG32(mmATC_MISC_CG);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

1534

data = RREG32(mmMC_CITF_MISC_WR_CG);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

1538

data = RREG32(mmMC_CITF_MISC_RD_CG);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

1542

data = RREG32(mmMC_CITF_MISC_VM_CG);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

1546

data = RREG32(mmVM_L2_CG);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

1550

data = RREG32(mmMC_HUB_MISC_HUB_CG);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

1554

data = RREG32(mmMC_HUB_MISC_SIP_CG);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

1558

data = RREG32(mmMC_HUB_MISC_VM_CG);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

1562

data = RREG32(mmMC_XPB_CLK_GAT);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

1566

data = RREG32(mmATC_MISC_CG);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

1570

data = RREG32(mmMC_CITF_MISC_WR_CG);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

1574

data = RREG32(mmMC_CITF_MISC_RD_CG);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

1578

data = RREG32(mmMC_CITF_MISC_VM_CG);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

1582

data = RREG32(mmVM_L2_CG);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

1594

data = RREG32(mmMC_HUB_MISC_HUB_CG);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

1598

data = RREG32(mmMC_HUB_MISC_SIP_CG);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

1602

data = RREG32(mmMC_HUB_MISC_VM_CG);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

1606

data = RREG32(mmMC_XPB_CLK_GAT);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

1610

data = RREG32(mmATC_MISC_CG);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

1614

data = RREG32(mmMC_CITF_MISC_WR_CG);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

1618

data = RREG32(mmMC_CITF_MISC_RD_CG);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

1622

data = RREG32(mmMC_CITF_MISC_VM_CG);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

1626

data = RREG32(mmVM_L2_CG);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

1630

data = RREG32(mmMC_HUB_MISC_HUB_CG);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

1634

data = RREG32(mmMC_HUB_MISC_SIP_CG);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

1638

data = RREG32(mmMC_HUB_MISC_VM_CG);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

1642

data = RREG32(mmMC_XPB_CLK_GAT);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

1646

data = RREG32(mmATC_MISC_CG);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

1650

data = RREG32(mmMC_CITF_MISC_WR_CG);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

1654

data = RREG32(mmMC_CITF_MISC_RD_CG);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

1658

data = RREG32(mmMC_CITF_MISC_VM_CG);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

1662

data = RREG32(mmVM_L2_CG);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

1704

data = RREG32(mmMC_HUB_MISC_HUB_CG);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

181

blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

199

tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

247

if (RREG32(mmMC_SEQ_IO_DEBUG_DATA) == 0x05b4dc40)

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

309

running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

332

if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

338

if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

378

data = RREG32(mmMC_SEQ_MISC0);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

402

data = RREG32(mmMC_SEQ_MISC0);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

417

base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

458

tmp = RREG32(mmVGA_HDP_CONTROL);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

463

tmp = RREG32(mmVGA_RENDER_CONTROL);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

493

tmp = RREG32(mmHDP_MISC_CNTL);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

497

tmp = RREG32(mmHDP_HOST_PATH_CNTL);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

520

tmp = RREG32(mmMC_ARB_RAMCFG);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

526

tmp = RREG32(mmMC_SHARED_CHMAP);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

560

tmp = RREG32(mmCONFIG_MEMSIZE);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

580

adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

633

u32 tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

641

RREG32(mmVM_INVALIDATE_RESPONSE);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

742

tmp = RREG32(mmVM_CONTEXT1_CNTL);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

775

tmp = RREG32(mmVM_PRT_CNTL);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

843

tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

851

tmp = RREG32(mmVM_L2_CNTL);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

860

tmp = RREG32(mmVM_L2_CNTL2);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

866

tmp = RREG32(mmVM_L2_CNTL3);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

872

tmp = RREG32(mmVM_L2_CNTL4);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

893

tmp = RREG32(mmVM_CONTEXT0_CNTL);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

923

tmp = RREG32(mmVM_CONTEXT1_CNTL);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

980

tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

986

tmp = RREG32(mmVM_L2_CNTL);

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

1829

vram_info = RREG32(regBIF_BIOS_SCRATCH_4);

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

431

tmp = RREG32(reg);

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

437

tmp = RREG32(reg);

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

445

tmp = RREG32(reg);

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

451

tmp = RREG32(reg);

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

631

RREG32(hub->vm_l2_pro_fault_status);

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

633

status = RREG32(hub->vm_l2_pro_fault_status);

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

787

value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)

drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c

102

def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL));

drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c

132

data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));

drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c

92

def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));

drivers/gpu/drm/amd/amdgpu/iceland_ih.c

117

interrupt_cntl = RREG32(mmINTERRUPT_CNTL);

drivers/gpu/drm/amd/amdgpu/iceland_ih.c

148

ih_cntl = RREG32(mmIH_CNTL);

drivers/gpu/drm/amd/amdgpu/iceland_ih.c

207

wptr = RREG32(mmIH_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/iceland_ih.c

220

tmp = RREG32(mmIH_RB_CNTL);

drivers/gpu/drm/amd/amdgpu/iceland_ih.c

351

u32 tmp = RREG32(mmSRBM_STATUS);

drivers/gpu/drm/amd/amdgpu/iceland_ih.c

367

tmp = RREG32(mmSRBM_STATUS);

drivers/gpu/drm/amd/amdgpu/iceland_ih.c

379

u32 tmp = RREG32(mmSRBM_STATUS);

drivers/gpu/drm/amd/amdgpu/iceland_ih.c

386

tmp = RREG32(mmSRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/iceland_ih.c

390

tmp = RREG32(mmSRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/iceland_ih.c

396

tmp = RREG32(mmSRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/iceland_ih.c

62

u32 ih_cntl = RREG32(mmIH_CNTL);

drivers/gpu/drm/amd/amdgpu/iceland_ih.c

63

u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);

drivers/gpu/drm/amd/amdgpu/iceland_ih.c

81

u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);

drivers/gpu/drm/amd/amdgpu/iceland_ih.c

82

u32 ih_cntl = RREG32(mmIH_CNTL);

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

136

tmp = RREG32(ih_regs->ih_rb_cntl);

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

277

tmp = RREG32(ih_regs->ih_rb_cntl);

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

136

tmp = RREG32(ih_regs->ih_rb_cntl);

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

249

tmp = RREG32(ih_regs->ih_rb_cntl);

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

136

tmp = RREG32(ih_regs->ih_rb_cntl);

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

249

tmp = RREG32(ih_regs->ih_rb_cntl);

drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c

249

data = RREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS)) & ~0x1;

drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c

261

data = RREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS));

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

473

if (!(RREG32(reg) & value))

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

496

if (!(RREG32(reg) & value))

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

807

RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_0_edc_cnt_regs[i]));

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

825

RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_0_edc_cnt_regs[i]));

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

1281

RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_7_edc_cnt_regs[i]));

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

1321

RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_7_ea_err_status_regs[i]));

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

1340

reg_value = RREG32(SOC15_REG_ENTRY_OFFSET(

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

1642

RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v9_4_edc_cnt_regs[i]));

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

1659

RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v9_4_edc_cnt_regs[i]));

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

1684

RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v9_4_err_status_regs[i]));

drivers/gpu/drm/amd/amdgpu/navi10_ih.c

161

tmp = RREG32(ih_regs->ih_rb_cntl);

drivers/gpu/drm/amd/amdgpu/navi10_ih.c

275

tmp = RREG32(ih_regs->ih_rb_cntl);

drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c

117

u32 doorbell_range = RREG32(reg);

drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c

140

u32 doorbell_range = RREG32(reg);

drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c

94

u32 doorbell_range = RREG32(reg);

drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c

73

u32 doorbell_range = RREG32(reg);

drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c

89

u32 doorbell_range = RREG32(reg);

drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c

168

doorbell_range = RREG32(reg);

drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c

193

doorbell_range = RREG32(reg);

drivers/gpu/drm/amd/amdgpu/nv.c

288

r = RREG32(data);

drivers/gpu/drm/amd/amdgpu/nv.c

366

val = RREG32(reg_offset);

drivers/gpu/drm/amd/amdgpu/nv.c

383

return RREG32(reg_offset);

drivers/gpu/drm/amd/amdgpu/psp_v13_0.c

902

pmfw_ver = RREG32(regMP1_PUB_SCRATCH0 / 4);

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

1000

sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

1011

sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

1016

sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

205

u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2;

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

344

rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

347

ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

384

f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

428

rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

461

ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

917

u32 tmp = RREG32(mmSRBM_STATUS2);

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

933

tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

947

u32 tmp = RREG32(mmSRBM_STATUS2);

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

951

tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

958

tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

965

tmp = RREG32(mmSRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

969

tmp = RREG32(mmSRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

975

tmp = RREG32(mmSRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

995

sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

1206

u32 tmp = RREG32(mmSRBM_STATUS2);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

1222

tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

1236

u32 tmp = RREG32(mmSRBM_STATUS2);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

1303

tmp = RREG32(mmSRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

1307

tmp = RREG32(mmSRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

1313

tmp = RREG32(mmSRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

1333

sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

1338

sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

1349

sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

1354

sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

1432

temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

1446

temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

1471

temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

1479

temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

1526

data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[0]);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

1531

data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[0]);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

369

wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2;

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

520

rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

523

ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

579

f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

621

f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

668

rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

695

doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

713

wptr_poll_cntl = RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i]);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

731

ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

1258

def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

1265

def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

1277

def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

128

RREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset)))

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

1283

def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

1289

def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

2343

data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

2348

data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

2388

RREG32(sdma_v4_0_get_reg_offset(adev, i,

drivers/gpu/drm/amd/amdgpu/sdma_v4_4.c

205

reg_value = RREG32(reg_offset);

drivers/gpu/drm/amd/amdgpu/sdma_v4_4.c

212

reg_value = RREG32(reg_offset);

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

103

RREG32(sdma_v4_4_2_get_reg_offset(adev, (instance), (offset)))

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

1653

uint32_t context_status = RREG32(sdma_v4_4_2_get_reg_offset(adev, instance_id, reg_offset));

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

2040

data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_CLK_CTRL));

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

2045

data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_POWER_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

2085

RREG32(sdma_v4_4_2_get_reg_offset(adev, i,

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1502

u32 tmp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1518

sdma0 = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1519

sdma1 = RREG32(sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1574

freeze = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_FREEZE));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1579

freeze = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_FREEZE));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1587

stat1_reg = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_STATUS1_REG));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1595

f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1599

cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1616

freeze = RREG32(sdma_v5_0_get_reg_offset(adev, inst_id, mmSDMA0_FREEZE));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1685

sdma_cntl = RREG32(reg_offset);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1758

def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1771

def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1795

def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1802

def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1850

data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1855

data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1896

RREG32(sdma_v5_0_get_reg_offset(adev, i,

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

629

f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

672

f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

793

temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

801

temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

807

temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

816

temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

975

m->sdmax_rlcx_rb_wptr_poll_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, 0,

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

986

m->sdmax_rlcx_ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, 0,

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1415

u32 tmp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1431

sdma0 = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1432

sdma1 = RREG32(sdma_v5_2_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1433

sdma2 = RREG32(sdma_v5_2_get_reg_offset(adev, 2, mmSDMA0_STATUS_REG));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1434

sdma3 = RREG32(sdma_v5_2_get_reg_offset(adev, 3, mmSDMA0_STATUS_REG));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1482

freeze = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_FREEZE));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1487

freeze = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_FREEZE));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1496

stat1_reg = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_STATUS1_REG));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1504

f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1508

cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1526

freeze = RREG32(sdma_v5_2_get_reg_offset(adev, inst_id, mmSDMA0_FREEZE));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1591

sdma_cntl = RREG32(reg_offset);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1724

def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1735

def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1762

def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1769

def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1822

data = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1898

RREG32(sdma_v5_2_get_reg_offset(adev, i,

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

195

wptr = RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

197

wptr |= RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

488

f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

519

f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

640

temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

663

temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

875

m->sdmax_rlcx_rb_wptr_poll_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, 0,

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

886

m->sdmax_rlcx_ib_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, 0,

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

1508

u32 tmp = RREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_STATUS_REG));

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

1524

sdma0 = RREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_STATUS_REG));

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

1525

sdma1 = RREG32(sdma_v6_0_get_reg_offset(adev, 1, regSDMA0_STATUS_REG));

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

1614

sdma_cntl = RREG32(reg_offset);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

1734

RREG32(sdma_v6_0_get_reg_offset(adev, i,

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

437

f32_cntl = RREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_CNTL));

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

1463

u32 tmp = RREG32(sdma_v7_0_get_reg_offset(adev, i, regSDMA0_STATUS_REG));

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

1479

sdma0 = RREG32(sdma_v7_0_get_reg_offset(adev, 0, regSDMA0_STATUS_REG));

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

1480

sdma1 = RREG32(sdma_v7_0_get_reg_offset(adev, 1, regSDMA0_STATUS_REG));

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

1547

sdma_cntl = RREG32(reg_offset);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

1666

RREG32(sdma_v7_0_get_reg_offset(adev, i,

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

1397

u32 tmp = RREG32(sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_STATUS_REG));

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

1414

sdma[j] = RREG32(sdma_v7_1_get_reg_offset(adev,

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

1484

sdma_cntl = RREG32(reg_offset);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

1595

RREG32(sdma_v7_1_get_reg_offset(adev, i,

drivers/gpu/drm/amd/amdgpu/si.c

1032

(void)RREG32(AMDGPU_PCIE_INDEX);

drivers/gpu/drm/amd/amdgpu/si.c

1033

r = RREG32(AMDGPU_PCIE_DATA);

drivers/gpu/drm/amd/amdgpu/si.c

1044

(void)RREG32(AMDGPU_PCIE_INDEX);

drivers/gpu/drm/amd/amdgpu/si.c

1046

(void)RREG32(AMDGPU_PCIE_DATA);

drivers/gpu/drm/amd/amdgpu/si.c

1057

(void)RREG32(PCIE_PORT_INDEX);

drivers/gpu/drm/amd/amdgpu/si.c

1058

r = RREG32(PCIE_PORT_DATA);

drivers/gpu/drm/amd/amdgpu/si.c

1069

(void)RREG32(PCIE_PORT_INDEX);

drivers/gpu/drm/amd/amdgpu/si.c

1071

(void)RREG32(PCIE_PORT_DATA);

drivers/gpu/drm/amd/amdgpu/si.c

1082

r = RREG32(mmSMC_IND_DATA_0);

drivers/gpu/drm/amd/amdgpu/si.c

1104

r = RREG32(mmUVD_CTX_DATA);

drivers/gpu/drm/amd/amdgpu/si.c

1193

val = RREG32(reg_offset);

drivers/gpu/drm/amd/amdgpu/si.c

1242

return RREG32(reg_offset);

drivers/gpu/drm/amd/amdgpu/si.c

1274

bus_cntl = RREG32(mmBUS_CNTL);

drivers/gpu/drm/amd/amdgpu/si.c

1276

d1vga_control = RREG32(mmD1VGA_CONTROL);

drivers/gpu/drm/amd/amdgpu/si.c

1277

d2vga_control = RREG32(mmD2VGA_CONTROL);

drivers/gpu/drm/amd/amdgpu/si.c

1278

vga_render_control = RREG32(mmVGA_RENDER_CONTROL);

drivers/gpu/drm/amd/amdgpu/si.c

1280

rom_cntl = RREG32(R600_ROM_CNTL);

drivers/gpu/drm/amd/amdgpu/si.c

1332

dw_ptr[i] = RREG32(mmROM_DATA);

drivers/gpu/drm/amd/amdgpu/si.c

1341

tmp = RREG32(mmCG_SPLL_FUNC_CNTL);

drivers/gpu/drm/amd/amdgpu/si.c

1345

tmp = RREG32(mmCG_SPLL_FUNC_CNTL_2);

drivers/gpu/drm/amd/amdgpu/si.c

1350

if (RREG32(mmCG_SPLL_STATUS) & CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK)

drivers/gpu/drm/amd/amdgpu/si.c

1355

tmp = RREG32(mmCG_SPLL_FUNC_CNTL_2);

drivers/gpu/drm/amd/amdgpu/si.c

1360

tmp = RREG32(MPLL_CNTL_MODE);

drivers/gpu/drm/amd/amdgpu/si.c

1369

tmp = RREG32(mmSPLL_CNTL_MODE);

drivers/gpu/drm/amd/amdgpu/si.c

1373

tmp = RREG32(mmCG_SPLL_FUNC_CNTL);

drivers/gpu/drm/amd/amdgpu/si.c

1377

tmp = RREG32(mmCG_SPLL_FUNC_CNTL);

drivers/gpu/drm/amd/amdgpu/si.c

1381

tmp = RREG32(mmSPLL_CNTL_MODE);

drivers/gpu/drm/amd/amdgpu/si.c

1406

if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff) {

drivers/gpu/drm/amd/amdgpu/si.c

1458

return RREG32(mmCONFIG_MEMSIZE);

drivers/gpu/drm/amd/amdgpu/si.c

1465

temp = RREG32(mmCONFIG_CNTL);

drivers/gpu/drm/amd/amdgpu/si.c

1480

tmp = RREG32(mmCG_CLKPIN_CNTL_2);

drivers/gpu/drm/amd/amdgpu/si.c

1484

tmp = RREG32(mmCG_CLKPIN_CNTL);

drivers/gpu/drm/amd/amdgpu/si.c

1495

RREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL);

drivers/gpu/drm/amd/amdgpu/si.c

1506

RREG32(mmHDP_DEBUG0);

drivers/gpu/drm/amd/amdgpu/si.c

1663

if ((RREG32(cg_upll_func_cntl) & mask) == mask)

drivers/gpu/drm/amd/amdgpu/si.c

2032

return (RREG32(mmCC_DRM_ID_STRAPS) & CC_DRM_ID_STRAPS__ATI_REV_ID_MASK)

drivers/gpu/drm/amd/amdgpu/si.c

2387

r = RREG32(EVERGREEN_PIF_PHY0_DATA);

drivers/gpu/drm/amd/amdgpu/si.c

2409

r = RREG32(EVERGREEN_PIF_PHY1_DATA);

drivers/gpu/drm/amd/amdgpu/si.c

2567

orig = data = RREG32(mmTHM_CLK_CNTL);

drivers/gpu/drm/amd/amdgpu/si.c

2573

orig = data = RREG32(mmMISC_CLK_CNTL);

drivers/gpu/drm/amd/amdgpu/si.c

2579

orig = data = RREG32(mmCG_CLKPIN_CNTL);

drivers/gpu/drm/amd/amdgpu/si.c

2584

orig = data = RREG32(mmCG_CLKPIN_CNTL_2);

drivers/gpu/drm/amd/amdgpu/si.c

2589

orig = data = RREG32(mmMPLL_BYPASSCLK_SEL);

drivers/gpu/drm/amd/amdgpu/si.c

2595

orig = data = RREG32(mmSPLL_CNTL_MODE);

drivers/gpu/drm/amd/amdgpu/si_dma.c

136

rb_cntl = RREG32(mmDMA_GFX_RB_CNTL + sdma_offsets[i]);

drivers/gpu/drm/amd/amdgpu/si_dma.c

183

dma_cntl = RREG32(mmDMA_CNTL + sdma_offsets[i]);

drivers/gpu/drm/amd/amdgpu/si_dma.c

564

u32 tmp = RREG32(mmSRBM_STATUS2);

drivers/gpu/drm/amd/amdgpu/si_dma.c

602

sdma_cntl = RREG32(mmDMA_CNTL + DMA0_REGISTER_OFFSET);

drivers/gpu/drm/amd/amdgpu/si_dma.c

607

sdma_cntl = RREG32(mmDMA_CNTL + DMA0_REGISTER_OFFSET);

drivers/gpu/drm/amd/amdgpu/si_dma.c

618

sdma_cntl = RREG32(mmDMA_CNTL + DMA1_REGISTER_OFFSET);

drivers/gpu/drm/amd/amdgpu/si_dma.c

623

sdma_cntl = RREG32(mmDMA_CNTL + DMA1_REGISTER_OFFSET);

drivers/gpu/drm/amd/amdgpu/si_dma.c

664

orig = data = RREG32(mmDMA_POWER_CNTL + offset);

drivers/gpu/drm/amd/amdgpu/si_dma.c

67

return (RREG32(mmDMA_GFX_RB_WPTR + sdma_offsets[me]) & 0x3fffc) >> 2;

drivers/gpu/drm/amd/amdgpu/si_dma.c

676

orig = data = RREG32(mmDMA_POWER_CNTL + offset);

drivers/gpu/drm/amd/amdgpu/si_dma.c

681

orig = data = RREG32(mmDMA_CLK_CTRL + offset);

drivers/gpu/drm/amd/amdgpu/si_ih.c

126

tmp = RREG32(IH_RB_CNTL);

drivers/gpu/drm/amd/amdgpu/si_ih.c

229

u32 tmp = RREG32(mmSRBM_STATUS);

drivers/gpu/drm/amd/amdgpu/si_ih.c

255

u32 tmp = RREG32(mmSRBM_STATUS);

drivers/gpu/drm/amd/amdgpu/si_ih.c

261

tmp = RREG32(mmSRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/si_ih.c

265

tmp = RREG32(mmSRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/si_ih.c

271

tmp = RREG32(mmSRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/si_ih.c

38

u32 ih_cntl = RREG32(IH_CNTL);

drivers/gpu/drm/amd/amdgpu/si_ih.c

39

u32 ih_rb_cntl = RREG32(IH_RB_CNTL);

drivers/gpu/drm/amd/amdgpu/si_ih.c

50

u32 ih_rb_cntl = RREG32(IH_RB_CNTL);

drivers/gpu/drm/amd/amdgpu/si_ih.c

51

u32 ih_cntl = RREG32(IH_CNTL);

drivers/gpu/drm/amd/amdgpu/si_ih.c

72

interrupt_cntl = RREG32(INTERRUPT_CNTL);

drivers/gpu/drm/amd/amdgpu/soc15.c

1372

def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));

drivers/gpu/drm/amd/amdgpu/soc15.c

1401

def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));

drivers/gpu/drm/amd/amdgpu/soc15.c

1484

data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));

drivers/gpu/drm/amd/amdgpu/soc15.c

1489

data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));

drivers/gpu/drm/amd/amdgpu/soc15.c

250

r = RREG32(data);

drivers/gpu/drm/amd/amdgpu/soc15.c

278

r = RREG32(data);

drivers/gpu/drm/amd/amdgpu/soc15.c

413

val = RREG32(reg_offset);

drivers/gpu/drm/amd/amdgpu/soc15.c

432

return RREG32(reg_offset);

drivers/gpu/drm/amd/amdgpu/soc15.c

487

RREG32_SOC15_IP(GC, reg) : RREG32(reg);

drivers/gpu/drm/amd/amdgpu/soc15_common.h

125

u32 tmp = RREG32(r1); \

drivers/gpu/drm/amd/amdgpu/soc15_common.h

48

RREG32(reg))

drivers/gpu/drm/amd/amdgpu/soc21.c

234

r = RREG32(data);

drivers/gpu/drm/amd/amdgpu/soc21.c

318

val = RREG32(reg_offset);

drivers/gpu/drm/amd/amdgpu/soc21.c

335

return RREG32(reg_offset);

drivers/gpu/drm/amd/amdgpu/soc24.c

146

val = RREG32(reg_offset);

drivers/gpu/drm/amd/amdgpu/soc24.c

164

return RREG32(reg_offset);

drivers/gpu/drm/amd/amdgpu/soc_v1_0.c

160

val = RREG32(reg_offset);

drivers/gpu/drm/amd/amdgpu/soc_v1_0.c

178

return RREG32(reg_offset);

drivers/gpu/drm/amd/amdgpu/tonga_ih.c

113

interrupt_cntl = RREG32(mmINTERRUPT_CNTL);

drivers/gpu/drm/amd/amdgpu/tonga_ih.c

145

ih_doorbell_rtpr = RREG32(mmIH_DOORBELL_RPTR);

drivers/gpu/drm/amd/amdgpu/tonga_ih.c

209

wptr = RREG32(mmIH_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/tonga_ih.c

224

tmp = RREG32(mmIH_RB_CNTL);

drivers/gpu/drm/amd/amdgpu/tonga_ih.c

369

u32 tmp = RREG32(mmSRBM_STATUS);

drivers/gpu/drm/amd/amdgpu/tonga_ih.c

385

tmp = RREG32(mmSRBM_STATUS);

drivers/gpu/drm/amd/amdgpu/tonga_ih.c

397

u32 tmp = RREG32(mmSRBM_STATUS);

drivers/gpu/drm/amd/amdgpu/tonga_ih.c

442

tmp = RREG32(mmSRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/tonga_ih.c

446

tmp = RREG32(mmSRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/tonga_ih.c

452

tmp = RREG32(mmSRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/tonga_ih.c

62

u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);

drivers/gpu/drm/amd/amdgpu/tonga_ih.c

79

u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);

drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c

155

tmp = RREG32(mmUVD_CONTEXT_ID);

drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c

213

tmp = RREG32(mmUVD_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c

291

if (RREG32(mmUVD_FW_STATUS) & UVD_FW_STATUS__DONE_MASK)

drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c

298

if (!(RREG32(mmUVD_FW_STATUS) & UVD_FW_STATUS__PASS_MASK))

drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c

303

if (!(RREG32(mmUVD_FW_STATUS) & UVD_FW_STATUS__BUSY_MASK))

drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c

358

tmp = RREG32(mmUVD_MPC_CNTL);

drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c

385

status = RREG32(mmUVD_STATUS);

drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c

426

ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c

456

status = RREG32(mmUVD_STATUS);

drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c

467

status = RREG32(mmUVD_LMI_STATUS);

drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c

48

return RREG32(mmUVD_RBC_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c

481

status = RREG32(mmUVD_LMI_STATUS);

drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c

605

orig = data = RREG32(mmUVD_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c

614

orig = data = RREG32(mmUVD_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c

62

return RREG32(mmUVD_RBC_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c

722

if (RREG32(mmUVD_STATUS) != 0)

drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c

786

return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);

drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c

795

if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK))

drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c

215

if (RREG32(mmUVD_STATUS) != 0)

drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c

319

tmp = RREG32(mmUVD_MPC_CNTL);

drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c

348

status = RREG32(mmUVD_STATUS);

drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c

389

ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c

419

status = RREG32(mmUVD_STATUS);

drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c

430

status = RREG32(mmUVD_LMI_STATUS);

drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c

444

status = RREG32(mmUVD_LMI_STATUS);

drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c

522

tmp = RREG32(mmUVD_CONTEXT_ID);

drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c

619

orig = data = RREG32(mmUVD_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c

62

return RREG32(mmUVD_RBC_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c

628

orig = data = RREG32(mmUVD_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c

642

tmp = RREG32(mmUVD_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c

666

return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);

drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c

675

if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK))

drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c

76

return RREG32(mmUVD_RBC_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c

213

if (RREG32(mmUVD_STATUS) != 0)

drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c

391

status = RREG32(mmUVD_STATUS);

drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c

445

ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c

536

tmp = RREG32(mmUVD_CONTEXT_ID);

drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c

587

return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);

drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c

596

if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK))

drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c

60

return RREG32(mmUVD_RBC_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c

637

data1 = RREG32(mmUVD_SUVD_CGC_GATE);

drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c

638

data3 = RREG32(mmUVD_CGC_GATE);

drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c

683

data = RREG32(mmUVD_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c

684

data2 = RREG32(mmUVD_SUVD_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c

731

data = RREG32(mmUVD_CGC_GATE);

drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c

732

data1 = RREG32(mmUVD_SUVD_CGC_GATE);

drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c

74

return RREG32(mmUVD_RBC_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c

777

orig = data = RREG32(mmUVD_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c

786

orig = data = RREG32(mmUVD_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c

854

data = RREG32(mmUVD_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

1002

tmp = RREG32(mmUVD_CONTEXT_ID);

drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

111

return RREG32(mmUVD_RBC_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

1152

return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);

drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

1172

u32 tmp = RREG32(mmSRBM_STATUS);

drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

1176

(RREG32(mmUVD_STATUS) & AMDGPU_UVD_STATUS_BUSY_MASK))

drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

1211

tmp = RREG32(mmSRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

1215

tmp = RREG32(mmSRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

1221

tmp = RREG32(mmSRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

126

return RREG32(mmUVD_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

128

return RREG32(mmUVD_RB_WPTR2);

drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

1287

data1 = RREG32(mmUVD_SUVD_CGC_GATE);

drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

1288

data3 = RREG32(mmUVD_CGC_GATE);

drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

1342

data = RREG32(mmUVD_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

1343

data2 = RREG32(mmUVD_SUVD_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

1391

data = RREG32(mmUVD_CGC_GATE);

drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

1392

data1 = RREG32(mmUVD_SUVD_CGC_GATE);

drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

1439

orig = data = RREG32(mmUVD_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

1448

orig = data = RREG32(mmUVD_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

1521

data = RREG32(mmUVD_CGC_CTRL);

drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

539

if (RREG32(mmUVD_STATUS) != 0)

drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

646

data = RREG32(mmUVD_CGC_GATE);

drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

647

data1 = RREG32(mmUVD_SUVD_CGC_GATE);

drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

808

status = RREG32(mmUVD_STATUS);

drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

81

return RREG32(mmUVD_RBC_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

862

ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

96

return RREG32(mmUVD_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

98

return RREG32(mmUVD_RB_RPTR2);

drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

101

return RREG32(mmVCE_RB_WPTR2);

drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

127

if (RREG32(mmVCE_LMI_STATUS) & 0x337f)

drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

143

if (RREG32(mmVCE_STATUS) & VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK)

drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

166

tmp = RREG32(mmVCE_CLOCK_GATING_A);

drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

170

tmp = RREG32(mmVCE_CLOCK_GATING_B);

drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

175

tmp = RREG32(mmVCE_UENC_CLOCK_GATING);

drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

179

tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);

drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

258

if (RREG32(mmVCE_FW_REG_STATUS) & VCE_FW_REG_STATUS__DONE_MASK)

drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

262

if (!(RREG32(mmVCE_FW_REG_STATUS) & VCE_FW_REG_STATUS__DONE_MASK)) {

drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

267

if (!(RREG32(mmVCE_FW_REG_STATUS) & VCE_FW_REG_STATUS__PASS_MASK)) {

drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

274

if (!(RREG32(mmVCE_FW_REG_STATUS) & VCE_FW_REG_STATUS__BUSY_MASK))

drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

278

if (RREG32(mmVCE_FW_REG_STATUS) & VCE_FW_REG_STATUS__BUSY_MASK) {

drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

295

if (RREG32(mmVCE_LMI_FW_START_KEYSEL)) {

drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

297

RREG32(mmVCE_LMI_FW_START_KEYSEL), adev->vce.keyselect);

drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

353

(RREG32(mmVCE_STATUS) & (VCE_STATUS__JOB_BUSY_MASK | VCE_STATUS__UENC_BUSY_MASK)) ||

drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

354

(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK);

drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

447

RREG32(mmVCE_STATUS), RREG32(mmSRBM_STATUS2));

drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

453

status = RREG32(mmVCE_LMI_STATUS);

drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

477

tmp = RREG32(mmVCE_CLOCK_GATING_A);

drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

481

tmp = RREG32(mmVCE_UENC_CLOCK_GATING);

drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

486

tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);

drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

490

tmp = RREG32(mmVCE_CLOCK_GATING_A);

drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

494

tmp = RREG32(mmVCE_UENC_CLOCK_GATING);

drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

499

tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);

drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

82

return RREG32(mmVCE_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

84

return RREG32(mmVCE_RB_RPTR2);

drivers/gpu/drm/amd/amdgpu/vce_v1_0.c

99

return RREG32(mmVCE_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/vce_v2_0.c

105

uint32_t status = RREG32(mmVCE_LMI_STATUS);

drivers/gpu/drm/amd/amdgpu/vce_v2_0.c

122

uint32_t status = RREG32(mmVCE_STATUS);

drivers/gpu/drm/amd/amdgpu/vce_v2_0.c

151

tmp = RREG32(mmVCE_CLOCK_GATING_A);

drivers/gpu/drm/amd/amdgpu/vce_v2_0.c

157

tmp = RREG32(mmVCE_UENC_CLOCK_GATING);

drivers/gpu/drm/amd/amdgpu/vce_v2_0.c

162

tmp = RREG32(mmVCE_CLOCK_GATING_B);

drivers/gpu/drm/amd/amdgpu/vce_v2_0.c

208

return !(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK);

drivers/gpu/drm/amd/amdgpu/vce_v2_0.c

300

status = RREG32(mmVCE_LMI_STATUS);

drivers/gpu/drm/amd/amdgpu/vce_v2_0.c

321

tmp = RREG32(mmVCE_CLOCK_GATING_B);

drivers/gpu/drm/amd/amdgpu/vce_v2_0.c

325

tmp = RREG32(mmVCE_UENC_CLOCK_GATING);

drivers/gpu/drm/amd/amdgpu/vce_v2_0.c

329

tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);

drivers/gpu/drm/amd/amdgpu/vce_v2_0.c

335

tmp = RREG32(mmVCE_CLOCK_GATING_B);

drivers/gpu/drm/amd/amdgpu/vce_v2_0.c

340

tmp = RREG32(mmVCE_UENC_CLOCK_GATING);

drivers/gpu/drm/amd/amdgpu/vce_v2_0.c

345

tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);

drivers/gpu/drm/amd/amdgpu/vce_v2_0.c

358

tmp = RREG32(mmVCE_CLOCK_GATING_B);

drivers/gpu/drm/amd/amdgpu/vce_v2_0.c

371

orig = tmp = RREG32(mmVCE_UENC_CLOCK_GATING);

drivers/gpu/drm/amd/amdgpu/vce_v2_0.c

377

orig = tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);

drivers/gpu/drm/amd/amdgpu/vce_v2_0.c

60

return RREG32(mmVCE_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/vce_v2_0.c

62

return RREG32(mmVCE_RB_RPTR2);

drivers/gpu/drm/amd/amdgpu/vce_v2_0.c

77

return RREG32(mmVCE_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/vce_v2_0.c

79

return RREG32(mmVCE_RB_WPTR2);

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

122

v = RREG32(mmVCE_RB_WPTR);

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

124

v = RREG32(mmVCE_RB_WPTR2);

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

126

v = RREG32(mmVCE_RB_WPTR3);

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

182

data = RREG32(mmVCE_CLOCK_GATING_B);

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

187

data = RREG32(mmVCE_UENC_CLOCK_GATING);

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

192

data = RREG32(mmVCE_UENC_CLOCK_GATING_2);

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

197

data = RREG32(mmVCE_UENC_REG_CLOCK_GATING);

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

201

data = RREG32(mmVCE_UENC_DMA_DCLK_CTRL);

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

208

data = RREG32(mmVCE_CLOCK_GATING_B);

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

213

data = RREG32(mmVCE_UENC_CLOCK_GATING);

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

217

data = RREG32(mmVCE_UENC_CLOCK_GATING_2);

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

221

data = RREG32(mmVCE_UENC_REG_CLOCK_GATING);

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

225

data = RREG32(mmVCE_UENC_DMA_DCLK_CTRL);

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

241

uint32_t status = RREG32(mmVCE_STATUS);

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

613

return !(RREG32(mmSRBM_STATUS2) & mask);

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

654

if (RREG32(mmVCE_STATUS) & AMDGPU_VCE_STATUS_BUSY_MASK) {

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

659

if (RREG32(mmVCE_STATUS) & AMDGPU_VCE_STATUS_BUSY_MASK) {

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

687

tmp = RREG32(mmSRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

691

tmp = RREG32(mmSRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

697

tmp = RREG32(mmSRBM_SOFT_RESET);

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

788

uint32_t data = RREG32(mmVCE_CLOCK_GATING_A);

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

794

data = RREG32(mmVCE_UENC_CLOCK_GATING);

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

856

data = RREG32(mmVCE_CLOCK_GATING_A);

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

90

v = RREG32(mmVCE_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

92

v = RREG32(mmVCE_RB_RPTR2);

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

94

v = RREG32(mmVCE_RB_RPTR3);

drivers/gpu/drm/amd/amdgpu/vce_v4_0.c

132

RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS));

drivers/gpu/drm/amd/amdgpu/vce_v4_0.c

168

data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_VMID));

drivers/gpu/drm/amd/amdgpu/vce_v4_0.c

187

data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP));

drivers/gpu/drm/amd/amdgpu/vce_v4_0.c

191

data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP));

drivers/gpu/drm/amd/amdgpu/vce_v4_0.c

67

return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR));

drivers/gpu/drm/amd/amdgpu/vce_v4_0.c

69

return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR2));

drivers/gpu/drm/amd/amdgpu/vce_v4_0.c

71

return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR3));

drivers/gpu/drm/amd/amdgpu/vce_v4_0.c

89

return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR));

drivers/gpu/drm/amd/amdgpu/vce_v4_0.c

91

return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR2));

drivers/gpu/drm/amd/amdgpu/vce_v4_0.c

93

return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR3));

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

2024

RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_1_0[j], i));

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

1845

tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9);

drivers/gpu/drm/amd/amdgpu/vega10_ih.c

105

tmp = RREG32(ih_regs->ih_rb_cntl);

drivers/gpu/drm/amd/amdgpu/vega10_ih.c

220

tmp = RREG32(ih_regs->ih_rb_cntl);

drivers/gpu/drm/amd/amdgpu/vega20_ih.c

113

tmp = RREG32(ih_regs->ih_rb_cntl);

drivers/gpu/drm/amd/amdgpu/vega20_ih.c

256

tmp = RREG32(ih_regs->ih_rb_cntl);

drivers/gpu/drm/amd/amdgpu/vi.c

1230

orig = data = RREG32(mmBIF_CLK_CTRL);

drivers/gpu/drm/amd/amdgpu/vi.c

1287

tmp = RREG32(mmBIF_DOORBELL_APER_EN);

drivers/gpu/drm/amd/amdgpu/vi.c

1306

return (RREG32(mmPCIE_EFUSE4) & PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID_MASK)

drivers/gpu/drm/amd/amdgpu/vi.c

1314

RREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL);

drivers/gpu/drm/amd/amdgpu/vi.c

1325

RREG32(mmHDP_DEBUG0);

drivers/gpu/drm/amd/amdgpu/vi.c

1763

temp = data = RREG32(mmHDP_HOST_PATH_CNTL);

drivers/gpu/drm/amd/amdgpu/vi.c

1779

temp = data = RREG32(mmHDP_MEM_POWER_LS);

drivers/gpu/drm/amd/amdgpu/vi.c

1795

temp = data = RREG32(0x157a);

drivers/gpu/drm/amd/amdgpu/vi.c

2005

data = RREG32(mmHDP_MEM_POWER_LS);

drivers/gpu/drm/amd/amdgpu/vi.c

2010

data = RREG32(mmHDP_HOST_PATH_CNTL);

drivers/gpu/drm/amd/amdgpu/vi.c

355

r = RREG32(mmMP0PUB_IND_DATA);

drivers/gpu/drm/amd/amdgpu/vi.c

377

r = RREG32(mmUVD_CTX_DATA);

drivers/gpu/drm/amd/amdgpu/vi.c

399

r = RREG32(mmDIDT_IND_DATA);

drivers/gpu/drm/amd/amdgpu/vi.c

421

r = RREG32(mmGC_CAC_IND_DATA);

drivers/gpu/drm/amd/amdgpu/vi.c

598

bus_cntl = RREG32(mmBUS_CNTL);

drivers/gpu/drm/amd/amdgpu/vi.c

600

d1vga_control = RREG32(mmD1VGA_CONTROL);

drivers/gpu/drm/amd/amdgpu/vi.c

601

d2vga_control = RREG32(mmD2VGA_CONTROL);

drivers/gpu/drm/amd/amdgpu/vi.c

602

vga_render_control = RREG32(mmVGA_RENDER_CONTROL);

drivers/gpu/drm/amd/amdgpu/vi.c

659

dw_ptr[i] = RREG32(mmSMC_IND_DATA_11);

drivers/gpu/drm/amd/amdgpu/vi.c

768

val = RREG32(reg_offset);

drivers/gpu/drm/amd/amdgpu/vi.c

835

return RREG32(reg_offset);

drivers/gpu/drm/amd/amdgpu/vi.c

884

if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff) {

drivers/gpu/drm/amd/amdgpu/vi.c

977

return RREG32(mmCONFIG_MEMSIZE);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

109

vpe_colla_cntl = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_COLLABORATE_CNTL));

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

114

vpe_colla_cfg = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_COLLABORATE_CFG));

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

136

ret = RREG32(vpe_get_reg_offset(vpe, j, regVPEC_CNTL_6_1_1));

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

138

ret = RREG32(vpe_get_reg_offset(vpe, j, regVPEC_CNTL));

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

162

f32_cntl = RREG32(f32_offset);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

218

rb_cntl = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_CNTL));

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

250

doorbell_offset = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_DOORBELL_OFFSET));

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

254

doorbell = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_DOORBELL));

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

264

ib_cntl = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_IB_CNTL));

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

284

queue_reset = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE_RESET_REQ_6_1_1));

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

286

queue_reset = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE_RESET_REQ));

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

318

vpe_cntl = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_CNTL_6_1_1));

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

320

vpe_cntl = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_CNTL));

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

79

f32_cntl = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_F32_CNTL));

drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c

126

u32 v = RREG32(mmDOUT_SCRATCH3);

drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c

422

data = RREG32(config_regs->offset);

drivers/gpu/drm/amd/pm/legacy-dpm/kv_smc.c

101

*value = RREG32(mmSMC_IND_DATA_0);

drivers/gpu/drm/amd/pm/legacy-dpm/kv_smc.c

142

original_data = RREG32(mmSMC_IND_DATA_0);

drivers/gpu/drm/amd/pm/legacy-dpm/kv_smc.c

196

original_data = RREG32(mmSMC_IND_DATA_0);

drivers/gpu/drm/amd/pm/legacy-dpm/kv_smc.c

40

if ((RREG32(mmSMC_RESP_0) & SMC_RESP_0__SMC_RESP_MASK) != 0)

drivers/gpu/drm/amd/pm/legacy-dpm/kv_smc.c

44

tmp = RREG32(mmSMC_RESP_0) & SMC_RESP_0__SMC_RESP_MASK;

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

2212

cac_window = RREG32(mmCG_CAC_CTRL) & CG_CAC_CTRL__CAC_WINDOW_MASK;

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

2774

reg = RREG32(mmCG_CAC_CTRL) & ~CG_CAC_CTRL__CAC_WINDOW_MASK;

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

2859

data = RREG32(config_regs->offset);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

3102

mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

3103

mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

3104

burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE0_MASK) >> STATE0_SHIFT;

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

3107

mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_1);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

3108

mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_1);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

3109

burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE1_MASK) >> STATE1_SHIFT;

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

3112

mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_2);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

3113

mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_2);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

3114

burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE2_MASK) >> STATE2_SHIFT;

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

3117

mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_3);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

3118

mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_3);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

3119

burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE3_MASK) >> STATE3_SHIFT;

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

3150

mc_cg_config = RREG32(MC_CG_CONFIG) | 0x0000000F;

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

3407

return (u8) ((RREG32(BIOS_SCRATCH_4) >> 16) & 0xff);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

3724

tmp = RREG32(MC_SEQ_MISC0);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

3730

width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32;

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

3732

tmp = RREG32(mmMC_ARB_RAMCFG);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

4086

si_pi->clock_registers.cg_spll_func_cntl = RREG32(mmCG_SPLL_FUNC_CNTL);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

4087

si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(mmCG_SPLL_FUNC_CNTL_2);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

4088

si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(mmCG_SPLL_FUNC_CNTL_3);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

4089

si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(mmCG_SPLL_FUNC_CNTL_4);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

4090

si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(mmCG_SPLL_SPREAD_SPECTRUM);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

4091

si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(mmCG_SPLL_SPREAD_SPECTRUM_2);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

4092

si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

4093

si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

4094

si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

4095

si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

4096

si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

4097

si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

4098

si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

4099

si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

4100

si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

4136

if (RREG32(SMC_RESP_0) == 1)

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

4206

tmp = RREG32(mmCG_DISPLAY_GAP_CNTL) & ~(CG_DISPLAY_GAP_CNTL__DISP1_GAP_MASK | CG_DISPLAY_GAP_CNTL__DISP2_GAP_MASK);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

4219

tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

4311

u32 tmp = RREG32(mmCG_DISPLAY_GAP_CNTL);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

4789

u32 tmp = (RREG32(mmMC_ARB_RAMCFG) & MC_ARB_RAMCFG__NOOFROWS_MASK) >> MC_ARB_RAMCFG__NOOFROWS__SHIFT;

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

4796

dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

4819

dram_timing = RREG32(MC_ARB_DRAM_TIMING);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

4820

dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

4821

burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

5542

(RREG32(mmDPG_PIPE_STUTTER_CONTROL) & DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK) &&

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

5558

((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

5559

dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

5561

dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

5569

dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

5891

temp_reg = RREG32(MC_PMG_CMD_EMRS);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

5902

temp_reg = RREG32(MC_PMG_CMD_MRS);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

5926

temp_reg = RREG32(MC_PMG_CMD_MRS1);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

6063

WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

6064

WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

6065

WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

6066

WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

6067

WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

6068

WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

6069

WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

6070

WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

6071

WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

6072

WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

6073

WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

6074

WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

6075

WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

6076

WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

6462

u32 thermal_int = RREG32(mmCG_THERMAL_INT);

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

6513

tmp = (RREG32(mmCG_FDO_CTRL2) & CG_FDO_CTRL2__FDO_PWM_MODE_MASK) >> CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

6515

tmp = (RREG32(mmCG_FDO_CTRL2) & CG_FDO_CTRL2__TMIN_MASK) >> CG_FDO_CTRL2__TMIN__SHIFT;

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

6520

tmp = RREG32(mmCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TMIN_MASK;

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

6524

tmp = RREG32(mmCG_FDO_CTRL2) & ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK;

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

6545

duty100 = (RREG32(mmCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK) >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT;

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

6581

tmp = (RREG32(mmCG_MULT_THERMAL_CTRL) & CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK) >> CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT;

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

6640

duty100 = (RREG32(mmCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK) >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT;

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

6641

duty = (RREG32(mmCG_THERMAL_STATUS) & CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK) >> CG_THERMAL_STATUS__FDO_PWM_DUTY__SHIFT;

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

6671

duty100 = (RREG32(mmCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK) >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT;

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

6680

tmp = RREG32(mmCG_FDO_CTRL0) & ~CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK;

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

6722

tmp = RREG32(mmCG_FDO_CTRL2) & CG_FDO_CTRL2__FDO_PWM_MODE_MASK;

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

6741

tach_period = (RREG32(mmCG_TACH_STATUS) & CG_TACH_STATUS__TACH_PERIOD_MASK) >> CG_TACH_STATUS__TACH_PERIOD__SHIFT;

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

6770

tmp = RREG32(mmCG_TACH_CTRL) & ~CG_TACH_CTRL__TARGET_PERIOD_MASK;

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

6786

tmp = RREG32(mmCG_FDO_CTRL2) & ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK;

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

6790

tmp = RREG32(mmCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TMIN_MASK;

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

6810

tmp = RREG32(mmCG_TACH_CTRL) & ~CG_TACH_CTRL__EDGE_PER_REV_MASK;

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

6815

tmp = RREG32(mmCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK;

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

7581

(RREG32(mmTARGET_AND_CURRENT_PROFILE_INDEX) & TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_INDEX_MASK) >>

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

7934

temp = (RREG32(mmCG_MULT_THERMAL_STATUS) & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >>

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

8066

(RREG32(mmTARGET_AND_CURRENT_PROFILE_INDEX) & TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_INDEX_MASK) >>

drivers/gpu/drm/amd/pm/legacy-dpm/si_smc.c

130

RREG32(mmCB_CGTT_SCLK_CTRL);

drivers/gpu/drm/amd/pm/legacy-dpm/si_smc.c

131

RREG32(mmCB_CGTT_SCLK_CTRL);

drivers/gpu/drm/amd/pm/legacy-dpm/si_smc.c

132

RREG32(mmCB_CGTT_SCLK_CTRL);

drivers/gpu/drm/amd/pm/legacy-dpm/si_smc.c

133

RREG32(mmCB_CGTT_SCLK_CTRL);

drivers/gpu/drm/amd/pm/legacy-dpm/si_smc.c

197

tmp = RREG32(mmSMC_RESP_0);

drivers/gpu/drm/amd/pm/legacy-dpm/si_smc.c

203

tmp = RREG32(mmSMC_RESP_0);

drivers/gpu/drm/amd/pm/legacy-dpm/si_smc.c

207

__func__, msg, RREG32(mmSMC_SCRATCH0));

drivers/gpu/drm/amd/pm/legacy-dpm/si_smc.c

282

*value = RREG32(mmSMC_IND_DATA_0);

drivers/gpu/drm/amd/pm/legacy-dpm/si_smc.c

92

original_data = RREG32(mmSMC_IND_DATA_0);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/common_baco.c

34

data = RREG32(reg);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/common_baco.c

56

data = RREG32(reg);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_baco.c

44

reg = RREG32(mmCC_BIF_BX_FUSESTRAP0);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_baco.c

57

reg = RREG32(mmBACO_CNTL);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu9_baco.c

40

data = RREG32(0x12075);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_baco.c

47

if (((RREG32(0x17569) & 0x20000000) >> 29) == 0x1) {

drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c

261

reg = RREG32(cfg->resp_reg);

drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c

290

args->out_args[i] = RREG32(ctl->config.arg_regs[i]);

drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c

308

RREG32(ctl->config.msg_reg),

drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c

309

RREG32(ctl->config.resp_reg));

drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c

312

in[i] = RREG32(ctl->config.arg_regs[i]);

drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c

396

reg = RREG32(ctl->config.resp_reg);

drivers/gpu/drm/mgag200/mgag200_g200er.c

45

memctl = RREG32(MGAREG_MEMCTL);

drivers/gpu/drm/mgag200/mgag200_g200se.c

422

g200se->unique_rev_id = RREG32(0x1e24);

drivers/gpu/drm/mgag200/mgag200_mode.c

100

status = RREG32(MGAREG_STATUS);

drivers/gpu/drm/mgag200/mgag200_mode.c

105

status = RREG32(MGAREG_STATUS);

drivers/gpu/drm/mgag200/mgag200_mode.c

171

u32 opmode = RREG32(MGAREG_OPMODE);

drivers/gpu/drm/radeon/atombios_crtc.c

1667

disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);

drivers/gpu/drm/radeon/atombios_crtc.c

1672

disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);

drivers/gpu/drm/radeon/atombios_crtc.c

1675

WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));

drivers/gpu/drm/radeon/atombios_crtc.c

1676

WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));

drivers/gpu/drm/radeon/atombios_crtc.c

238

vga_control = RREG32(vga_control_regs[radeon_crtc->crtc_id]);

drivers/gpu/drm/radeon/atombios_crtc.c

402

ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);

drivers/gpu/drm/radeon/atombios_crtc.c

407

ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);

drivers/gpu/drm/radeon/atombios_crtc.c

418

ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);

drivers/gpu/drm/radeon/atombios_crtc.c

423

ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);

drivers/gpu/drm/radeon/atombios_encoders.c

1544

temp = RREG32(reg);

drivers/gpu/drm/radeon/atombios_encoders.c

1619

u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);

drivers/gpu/drm/radeon/atombios_encoders.c

2006

uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);

drivers/gpu/drm/radeon/atombios_encoders.c

2336

bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);

drivers/gpu/drm/radeon/atombios_encoders.c

2338

bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);

drivers/gpu/drm/radeon/atombios_encoders.c

2385

bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);

drivers/gpu/drm/radeon/atombios_encoders.c

54

bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);

drivers/gpu/drm/radeon/atombios_encoders.c

56

bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);

drivers/gpu/drm/radeon/atombios_encoders.c

71

bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);

drivers/gpu/drm/radeon/atombios_encoders.c

73

bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);

drivers/gpu/drm/radeon/btc_dpm.c

1314

bif = RREG32(CG_BIF_REQ_AND_RSP) & ~CG_CLIENT_REQ_MASK;

drivers/gpu/drm/radeon/btc_dpm.c

1333

bif = RREG32(CG_BIF_REQ_AND_RSP) & ~CG_CLIENT_REQ_MASK;

drivers/gpu/drm/radeon/btc_dpm.c

1417

tmp = RREG32(sequence[i]);

drivers/gpu/drm/radeon/btc_dpm.c

1714

if (((RREG32(LB_SYNC_RESET_SEL) & LB_SYNC_RESET_SEL_MASK) >> LB_SYNC_RESET_SEL_SHIFT) != 1)

drivers/gpu/drm/radeon/btc_dpm.c

1729

arb_registers->mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING);

drivers/gpu/drm/radeon/btc_dpm.c

1730

arb_registers->mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);

drivers/gpu/drm/radeon/btc_dpm.c

1731

arb_registers->mc_arb_rfsh_rate = RREG32(MC_ARB_RFSH_RATE);

drivers/gpu/drm/radeon/btc_dpm.c

1732

arb_registers->mc_arb_burst_time = RREG32(MC_ARB_BURST_TIME);

drivers/gpu/drm/radeon/btc_dpm.c

1896

tmp = RREG32(MC_PMG_CMD_EMRS);

drivers/gpu/drm/radeon/btc_dpm.c

1909

tmp = RREG32(MC_PMG_CMD_MRS);

drivers/gpu/drm/radeon/btc_dpm.c

1925

tmp = RREG32(MC_PMG_CMD_MRS1);

drivers/gpu/drm/radeon/btc_dpm.c

2000

WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));

drivers/gpu/drm/radeon/btc_dpm.c

2001

WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));

drivers/gpu/drm/radeon/btc_dpm.c

2002

WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));

drivers/gpu/drm/radeon/btc_dpm.c

2003

WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));

drivers/gpu/drm/radeon/btc_dpm.c

2004

WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));

drivers/gpu/drm/radeon/btc_dpm.c

2005

WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));

drivers/gpu/drm/radeon/btc_dpm.c

2006

WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));

drivers/gpu/drm/radeon/btc_dpm.c

2007

WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));

drivers/gpu/drm/radeon/btc_dpm.c

2008

WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));

drivers/gpu/drm/radeon/btc_dpm.c

2009

WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));

drivers/gpu/drm/radeon/btc_dpm.c

2010

WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));

drivers/gpu/drm/radeon/btc_dpm.c

2043

tmp = RREG32(MC_PMG_AUTO_CFG);

drivers/gpu/drm/radeon/btc_dpm.c

2711

(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK) >>

drivers/gpu/drm/radeon/btc_dpm.c

2736

(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK) >>

drivers/gpu/drm/radeon/btc_dpm.c

2759

(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK) >>

drivers/gpu/drm/radeon/ci_dpm.c

1626

tmp = RREG32(SMC_RESP_0);

drivers/gpu/drm/radeon/ci_dpm.c

1631

tmp = RREG32(SMC_RESP_0);

drivers/gpu/drm/radeon/ci_dpm.c

1651

*parameter = RREG32(SMC_MSG_ARG_0);

drivers/gpu/drm/radeon/ci_dpm.c

1844

pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);

drivers/gpu/drm/radeon/ci_dpm.c

1845

pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);

drivers/gpu/drm/radeon/ci_dpm.c

1846

pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);

drivers/gpu/drm/radeon/ci_dpm.c

1847

pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);

drivers/gpu/drm/radeon/ci_dpm.c

1848

pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);

drivers/gpu/drm/radeon/ci_dpm.c

1849

pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);

drivers/gpu/drm/radeon/ci_dpm.c

1850

pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);

drivers/gpu/drm/radeon/ci_dpm.c

1851

pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);

drivers/gpu/drm/radeon/ci_dpm.c

1852

pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);

drivers/gpu/drm/radeon/ci_dpm.c

1903

if (RREG32(SMC_RESP_0) == 1)

drivers/gpu/drm/radeon/ci_dpm.c

2459

tmp = RREG32(MC_SEQ_MISC0);

drivers/gpu/drm/radeon/ci_dpm.c

2489

dram_timing = RREG32(MC_ARB_DRAM_TIMING);

drivers/gpu/drm/radeon/ci_dpm.c

2490

dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);

drivers/gpu/drm/radeon/ci_dpm.c

2491

burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;

drivers/gpu/drm/radeon/ci_dpm.c

2888

(RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&

drivers/gpu/drm/radeon/ci_dpm.c

2909

((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))

drivers/gpu/drm/radeon/ci_dpm.c

2910

dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;

drivers/gpu/drm/radeon/ci_dpm.c

2912

dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;

drivers/gpu/drm/radeon/ci_dpm.c

2918

dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;

drivers/gpu/drm/radeon/ci_dpm.c

4298

temp_reg = RREG32(MC_PMG_CMD_EMRS);

drivers/gpu/drm/radeon/ci_dpm.c

4309

temp_reg = RREG32(MC_PMG_CMD_MRS);

drivers/gpu/drm/radeon/ci_dpm.c

4335

temp_reg = RREG32(MC_PMG_CMD_MRS1);

drivers/gpu/drm/radeon/ci_dpm.c

4491

tmp = RREG32(MC_SEQ_MISC0);

drivers/gpu/drm/radeon/ci_dpm.c

4565

tmp = RREG32(MC_SEQ_IO_DEBUG_DATA);

drivers/gpu/drm/radeon/ci_dpm.c

4586

WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));

drivers/gpu/drm/radeon/ci_dpm.c

4587

WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));

drivers/gpu/drm/radeon/ci_dpm.c

4588

WREG32(MC_SEQ_DLL_STBY_LP, RREG32(MC_SEQ_DLL_STBY));

drivers/gpu/drm/radeon/ci_dpm.c

4589

WREG32(MC_SEQ_G5PDX_CMD0_LP, RREG32(MC_SEQ_G5PDX_CMD0));

drivers/gpu/drm/radeon/ci_dpm.c

4590

WREG32(MC_SEQ_G5PDX_CMD1_LP, RREG32(MC_SEQ_G5PDX_CMD1));

drivers/gpu/drm/radeon/ci_dpm.c

4591

WREG32(MC_SEQ_G5PDX_CTRL_LP, RREG32(MC_SEQ_G5PDX_CTRL));

drivers/gpu/drm/radeon/ci_dpm.c

4592

WREG32(MC_SEQ_PMG_DVS_CMD_LP, RREG32(MC_SEQ_PMG_DVS_CMD));

drivers/gpu/drm/radeon/ci_dpm.c

4593

WREG32(MC_SEQ_PMG_DVS_CTL_LP, RREG32(MC_SEQ_PMG_DVS_CTL));

drivers/gpu/drm/radeon/ci_dpm.c

4594

WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));

drivers/gpu/drm/radeon/ci_dpm.c

4595

WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));

drivers/gpu/drm/radeon/ci_dpm.c

4596

WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));

drivers/gpu/drm/radeon/ci_dpm.c

4597

WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));

drivers/gpu/drm/radeon/ci_dpm.c

4598

WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));

drivers/gpu/drm/radeon/ci_dpm.c

4599

WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));

drivers/gpu/drm/radeon/ci_dpm.c

4600

WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));

drivers/gpu/drm/radeon/ci_dpm.c

4601

WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));

drivers/gpu/drm/radeon/ci_dpm.c

4602

WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));

drivers/gpu/drm/radeon/ci_dpm.c

4603

WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));

drivers/gpu/drm/radeon/ci_dpm.c

4604

WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));

drivers/gpu/drm/radeon/ci_dpm.c

4605

WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));

drivers/gpu/drm/radeon/ci_dpm.c

5042

tmp = RREG32(MC_SEQ_MISC0);

drivers/gpu/drm/radeon/ci_dpm.c

560

data = RREG32(config_regs->offset << 2);

drivers/gpu/drm/radeon/ci_smc.c

255

*value = RREG32(SMC_IND_DATA_0);

drivers/gpu/drm/radeon/ci_smc.c

88

original_data = RREG32(SMC_IND_DATA_0);

drivers/gpu/drm/radeon/cik.c

169

*val = RREG32(reg);

drivers/gpu/drm/radeon/cik.c

186

r = RREG32(CIK_DIDT_IND_DATA);

drivers/gpu/drm/radeon/cik.c

1902

running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;

drivers/gpu/drm/radeon/cik.c

1920

tmp = RREG32(MC_SEQ_MISC0);

drivers/gpu/drm/radeon/cik.c

1943

if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0)

drivers/gpu/drm/radeon/cik.c

1948

if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1)

drivers/gpu/drm/radeon/cik.c

244

(void)RREG32(PCIE_INDEX);

drivers/gpu/drm/radeon/cik.c

245

r = RREG32(PCIE_DATA);

drivers/gpu/drm/radeon/cik.c

256

(void)RREG32(PCIE_INDEX);

drivers/gpu/drm/radeon/cik.c

258

(void)RREG32(PCIE_DATA);

drivers/gpu/drm/radeon/cik.c

3077

data = RREG32(CC_RB_BACKEND_DISABLE);

drivers/gpu/drm/radeon/cik.c

3082

data |= RREG32(GC_USER_RB_BACKEND_DISABLE);

drivers/gpu/drm/radeon/cik.c

3170

u32 gb_addr_config = RREG32(GB_ADDR_CONFIG);

drivers/gpu/drm/radeon/cik.c

3264

RREG32(MC_SHARED_CHMAP);

drivers/gpu/drm/radeon/cik.c

3265

mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);

drivers/gpu/drm/radeon/cik.c

3354

tmp = RREG32(SPI_CONFIG_CNTL);

drivers/gpu/drm/radeon/cik.c

3362

tmp = RREG32(DB_DEBUG2) & ~0xf00fffff;

drivers/gpu/drm/radeon/cik.c

3366

tmp = RREG32(DB_DEBUG3) & ~0x0002021c;

drivers/gpu/drm/radeon/cik.c

3370

tmp = RREG32(CB_HW_CONTROL) & ~0x00010000;

drivers/gpu/drm/radeon/cik.c

3396

tmp = RREG32(HDP_MISC_CNTL);

drivers/gpu/drm/radeon/cik.c

3400

hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);

drivers/gpu/drm/radeon/cik.c

3470

tmp = RREG32(scratch);

drivers/gpu/drm/radeon/cik.c

3815

tmp = RREG32(scratch);

drivers/gpu/drm/radeon/cik.c

4121

rptr = RREG32(CP_RB0_RPTR);

drivers/gpu/drm/radeon/cik.c

4129

return RREG32(CP_RB0_WPTR);

drivers/gpu/drm/radeon/cik.c

4136

(void)RREG32(CP_RB0_WPTR);

drivers/gpu/drm/radeon/cik.c

4149

rptr = RREG32(CP_HQD_PQ_RPTR);

drivers/gpu/drm/radeon/cik.c

4168

wptr = RREG32(CP_HQD_PQ_WPTR);

drivers/gpu/drm/radeon/cik.c

4191

tmp = RREG32(CP_PQ_WPTR_POLL_CNTL);

drivers/gpu/drm/radeon/cik.c

4195

if (RREG32(CP_HQD_ACTIVE) & 1) {

drivers/gpu/drm/radeon/cik.c

4198

if (!(RREG32(CP_HQD_ACTIVE) & 1))

drivers/gpu/drm/radeon/cik.c

4525

tmp = RREG32(CP_CPF_DEBUG);

drivers/gpu/drm/radeon/cik.c

4547

tmp = RREG32(CP_HPD_EOP_CONTROL);

drivers/gpu/drm/radeon/cik.c

4610

tmp = RREG32(CP_PQ_WPTR_POLL_CNTL);

drivers/gpu/drm/radeon/cik.c

4616

RREG32(CP_HQD_PQ_DOORBELL_CONTROL);

drivers/gpu/drm/radeon/cik.c

4628

if (RREG32(CP_HQD_ACTIVE) & 1) {

drivers/gpu/drm/radeon/cik.c

4631

if (!(RREG32(CP_HQD_ACTIVE) & 1))

drivers/gpu/drm/radeon/cik.c

4646

mqd->queue_state.cp_mqd_control = RREG32(CP_MQD_CONTROL);

drivers/gpu/drm/radeon/cik.c

4658

mqd->queue_state.cp_hqd_pq_control = RREG32(CP_HQD_PQ_CONTROL);

drivers/gpu/drm/radeon/cik.c

4702

RREG32(CP_HQD_PQ_DOORBELL_CONTROL);

drivers/gpu/drm/radeon/cik.c

4720

mqd->queue_state.cp_hqd_pq_rptr = RREG32(CP_HQD_PQ_RPTR);

drivers/gpu/drm/radeon/cik.c

4796

RREG32(GRBM_STATUS));

drivers/gpu/drm/radeon/cik.c

4798

RREG32(GRBM_STATUS2));

drivers/gpu/drm/radeon/cik.c

4800

RREG32(GRBM_STATUS_SE0));

drivers/gpu/drm/radeon/cik.c

4802

RREG32(GRBM_STATUS_SE1));

drivers/gpu/drm/radeon/cik.c

4804

RREG32(GRBM_STATUS_SE2));

drivers/gpu/drm/radeon/cik.c

4806

RREG32(GRBM_STATUS_SE3));

drivers/gpu/drm/radeon/cik.c

4808

RREG32(SRBM_STATUS));

drivers/gpu/drm/radeon/cik.c

4810

RREG32(SRBM_STATUS2));

drivers/gpu/drm/radeon/cik.c

4812

RREG32(SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET));

drivers/gpu/drm/radeon/cik.c

4814

RREG32(SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET));

drivers/gpu/drm/radeon/cik.c

4815

dev_info(rdev->dev, " CP_STAT = 0x%08x\n", RREG32(CP_STAT));

drivers/gpu/drm/radeon/cik.c

4817

RREG32(CP_STALLED_STAT1));

drivers/gpu/drm/radeon/cik.c

4819

RREG32(CP_STALLED_STAT2));

drivers/gpu/drm/radeon/cik.c

4821

RREG32(CP_STALLED_STAT3));

drivers/gpu/drm/radeon/cik.c

4823

RREG32(CP_CPF_BUSY_STAT));

drivers/gpu/drm/radeon/cik.c

4825

RREG32(CP_CPF_STALLED_STAT1));

drivers/gpu/drm/radeon/cik.c

4826

dev_info(rdev->dev, " CP_CPF_STATUS = 0x%08x\n", RREG32(CP_CPF_STATUS));

drivers/gpu/drm/radeon/cik.c

4827

dev_info(rdev->dev, " CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(CP_CPC_BUSY_STAT));

drivers/gpu/drm/radeon/cik.c

4829

RREG32(CP_CPC_STALLED_STAT1));

drivers/gpu/drm/radeon/cik.c

4830

dev_info(rdev->dev, " CP_CPC_STATUS = 0x%08x\n", RREG32(CP_CPC_STATUS));

drivers/gpu/drm/radeon/cik.c

4848

tmp = RREG32(GRBM_STATUS);

drivers/gpu/drm/radeon/cik.c

4861

tmp = RREG32(GRBM_STATUS2);

drivers/gpu/drm/radeon/cik.c

4866

tmp = RREG32(SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET);

drivers/gpu/drm/radeon/cik.c

4871

tmp = RREG32(SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET);

drivers/gpu/drm/radeon/cik.c

4876

tmp = RREG32(SRBM_STATUS2);

drivers/gpu/drm/radeon/cik.c

4884

tmp = RREG32(SRBM_STATUS);

drivers/gpu/drm/radeon/cik.c

4935

RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR));

drivers/gpu/drm/radeon/cik.c

4937

RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));

drivers/gpu/drm/radeon/cik.c

4954

tmp = RREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET);

drivers/gpu/drm/radeon/cik.c

4960

tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET);

drivers/gpu/drm/radeon/cik.c

5009

tmp = RREG32(GRBM_SOFT_RESET);

drivers/gpu/drm/radeon/cik.c

5013

tmp = RREG32(GRBM_SOFT_RESET);

drivers/gpu/drm/radeon/cik.c

5019

tmp = RREG32(GRBM_SOFT_RESET);

drivers/gpu/drm/radeon/cik.c

5023

tmp = RREG32(SRBM_SOFT_RESET);

drivers/gpu/drm/radeon/cik.c

5027

tmp = RREG32(SRBM_SOFT_RESET);

drivers/gpu/drm/radeon/cik.c

5033

tmp = RREG32(SRBM_SOFT_RESET);

drivers/gpu/drm/radeon/cik.c

5054

save->gmcon_reng_execute = RREG32(GMCON_RENG_EXECUTE);

drivers/gpu/drm/radeon/cik.c

5055

save->gmcon_misc = RREG32(GMCON_MISC);

drivers/gpu/drm/radeon/cik.c

5056

save->gmcon_misc3 = RREG32(GMCON_MISC3);

drivers/gpu/drm/radeon/cik.c

5157

tmp = RREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET);

drivers/gpu/drm/radeon/cik.c

5161

tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET);

drivers/gpu/drm/radeon/cik.c

5189

if (RREG32(CONFIG_MEMSIZE) != 0xffffffff)

drivers/gpu/drm/radeon/cik.c

5335

tmp = RREG32(MC_ARB_RAMCFG);

drivers/gpu/drm/radeon/cik.c

5341

tmp = RREG32(MC_SHARED_CHMAP);

drivers/gpu/drm/radeon/cik.c

5377

rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;

drivers/gpu/drm/radeon/cik.c

5378

rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;

drivers/gpu/drm/radeon/cik.c

5496

u32 tmp = RREG32(CHUB_CONTROL);

drivers/gpu/drm/radeon/cik.c

5546

rdev->vm_manager.saved_table_addr[i] = RREG32(reg);

drivers/gpu/drm/radeon/cik.c

5621

u64 tmp = RREG32(MC_VM_FB_OFFSET);

drivers/gpu/drm/radeon/cik.c

5760

u32 tmp = RREG32(CP_INT_CNTL_RING0);

drivers/gpu/drm/radeon/cik.c

5773

tmp = RREG32(RLC_LB_CNTL);

drivers/gpu/drm/radeon/cik.c

5790

if (RREG32(RLC_SERDES_CU_MASTER_BUSY) == 0)

drivers/gpu/drm/radeon/cik.c

5800

if ((RREG32(RLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)

drivers/gpu/drm/radeon/cik.c

5810

tmp = RREG32(RLC_CNTL);

drivers/gpu/drm/radeon/cik.c

5819

orig = data = RREG32(RLC_CNTL);

drivers/gpu/drm/radeon/cik.c

5828

if ((RREG32(RLC_GPM_STAT) & RLC_GPM_BUSY) == 0)

drivers/gpu/drm/radeon/cik.c

5848

if ((RREG32(RLC_GPM_STAT) & mask) == mask)

drivers/gpu/drm/radeon/cik.c

5854

if ((RREG32(RLC_GPR_REG2) & REQ) == 0)

drivers/gpu/drm/radeon/cik.c

5919

tmp = RREG32(RLC_CGCG_CGLS_CTRL) & 0xfffffffc;

drivers/gpu/drm/radeon/cik.c

5994

orig = data = RREG32(RLC_CGCG_CGLS_CTRL);

drivers/gpu/drm/radeon/cik.c

6013

RREG32(CB_CGTT_SCLK_CTRL);

drivers/gpu/drm/radeon/cik.c

6014

RREG32(CB_CGTT_SCLK_CTRL);

drivers/gpu/drm/radeon/cik.c

6015

RREG32(CB_CGTT_SCLK_CTRL);

drivers/gpu/drm/radeon/cik.c

6016

RREG32(CB_CGTT_SCLK_CTRL);

drivers/gpu/drm/radeon/cik.c

6033

orig = data = RREG32(CP_MEM_SLP_CNTL);

drivers/gpu/drm/radeon/cik.c

6040

orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/radeon/cik.c

6057

orig = data = RREG32(CGTS_SM_CTRL_REG);

drivers/gpu/drm/radeon/cik.c

6072

orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/radeon/cik.c

6077

data = RREG32(RLC_MEM_SLP_CNTL);

drivers/gpu/drm/radeon/cik.c

6083

data = RREG32(CP_MEM_SLP_CNTL);

drivers/gpu/drm/radeon/cik.c

6089

orig = data = RREG32(CGTS_SM_CTRL_REG);

drivers/gpu/drm/radeon/cik.c

6126

orig = data = RREG32(mc_cg_registers[i]);

drivers/gpu/drm/radeon/cik.c

6143

orig = data = RREG32(mc_cg_registers[i]);

drivers/gpu/drm/radeon/cik.c

6162

orig = data = RREG32(SDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET);

drivers/gpu/drm/radeon/cik.c

6167

orig = data = RREG32(SDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET);

drivers/gpu/drm/radeon/cik.c

6180

orig = data = RREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);

drivers/gpu/drm/radeon/cik.c

6185

orig = data = RREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);

drivers/gpu/drm/radeon/cik.c

6190

orig = data = RREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);

drivers/gpu/drm/radeon/cik.c

6195

orig = data = RREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);

drivers/gpu/drm/radeon/cik.c

6212

orig = data = RREG32(UVD_CGC_CTRL);

drivers/gpu/drm/radeon/cik.c

6221

orig = data = RREG32(UVD_CGC_CTRL);

drivers/gpu/drm/radeon/cik.c

6251

orig = data = RREG32(HDP_HOST_PATH_CNTL);

drivers/gpu/drm/radeon/cik.c

6267

orig = data = RREG32(HDP_MEM_POWER_LS);

drivers/gpu/drm/radeon/cik.c

6357

orig = data = RREG32(RLC_PG_CNTL);

drivers/gpu/drm/radeon/cik.c

6371

orig = data = RREG32(RLC_PG_CNTL);

drivers/gpu/drm/radeon/cik.c

6384

orig = data = RREG32(RLC_PG_CNTL);

drivers/gpu/drm/radeon/cik.c

6397

orig = data = RREG32(RLC_PG_CNTL);

drivers/gpu/drm/radeon/cik.c

6500

orig = data = RREG32(RLC_PG_CNTL);

drivers/gpu/drm/radeon/cik.c

6505

orig = data = RREG32(RLC_AUTO_PG_CTRL);

drivers/gpu/drm/radeon/cik.c

6510

orig = data = RREG32(RLC_PG_CNTL);

drivers/gpu/drm/radeon/cik.c

6515

orig = data = RREG32(RLC_AUTO_PG_CTRL);

drivers/gpu/drm/radeon/cik.c

6520

data = RREG32(DB_RENDER_CONTROL);

drivers/gpu/drm/radeon/cik.c

6530

tmp = RREG32(CC_GC_SHADER_ARRAY_CONFIG);

drivers/gpu/drm/radeon/cik.c

6531

tmp1 = RREG32(GC_USER_SHADER_ARRAY_CONFIG);

drivers/gpu/drm/radeon/cik.c

6574

tmp = RREG32(RLC_MAX_PG_CU);

drivers/gpu/drm/radeon/cik.c

6585

orig = data = RREG32(RLC_PG_CNTL);

drivers/gpu/drm/radeon/cik.c

6599

orig = data = RREG32(RLC_PG_CNTL);

drivers/gpu/drm/radeon/cik.c

6632

orig = data = RREG32(RLC_PG_CNTL);

drivers/gpu/drm/radeon/cik.c

6640

data = RREG32(CP_RB_WPTR_POLL_CNTL);

drivers/gpu/drm/radeon/cik.c

6648

data = RREG32(RLC_PG_DELAY_2);

drivers/gpu/drm/radeon/cik.c

6653

data = RREG32(RLC_AUTO_PG_CTRL);

drivers/gpu/drm/radeon/cik.c

6814

u32 ih_cntl = RREG32(IH_CNTL);

drivers/gpu/drm/radeon/cik.c

6815

u32 ih_rb_cntl = RREG32(IH_RB_CNTL);

drivers/gpu/drm/radeon/cik.c

6833

u32 ih_rb_cntl = RREG32(IH_RB_CNTL);

drivers/gpu/drm/radeon/cik.c

6834

u32 ih_cntl = RREG32(IH_CNTL);

drivers/gpu/drm/radeon/cik.c

6859

tmp = RREG32(CP_INT_CNTL_RING0) &

drivers/gpu/drm/radeon/cik.c

6863

tmp = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;

drivers/gpu/drm/radeon/cik.c

6865

tmp = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;

drivers/gpu/drm/radeon/cik.c

6909

tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;

drivers/gpu/drm/radeon/cik.c

6911

tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;

drivers/gpu/drm/radeon/cik.c

6913

tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;

drivers/gpu/drm/radeon/cik.c

6915

tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;

drivers/gpu/drm/radeon/cik.c

6917

tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;

drivers/gpu/drm/radeon/cik.c

6919

tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;

drivers/gpu/drm/radeon/cik.c

6959

interrupt_cntl = RREG32(INTERRUPT_CNTL);

drivers/gpu/drm/radeon/cik.c

7037

cp_int_cntl = RREG32(CP_INT_CNTL_RING0) &

drivers/gpu/drm/radeon/cik.c

7041

hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);

drivers/gpu/drm/radeon/cik.c

7042

hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);

drivers/gpu/drm/radeon/cik.c

7043

hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);

drivers/gpu/drm/radeon/cik.c

7044

hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);

drivers/gpu/drm/radeon/cik.c

7045

hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);

drivers/gpu/drm/radeon/cik.c

7046

hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);

drivers/gpu/drm/radeon/cik.c

7048

dma_cntl = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;

drivers/gpu/drm/radeon/cik.c

7049

dma_cntl1 = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;

drivers/gpu/drm/radeon/cik.c

7051

cp_m1p0 = RREG32(CP_ME1_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;

drivers/gpu/drm/radeon/cik.c

7052

cp_m1p1 = RREG32(CP_ME1_PIPE1_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;

drivers/gpu/drm/radeon/cik.c

7053

cp_m1p2 = RREG32(CP_ME1_PIPE2_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;

drivers/gpu/drm/radeon/cik.c

7054

cp_m1p3 = RREG32(CP_ME1_PIPE3_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;

drivers/gpu/drm/radeon/cik.c

7055

cp_m2p0 = RREG32(CP_ME2_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;

drivers/gpu/drm/radeon/cik.c

7056

cp_m2p1 = RREG32(CP_ME2_PIPE1_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;

drivers/gpu/drm/radeon/cik.c

7057

cp_m2p2 = RREG32(CP_ME2_PIPE2_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;

drivers/gpu/drm/radeon/cik.c

7058

cp_m2p3 = RREG32(CP_ME2_PIPE3_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;

drivers/gpu/drm/radeon/cik.c

7271

RREG32(SRBM_STATUS);

drivers/gpu/drm/radeon/cik.c

7289

rdev->irq.stat_regs.cik.disp_int = RREG32(DISP_INTERRUPT_STATUS);

drivers/gpu/drm/radeon/cik.c

7290

rdev->irq.stat_regs.cik.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);

drivers/gpu/drm/radeon/cik.c

7291

rdev->irq.stat_regs.cik.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);

drivers/gpu/drm/radeon/cik.c

7292

rdev->irq.stat_regs.cik.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);

drivers/gpu/drm/radeon/cik.c

7293

rdev->irq.stat_regs.cik.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);

drivers/gpu/drm/radeon/cik.c

7294

rdev->irq.stat_regs.cik.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);

drivers/gpu/drm/radeon/cik.c

7295

rdev->irq.stat_regs.cik.disp_int_cont6 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE6);

drivers/gpu/drm/radeon/cik.c

7297

rdev->irq.stat_regs.cik.d1grph_int = RREG32(GRPH_INT_STATUS +

drivers/gpu/drm/radeon/cik.c

7299

rdev->irq.stat_regs.cik.d2grph_int = RREG32(GRPH_INT_STATUS +

drivers/gpu/drm/radeon/cik.c

7302

rdev->irq.stat_regs.cik.d3grph_int = RREG32(GRPH_INT_STATUS +

drivers/gpu/drm/radeon/cik.c

7304

rdev->irq.stat_regs.cik.d4grph_int = RREG32(GRPH_INT_STATUS +

drivers/gpu/drm/radeon/cik.c

7308

rdev->irq.stat_regs.cik.d5grph_int = RREG32(GRPH_INT_STATUS +

drivers/gpu/drm/radeon/cik.c

7310

rdev->irq.stat_regs.cik.d6grph_int = RREG32(GRPH_INT_STATUS +

drivers/gpu/drm/radeon/cik.c

7364

tmp = RREG32(DC_HPD1_INT_CONTROL);

drivers/gpu/drm/radeon/cik.c

7369

tmp = RREG32(DC_HPD2_INT_CONTROL);

drivers/gpu/drm/radeon/cik.c

7374

tmp = RREG32(DC_HPD3_INT_CONTROL);

drivers/gpu/drm/radeon/cik.c

7379

tmp = RREG32(DC_HPD4_INT_CONTROL);

drivers/gpu/drm/radeon/cik.c

7384

tmp = RREG32(DC_HPD5_INT_CONTROL);

drivers/gpu/drm/radeon/cik.c

7389

tmp = RREG32(DC_HPD6_INT_CONTROL);

drivers/gpu/drm/radeon/cik.c

7394

tmp = RREG32(DC_HPD1_INT_CONTROL);

drivers/gpu/drm/radeon/cik.c

7399

tmp = RREG32(DC_HPD2_INT_CONTROL);

drivers/gpu/drm/radeon/cik.c

7404

tmp = RREG32(DC_HPD3_INT_CONTROL);

drivers/gpu/drm/radeon/cik.c

7409

tmp = RREG32(DC_HPD4_INT_CONTROL);

drivers/gpu/drm/radeon/cik.c

7414

tmp = RREG32(DC_HPD5_INT_CONTROL);

drivers/gpu/drm/radeon/cik.c

7419

tmp = RREG32(DC_HPD6_INT_CONTROL);

drivers/gpu/drm/radeon/cik.c

7488

wptr = RREG32(IH_RB_WPTR);

drivers/gpu/drm/radeon/cik.c

7499

tmp = RREG32(IH_RB_CNTL);

drivers/gpu/drm/radeon/cik.c

7887

DRM_ERROR("SRBM_READ_ERROR: 0x%x\n", RREG32(SRBM_READ_ERROR));

drivers/gpu/drm/radeon/cik.c

7896

addr = RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR);

drivers/gpu/drm/radeon/cik.c

7897

status = RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS);

drivers/gpu/drm/radeon/cik.c

7898

mc_client = RREG32(VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);

drivers/gpu/drm/radeon/cik.c

8858

if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &

drivers/gpu/drm/radeon/cik.c

8891

u32 tmp = RREG32(MC_SHARED_CHMAP);

drivers/gpu/drm/radeon/cik.c

9350

wm_mask = RREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset);

drivers/gpu/drm/radeon/cik.c

9359

tmp = RREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset);

drivers/gpu/drm/radeon/cik.c

9419

clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |

drivers/gpu/drm/radeon/cik.c

9420

((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);

drivers/gpu/drm/radeon/cik_sdma.c

121

(void)RREG32(reg);

drivers/gpu/drm/radeon/cik_sdma.c

263

rb_cntl = RREG32(SDMA0_GFX_RB_CNTL + reg_offset);

drivers/gpu/drm/radeon/cik_sdma.c

277

(void)RREG32(SRBM_SOFT_RESET);

drivers/gpu/drm/radeon/cik_sdma.c

280

(void)RREG32(SRBM_SOFT_RESET);

drivers/gpu/drm/radeon/cik_sdma.c

313

value = RREG32(SDMA0_CNTL + reg_offset);

drivers/gpu/drm/radeon/cik_sdma.c

345

me_cntl = RREG32(SDMA0_ME_CNTL + reg_offset);

drivers/gpu/drm/radeon/cik_sdma.c

75

rptr = RREG32(reg);

drivers/gpu/drm/radeon/cik_sdma.c

99

return (RREG32(reg) & 0x3fffc) >> 2;

drivers/gpu/drm/radeon/cypress_dpm.c

1041

RREG32(eg_pi->mc_reg_table.mc_reg_address[i].s1 << 2);

drivers/gpu/drm/radeon/cypress_dpm.c

106

RREG32(GB_ADDR_CONFIG);

drivers/gpu/drm/radeon/cypress_dpm.c

1112

if (((RREG32(MC_SEQ_CG) & CG_SEQ_RESP_MASK) >> CG_SEQ_RESP_SHIFT) == value)

drivers/gpu/drm/radeon/cypress_dpm.c

1127

if (RREG32(MC_SEQ_STATUS_M) & PMG_PWRSTATE)

drivers/gpu/drm/radeon/cypress_dpm.c

1156

if (RREG32(MC_SEQ_STATUS_M) & PMG_PWRSTATE)

drivers/gpu/drm/radeon/cypress_dpm.c

1175

value = RREG32(eg_pi->mc_reg_table.mc_reg_address[i].s1 << 2);

drivers/gpu/drm/radeon/cypress_dpm.c

1214

if (!(RREG32(MC_SEQ_STATUS_M) & PMG_PWRSTATE))

drivers/gpu/drm/radeon/cypress_dpm.c

147

RREG32(GB_ADDR_CONFIG);

drivers/gpu/drm/radeon/cypress_dpm.c

1579

u32 tmp = RREG32(GENERAL_PWRMGT);

drivers/gpu/drm/radeon/cypress_dpm.c

1733

u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);

drivers/gpu/drm/radeon/cypress_dpm.c

1750

tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);

drivers/gpu/drm/radeon/cypress_dpm.c

1763

tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);

drivers/gpu/drm/radeon/cypress_dpm.c

505

mc_seq_misc7 = RREG32(MC_SEQ_MISC7);

drivers/gpu/drm/radeon/cypress_dpm.c

59

bif = RREG32(CG_BIF_REQ_AND_RSP) & ~CG_CLIENT_REQ_MASK;

drivers/gpu/drm/radeon/cypress_dpm.c

720

((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))

drivers/gpu/drm/radeon/cypress_dpm.c

721

dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;

drivers/gpu/drm/radeon/cypress_dpm.c

723

dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;

drivers/gpu/drm/radeon/cypress_dpm.c

931

u32 mc_arb_burst_time = RREG32(MC_ARB_BURST_TIME);

drivers/gpu/drm/radeon/dce3_1_afmt.c

155

dto_cntl = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;

drivers/gpu/drm/radeon/dce3_1_afmt.c

162

dto_cntl = RREG32(DCCG_AUDIO_DTO1_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;

drivers/gpu/drm/radeon/dce6_afmt.c

306

unsigned int div = (RREG32(DENTIST_DISPCLK_CNTL) &

drivers/gpu/drm/radeon/dce6_afmt.c

42

r = RREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset);

drivers/gpu/drm/radeon/evergreen.c

108

r = RREG32(EVERGREEN_PIF_PHY1_DATA);

drivers/gpu/drm/radeon/evergreen.c

1104

*val = RREG32(reg);

drivers/gpu/drm/radeon/evergreen.c

1156

if (RREG32(status_reg) & DCLK_STATUS)

drivers/gpu/drm/radeon/evergreen.c

1169

u32 cg_scratch = RREG32(CG_SCRATCH1);

drivers/gpu/drm/radeon/evergreen.c

1350

if (RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK)

drivers/gpu/drm/radeon/evergreen.c

1360

pos1 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]);

drivers/gpu/drm/radeon/evergreen.c

1361

pos2 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]);

drivers/gpu/drm/radeon/evergreen.c

1384

if (!(RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[crtc]) & EVERGREEN_CRTC_MASTER_EN))

drivers/gpu/drm/radeon/evergreen.c

1434

RREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset);

drivers/gpu/drm/radeon/evergreen.c

1450

return !!(RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) &

drivers/gpu/drm/radeon/evergreen.c

1461

toffset = (RREG32(CG_THERMAL_CTRL) & TOFFSET_MASK) >>

drivers/gpu/drm/radeon/evergreen.c

1463

temp = (RREG32(CG_TS0_STATUS) & TS0_ADC_DOUT_MASK) >>

drivers/gpu/drm/radeon/evergreen.c

1474

temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>

drivers/gpu/drm/radeon/evergreen.c

1495

u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff;

drivers/gpu/drm/radeon/evergreen.c

1686

tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);

drivers/gpu/drm/radeon/evergreen.c

1711

tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);

drivers/gpu/drm/radeon/evergreen.c

1732

return !!(RREG32(DC_HPDx_INT_STATUS_REG(hpd)) & DC_HPDx_SENSE);

drivers/gpu/drm/radeon/evergreen.c

1877

if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &

drivers/gpu/drm/radeon/evergreen.c

1920

u32 tmp = RREG32(MC_SHARED_CHMAP);

drivers/gpu/drm/radeon/evergreen.c

2289

arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);

drivers/gpu/drm/radeon/evergreen.c

2298

tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);

drivers/gpu/drm/radeon/evergreen.c

2368

tmp = RREG32(SRBM_STATUS) & 0x1F00;

drivers/gpu/drm/radeon/evergreen.c

2389

tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);

drivers/gpu/drm/radeon/evergreen.c

2582

dig_fe = RREG32(NI_DIG_FE_CNTL + ni_dig_offsets[i]);

drivers/gpu/drm/radeon/evergreen.c

2596

dig_be = RREG32(NI_DIG_BE_CNTL + ni_dig_offsets[i]);

drivers/gpu/drm/radeon/evergreen.c

2603

dig_en_be = RREG32(NI_DIG_BE_EN_CNTL +

drivers/gpu/drm/radeon/evergreen.c

2605

uniphy_pll = RREG32(NI_DCIO_UNIPHY0_PLL_CONTROL1 +

drivers/gpu/drm/radeon/evergreen.c

2639

stream_ctrl = RREG32(EVERGREEN_DP_VID_STREAM_CNTL +

drivers/gpu/drm/radeon/evergreen.c

2650

stream_ctrl = RREG32(EVERGREEN_DP_VID_STREAM_CNTL +

drivers/gpu/drm/radeon/evergreen.c

2655

stream_ctrl = RREG32(EVERGREEN_DP_VID_STREAM_CNTL +

drivers/gpu/drm/radeon/evergreen.c

2661

fifo_ctrl = RREG32(EVERGREEN_DP_STEER_FIFO + evergreen_dp_offsets[dig_fe]);

drivers/gpu/drm/radeon/evergreen.c

2674

save->vga_render_control = RREG32(VGA_RENDER_CONTROL);

drivers/gpu/drm/radeon/evergreen.c

2675

save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);

drivers/gpu/drm/radeon/evergreen.c

2682

crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN;

drivers/gpu/drm/radeon/evergreen.c

2686

tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);

drivers/gpu/drm/radeon/evergreen.c

2695

tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);

drivers/gpu/drm/radeon/evergreen.c

2724

tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);

drivers/gpu/drm/radeon/evergreen.c

2737

blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);

drivers/gpu/drm/radeon/evergreen.c

2751

tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);

drivers/gpu/drm/radeon/evergreen.c

2756

tmp = RREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i]);

drivers/gpu/drm/radeon/evergreen.c

2790

tmp = RREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i]);

drivers/gpu/drm/radeon/evergreen.c

2795

tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);

drivers/gpu/drm/radeon/evergreen.c

2800

tmp = RREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i]);

drivers/gpu/drm/radeon/evergreen.c

2806

tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);

drivers/gpu/drm/radeon/evergreen.c

2815

tmp = RREG32(MC_SHARED_BLACKOUT_CNTL);

drivers/gpu/drm/radeon/evergreen.c

2824

tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);

drivers/gpu/drm/radeon/evergreen.c

2830

tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);

drivers/gpu/drm/radeon/evergreen.c

2901

tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF;

drivers/gpu/drm/radeon/evergreen.c

3081

RREG32(GRBM_SOFT_RESET);

drivers/gpu/drm/radeon/evergreen.c

3084

RREG32(GRBM_SOFT_RESET);

drivers/gpu/drm/radeon/evergreen.c

3404

RREG32(MC_SHARED_CHMAP);

drivers/gpu/drm/radeon/evergreen.c

3408

mc_arb_ramcfg = RREG32(FUS_MC_ARB_RAMCFG);

drivers/gpu/drm/radeon/evergreen.c

3410

mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);

drivers/gpu/drm/radeon/evergreen.c

3471

rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16;

drivers/gpu/drm/radeon/evergreen.c

3492

simd_disable_bitmap = (RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffff0000) >> 16;

drivers/gpu/drm/radeon/evergreen.c

3543

sx_debug_1 = RREG32(SX_DEBUG_1);

drivers/gpu/drm/radeon/evergreen.c

3548

smx_dc_ctl0 = RREG32(SMX_DC_CTL0);

drivers/gpu/drm/radeon/evergreen.c

3574

sq_config = RREG32(SQ_CONFIG);

drivers/gpu/drm/radeon/evergreen.c

3599

sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT);

drivers/gpu/drm/radeon/evergreen.c

3701

tmp = RREG32(HDP_MISC_CNTL);

drivers/gpu/drm/radeon/evergreen.c

3705

hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);

drivers/gpu/drm/radeon/evergreen.c

3724

tmp = RREG32(FUS_MC_ARB_RAMCFG);

drivers/gpu/drm/radeon/evergreen.c

3726

tmp = RREG32(MC_ARB_RAMCFG);

drivers/gpu/drm/radeon/evergreen.c

3734

tmp = RREG32(MC_SHARED_CHMAP);

drivers/gpu/drm/radeon/evergreen.c

3759

rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);

drivers/gpu/drm/radeon/evergreen.c

3760

rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);

drivers/gpu/drm/radeon/evergreen.c

3763

rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;

drivers/gpu/drm/radeon/evergreen.c

3764

rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;

drivers/gpu/drm/radeon/evergreen.c

3776

RREG32(GRBM_STATUS));

drivers/gpu/drm/radeon/evergreen.c

3778

RREG32(GRBM_STATUS_SE0));

drivers/gpu/drm/radeon/evergreen.c

3780

RREG32(GRBM_STATUS_SE1));

drivers/gpu/drm/radeon/evergreen.c

3782

RREG32(SRBM_STATUS));

drivers/gpu/drm/radeon/evergreen.c

3784

RREG32(SRBM_STATUS2));

drivers/gpu/drm/radeon/evergreen.c

3786

RREG32(CP_STALLED_STAT1));

drivers/gpu/drm/radeon/evergreen.c

3788

RREG32(CP_STALLED_STAT2));

drivers/gpu/drm/radeon/evergreen.c

3790

RREG32(CP_BUSY_STAT));

drivers/gpu/drm/radeon/evergreen.c

3792

RREG32(CP_STAT));

drivers/gpu/drm/radeon/evergreen.c

3794

RREG32(DMA_STATUS_REG));

drivers/gpu/drm/radeon/evergreen.c

3797

RREG32(DMA_STATUS_REG + 0x800));

drivers/gpu/drm/radeon/evergreen.c

3808

if (RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN) {

drivers/gpu/drm/radeon/evergreen.c

3809

crtc_status[i] = RREG32(EVERGREEN_CRTC_STATUS_HV_COUNT + crtc_offsets[i]);

drivers/gpu/drm/radeon/evergreen.c

3817

tmp = RREG32(EVERGREEN_CRTC_STATUS_HV_COUNT + crtc_offsets[i]);

drivers/gpu/drm/radeon/evergreen.c

3837

tmp = RREG32(GRBM_STATUS);

drivers/gpu/drm/radeon/evergreen.c

3853

tmp = RREG32(DMA_STATUS_REG);

drivers/gpu/drm/radeon/evergreen.c

3858

tmp = RREG32(SRBM_STATUS2);

drivers/gpu/drm/radeon/evergreen.c

3863

tmp = RREG32(SRBM_STATUS);

drivers/gpu/drm/radeon/evergreen.c

3887

tmp = RREG32(VM_L2_STATUS);

drivers/gpu/drm/radeon/evergreen.c

3918

tmp = RREG32(DMA_RB_CNTL);

drivers/gpu/drm/radeon/evergreen.c

3978

tmp = RREG32(GRBM_SOFT_RESET);

drivers/gpu/drm/radeon/evergreen.c

3982

tmp = RREG32(GRBM_SOFT_RESET);

drivers/gpu/drm/radeon/evergreen.c

3988

tmp = RREG32(GRBM_SOFT_RESET);

drivers/gpu/drm/radeon/evergreen.c

3992

tmp = RREG32(SRBM_SOFT_RESET);

drivers/gpu/drm/radeon/evergreen.c

3996

tmp = RREG32(SRBM_SOFT_RESET);

drivers/gpu/drm/radeon/evergreen.c

4002

tmp = RREG32(SRBM_SOFT_RESET);

drivers/gpu/drm/radeon/evergreen.c

4027

tmp = RREG32(DMA_RB_CNTL);

drivers/gpu/drm/radeon/evergreen.c

4050

if (RREG32(CONFIG_MEMSIZE) != 0xffffffff)

drivers/gpu/drm/radeon/evergreen.c

4403

u32 tmp = (RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffff0000) >> 16;

drivers/gpu/drm/radeon/evergreen.c

4460

return RREG32(CRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);

drivers/gpu/drm/radeon/evergreen.c

4473

tmp = RREG32(CAYMAN_DMA1_CNTL) & ~TRAP_ENABLE;

drivers/gpu/drm/radeon/evergreen.c

4477

tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE;

drivers/gpu/drm/radeon/evergreen.c

4519

thermal_int = RREG32(TN_CG_THERMAL_INT_CTRL) &

drivers/gpu/drm/radeon/evergreen.c

4522

thermal_int = RREG32(CG_THERMAL_INT) &

drivers/gpu/drm/radeon/evergreen.c

4525

dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE;

drivers/gpu/drm/radeon/evergreen.c

4555

dma_cntl1 = RREG32(CAYMAN_DMA1_CNTL) & ~TRAP_ENABLE;

drivers/gpu/drm/radeon/evergreen.c

4612

RREG32(SRBM_STATUS);

drivers/gpu/drm/radeon/evergreen.c

4626

disp_int[i] = RREG32(evergreen_disp_int_status[i]);

drivers/gpu/drm/radeon/evergreen.c

4627

afmt_status[i] = RREG32(AFMT_STATUS + crtc_offsets[i]);

drivers/gpu/drm/radeon/evergreen.c

4629

grph_int[i] = RREG32(GRPH_INT_STATUS + crtc_offsets[i]);

drivers/gpu/drm/radeon/evergreen.c

4689

wptr = RREG32(IH_RB_WPTR);

drivers/gpu/drm/radeon/evergreen.c

4700

tmp = RREG32(IH_RB_CNTL);

drivers/gpu/drm/radeon/evergreen.c

4843

drm_err(ddev, "SRBM_READ_ERROR: 0x%x\n", RREG32(SRBM_READ_ERROR));

drivers/gpu/drm/radeon/evergreen.c

4852

addr = RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR);

drivers/gpu/drm/radeon/evergreen.c

4853

status = RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS);

drivers/gpu/drm/radeon/evergreen.c

64

r = RREG32(EVERGREEN_CG_IND_DATA);

drivers/gpu/drm/radeon/evergreen.c

86

r = RREG32(EVERGREEN_PIF_PHY0_DATA);

drivers/gpu/drm/radeon/evergreen_hdmi.c

251

value = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;

drivers/gpu/drm/radeon/evergreen_hdmi.c

277

value = RREG32(DCCG_AUDIO_DTO1_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;

drivers/gpu/drm/radeon/evergreen_hdmi.c

295

unsigned int div = (RREG32(DCE41_DENTIST_DISPCLK_CNTL) &

drivers/gpu/drm/radeon/evergreen_hdmi.c

326

val = RREG32(HDMI_CONTROL + offset);

drivers/gpu/drm/radeon/evergreen_hdmi.c

43

u32 tmp = RREG32(AZ_HOT_PLUG_CONTROL);

drivers/gpu/drm/radeon/evergreen_hdmi.c

467

val = RREG32(EVERGREEN_DP_SEC_AUD_N + dig->afmt->offset);

drivers/gpu/drm/radeon/kv_dpm.c

179

data = RREG32(config_regs->offset << 2);

drivers/gpu/drm/radeon/kv_smc.c

138

original_data = RREG32(SMC_IND_DATA_0);

drivers/gpu/drm/radeon/kv_smc.c

192

original_data = RREG32(SMC_IND_DATA_0);

drivers/gpu/drm/radeon/kv_smc.c

37

if ((RREG32(SMC_RESP_0) & SMC_RESP_MASK) != 0)

drivers/gpu/drm/radeon/kv_smc.c

41

tmp = RREG32(SMC_RESP_0) & SMC_RESP_MASK;

drivers/gpu/drm/radeon/kv_smc.c

97

*value = RREG32(SMC_IND_DATA_0);

drivers/gpu/drm/radeon/ni.c

1071

rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16;

drivers/gpu/drm/radeon/ni.c

1091

simd_disable_bitmap = (RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffff0000) >> 16;

drivers/gpu/drm/radeon/ni.c

1140

cgts_sm_ctrl_reg = RREG32(CGTS_SM_CTRL_REG);

drivers/gpu/drm/radeon/ni.c

1148

sx_debug_1 = RREG32(SX_DEBUG_1);

drivers/gpu/drm/radeon/ni.c

1152

smx_dc_ctl0 = RREG32(SMX_DC_CTL0);

drivers/gpu/drm/radeon/ni.c

1214

tmp = RREG32(HDP_MISC_CNTL);

drivers/gpu/drm/radeon/ni.c

1218

hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);

drivers/gpu/drm/radeon/ni.c

1337

rdev->vm_manager.saved_table_addr[i] = RREG32(

drivers/gpu/drm/radeon/ni.c

1457

rptr = RREG32(CP_RB0_RPTR);

drivers/gpu/drm/radeon/ni.c

1459

rptr = RREG32(CP_RB1_RPTR);

drivers/gpu/drm/radeon/ni.c

1461

rptr = RREG32(CP_RB2_RPTR);

drivers/gpu/drm/radeon/ni.c

1473

wptr = RREG32(CP_RB0_WPTR);

drivers/gpu/drm/radeon/ni.c

1475

wptr = RREG32(CP_RB1_WPTR);

drivers/gpu/drm/radeon/ni.c

1477

wptr = RREG32(CP_RB2_WPTR);

drivers/gpu/drm/radeon/ni.c

1487

(void)RREG32(CP_RB0_WPTR);

drivers/gpu/drm/radeon/ni.c

1490

(void)RREG32(CP_RB1_WPTR);

drivers/gpu/drm/radeon/ni.c

1493

(void)RREG32(CP_RB2_WPTR);

drivers/gpu/drm/radeon/ni.c

1645

RREG32(GRBM_SOFT_RESET);

drivers/gpu/drm/radeon/ni.c

1648

RREG32(GRBM_SOFT_RESET);

drivers/gpu/drm/radeon/ni.c

1726

tmp = RREG32(GRBM_STATUS);

drivers/gpu/drm/radeon/ni.c

1743

tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET);

drivers/gpu/drm/radeon/ni.c

1748

tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET);

drivers/gpu/drm/radeon/ni.c

1753

tmp = RREG32(SRBM_STATUS2);

drivers/gpu/drm/radeon/ni.c

1761

tmp = RREG32(SRBM_STATUS);

drivers/gpu/drm/radeon/ni.c

1785

tmp = RREG32(VM_L2_STATUS);

drivers/gpu/drm/radeon/ni.c

1811

RREG32(0x14F8));

drivers/gpu/drm/radeon/ni.c

1813

RREG32(0x14D8));

drivers/gpu/drm/radeon/ni.c

1815

RREG32(0x14FC));

drivers/gpu/drm/radeon/ni.c

1817

RREG32(0x14DC));

drivers/gpu/drm/radeon/ni.c

1824

tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);

drivers/gpu/drm/radeon/ni.c

1831

tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);

drivers/gpu/drm/radeon/ni.c

1894

tmp = RREG32(GRBM_SOFT_RESET);

drivers/gpu/drm/radeon/ni.c

1898

tmp = RREG32(GRBM_SOFT_RESET);

drivers/gpu/drm/radeon/ni.c

1904

tmp = RREG32(GRBM_SOFT_RESET);

drivers/gpu/drm/radeon/ni.c

1908

tmp = RREG32(SRBM_SOFT_RESET);

drivers/gpu/drm/radeon/ni.c

1912

tmp = RREG32(SRBM_SOFT_RESET);

drivers/gpu/drm/radeon/ni.c

1918

tmp = RREG32(SRBM_SOFT_RESET);

drivers/gpu/drm/radeon/ni.c

2484

u64 tmp = RREG32(FUS_MC_VM_FB_OFFSET);

drivers/gpu/drm/radeon/ni.c

2703

if (RREG32(CG_ECLK_STATUS) & ECLK_STATUS)

drivers/gpu/drm/radeon/ni.c

2713

if (RREG32(CG_ECLK_STATUS) & ECLK_STATUS)

drivers/gpu/drm/radeon/ni.c

54

r = RREG32(TN_SMC_IND_DATA_0);

drivers/gpu/drm/radeon/ni.c

652

mem_type = (RREG32(MC_SEQ_MISC0) & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT;

drivers/gpu/drm/radeon/ni.c

653

running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;

drivers/gpu/drm/radeon/ni.c

677

if (RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD)

drivers/gpu/drm/radeon/ni.c

847

*val = RREG32(reg);

drivers/gpu/drm/radeon/ni.c

993

RREG32(MC_SHARED_CHMAP);

drivers/gpu/drm/radeon/ni.c

994

mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);

drivers/gpu/drm/radeon/ni_dma.c

165

rb_cntl = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);

drivers/gpu/drm/radeon/ni_dma.c

170

rb_cntl = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);

drivers/gpu/drm/radeon/ni_dma.c

238

dma_cntl = RREG32(DMA_CNTL + reg_offset);

drivers/gpu/drm/radeon/ni_dma.c

65

rptr = RREG32(reg);

drivers/gpu/drm/radeon/ni_dma.c

89

return (RREG32(reg) & 0x3fffc) >> 2;

drivers/gpu/drm/radeon/ni_dpm.c

1086

tmp = RREG32(LB_SYNC_RESET_SEL) & LB_SYNC_RESET_SEL_MASK;

drivers/gpu/drm/radeon/ni_dpm.c

1183

ni_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);

drivers/gpu/drm/radeon/ni_dpm.c

1184

ni_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);

drivers/gpu/drm/radeon/ni_dpm.c

1185

ni_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);

drivers/gpu/drm/radeon/ni_dpm.c

1186

ni_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);

drivers/gpu/drm/radeon/ni_dpm.c

1187

ni_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);

drivers/gpu/drm/radeon/ni_dpm.c

1188

ni_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);

drivers/gpu/drm/radeon/ni_dpm.c

1189

ni_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);

drivers/gpu/drm/radeon/ni_dpm.c

1190

ni_pi->clock_registers.mpll_ad_func_cntl_2 = RREG32(MPLL_AD_FUNC_CNTL_2);

drivers/gpu/drm/radeon/ni_dpm.c

1191

ni_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);

drivers/gpu/drm/radeon/ni_dpm.c

1192

ni_pi->clock_registers.mpll_dq_func_cntl_2 = RREG32(MPLL_DQ_FUNC_CNTL_2);

drivers/gpu/drm/radeon/ni_dpm.c

1193

ni_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);

drivers/gpu/drm/radeon/ni_dpm.c

1194

ni_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);

drivers/gpu/drm/radeon/ni_dpm.c

1195

ni_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);

drivers/gpu/drm/radeon/ni_dpm.c

1196

ni_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);

drivers/gpu/drm/radeon/ni_dpm.c

1208

RREG32(GB_ADDR_CONFIG);

drivers/gpu/drm/radeon/ni_dpm.c

1367

u32 tmp = RREG32(CG_CAC_CTRL) & TID_CNT_MASK;

drivers/gpu/drm/radeon/ni_dpm.c

1514

mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING);

drivers/gpu/drm/radeon/ni_dpm.c

1515

mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);

drivers/gpu/drm/radeon/ni_dpm.c

1516

burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE0_MASK) >> STATE0_SHIFT;

drivers/gpu/drm/radeon/ni_dpm.c

1519

mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_1);

drivers/gpu/drm/radeon/ni_dpm.c

1520

mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_1);

drivers/gpu/drm/radeon/ni_dpm.c

1521

burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE1_MASK) >> STATE1_SHIFT;

drivers/gpu/drm/radeon/ni_dpm.c

1524

mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_2);

drivers/gpu/drm/radeon/ni_dpm.c

1525

mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_2);

drivers/gpu/drm/radeon/ni_dpm.c

1526

burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE2_MASK) >> STATE2_SHIFT;

drivers/gpu/drm/radeon/ni_dpm.c

1529

mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_3);

drivers/gpu/drm/radeon/ni_dpm.c

1530

mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_3);

drivers/gpu/drm/radeon/ni_dpm.c

1531

burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE3_MASK) >> STATE3_SHIFT;

drivers/gpu/drm/radeon/ni_dpm.c

1562

mc_cg_config = RREG32(MC_CG_CONFIG) | 0x0000000F;

drivers/gpu/drm/radeon/ni_dpm.c

1626

dram_timing = RREG32(MC_ARB_DRAM_TIMING);

drivers/gpu/drm/radeon/ni_dpm.c

1627

dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);

drivers/gpu/drm/radeon/ni_dpm.c

2189

mc_seq_misc7 = RREG32(MC_SEQ_MISC7);

drivers/gpu/drm/radeon/ni_dpm.c

2323

u32 tmp = RREG32(DC_STUTTER_CNTL);

drivers/gpu/drm/radeon/ni_dpm.c

2350

((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))

drivers/gpu/drm/radeon/ni_dpm.c

2351

dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;

drivers/gpu/drm/radeon/ni_dpm.c

2353

dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;

drivers/gpu/drm/radeon/ni_dpm.c

2726

temp_reg = RREG32(MC_PMG_CMD_EMRS);

drivers/gpu/drm/radeon/ni_dpm.c

2737

temp_reg = RREG32(MC_PMG_CMD_MRS);

drivers/gpu/drm/radeon/ni_dpm.c

2752

temp_reg = RREG32(MC_PMG_CMD_MRS1);

drivers/gpu/drm/radeon/ni_dpm.c

2886

WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));

drivers/gpu/drm/radeon/ni_dpm.c

2887

WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));

drivers/gpu/drm/radeon/ni_dpm.c

2888

WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));

drivers/gpu/drm/radeon/ni_dpm.c

2889

WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));

drivers/gpu/drm/radeon/ni_dpm.c

2890

WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));

drivers/gpu/drm/radeon/ni_dpm.c

2891

WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));

drivers/gpu/drm/radeon/ni_dpm.c

2892

WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));

drivers/gpu/drm/radeon/ni_dpm.c

2893

WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));

drivers/gpu/drm/radeon/ni_dpm.c

2894

WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));

drivers/gpu/drm/radeon/ni_dpm.c

2895

WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));

drivers/gpu/drm/radeon/ni_dpm.c

2896

WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));

drivers/gpu/drm/radeon/ni_dpm.c

2897

WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));

drivers/gpu/drm/radeon/ni_dpm.c

2898

WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));

drivers/gpu/drm/radeon/ni_dpm.c

3154

reg = RREG32(CG_CAC_CTRL) & ~(TID_CNT_MASK | TID_UNIT_MASK);

drivers/gpu/drm/radeon/ni_dpm.c

3354

reg = RREG32(SQ_CAC_THRESHOLD) & ~(VSP_MASK |

drivers/gpu/drm/radeon/ni_dpm.c

3470

bif = RREG32(CG_BIF_REQ_AND_RSP) & ~CG_CLIENT_REQ_MASK;

drivers/gpu/drm/radeon/ni_dpm.c

3485

bif = RREG32(CG_BIF_REQ_AND_RSP) & ~CG_CLIENT_REQ_MASK;

drivers/gpu/drm/radeon/ni_dpm.c

4309

(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>

drivers/gpu/drm/radeon/ni_dpm.c

4329

(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>

drivers/gpu/drm/radeon/ni_dpm.c

4347

(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>

drivers/gpu/drm/radeon/r100.c

101

vline1 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;

drivers/gpu/drm/radeon/r100.c

102

vline2 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;

drivers/gpu/drm/radeon/r100.c

1101

rptr = RREG32(RADEON_CP_RB_RPTR);

drivers/gpu/drm/radeon/r100.c

1109

return RREG32(RADEON_CP_RB_WPTR);

drivers/gpu/drm/radeon/r100.c

1116

(void)RREG32(RADEON_CP_RB_WPTR);

drivers/gpu/drm/radeon/r100.c

126

if (!(RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN))

drivers/gpu/drm/radeon/r100.c

129

if (!(RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN))

drivers/gpu/drm/radeon/r100.c

185

if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET)

drivers/gpu/drm/radeon/r100.c

211

return !!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) &

drivers/gpu/drm/radeon/r100.c

2505

tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;

drivers/gpu/drm/radeon/r100.c

2523

tmp = RREG32(RADEON_RBBM_STATUS);

drivers/gpu/drm/radeon/r100.c

2539

tmp = RREG32(RADEON_MC_STATUS);

drivers/gpu/drm/radeon/r100.c

2552

rbbm_status = RREG32(R_000E40_RBBM_STATUS);

drivers/gpu/drm/radeon/r100.c

2565

tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;

drivers/gpu/drm/radeon/r100.c

2574

tmp = RREG32(R_000030_BUS_CNTL);

drivers/gpu/drm/radeon/r100.c

2580

tmp = RREG32(RADEON_BUS_CNTL);

drivers/gpu/drm/radeon/r100.c

2592

status = RREG32(R_000E40_RBBM_STATUS);

drivers/gpu/drm/radeon/r100.c

2597

status = RREG32(R_000E40_RBBM_STATUS);

drivers/gpu/drm/radeon/r100.c

2601

tmp = RREG32(RADEON_CP_RB_CNTL);

drivers/gpu/drm/radeon/r100.c

2614

RREG32(R_0000F0_RBBM_SOFT_RESET);

drivers/gpu/drm/radeon/r100.c

2618

status = RREG32(R_000E40_RBBM_STATUS);

drivers/gpu/drm/radeon/r100.c

2622

RREG32(R_0000F0_RBBM_SOFT_RESET);

drivers/gpu/drm/radeon/r100.c

2626

status = RREG32(R_000E40_RBBM_STATUS);

drivers/gpu/drm/radeon/r100.c

2687

u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);

drivers/gpu/drm/radeon/r100.c

2688

u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);

drivers/gpu/drm/radeon/r100.c

2689

u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);

drivers/gpu/drm/radeon/r100.c

2735

else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)

drivers/gpu/drm/radeon/r100.c

2740

tmp = RREG32(RADEON_MEM_CNTL);

drivers/gpu/drm/radeon/r100.c

2751

tmp = RREG32(RADEON_MEM_CNTL);

drivers/gpu/drm/radeon/r100.c

2768

aper_size = RREG32(RADEON_CONFIG_APER_SIZE);

drivers/gpu/drm/radeon/r100.c

2796

if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)

drivers/gpu/drm/radeon/r100.c

2812

config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);

drivers/gpu/drm/radeon/r100.c

2816

tom = RREG32(RADEON_NB_TOM);

drivers/gpu/drm/radeon/r100.c

2821

rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);

drivers/gpu/drm/radeon/r100.c

2846

temp = RREG32(RADEON_CONFIG_CNTL);

drivers/gpu/drm/radeon/r100.c

2864

base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;

drivers/gpu/drm/radeon/r100.c

2879

(void)RREG32(RADEON_CLOCK_CNTL_DATA);

drivers/gpu/drm/radeon/r100.c

2880

(void)RREG32(RADEON_CRTC_GEN_CNTL);

drivers/gpu/drm/radeon/r100.c

2901

save = RREG32(RADEON_CLOCK_CNTL_INDEX);

drivers/gpu/drm/radeon/r100.c

2904

tmp = RREG32(RADEON_CLOCK_CNTL_DATA);

drivers/gpu/drm/radeon/r100.c

2917

data = RREG32(RADEON_CLOCK_CNTL_DATA);

drivers/gpu/drm/radeon/r100.c

2958

seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));

drivers/gpu/drm/radeon/r100.c

2959

seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));

drivers/gpu/drm/radeon/r100.c

2960

seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));

drivers/gpu/drm/radeon/r100.c

2963

reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;

drivers/gpu/drm/radeon/r100.c

2965

value = RREG32(RADEON_RBBM_CMDFIFO_DATA);

drivers/gpu/drm/radeon/r100.c

2979

rdp = RREG32(RADEON_CP_RB_RPTR);

drivers/gpu/drm/radeon/r100.c

2980

wdp = RREG32(RADEON_CP_RB_WPTR);

drivers/gpu/drm/radeon/r100.c

2982

seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));

drivers/gpu/drm/radeon/r100.c

3004

seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));

drivers/gpu/drm/radeon/r100.c

3005

seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));

drivers/gpu/drm/radeon/r100.c

3006

csq_stat = RREG32(RADEON_CP_CSQ_STAT);

drivers/gpu/drm/radeon/r100.c

3007

csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);

drivers/gpu/drm/radeon/r100.c

3027

tmp = RREG32(RADEON_CP_CSQ_DATA);

drivers/gpu/drm/radeon/r100.c

3033

tmp = RREG32(RADEON_CP_CSQ_DATA);

drivers/gpu/drm/radeon/r100.c

3039

tmp = RREG32(RADEON_CP_CSQ_DATA);

drivers/gpu/drm/radeon/r100.c

3050

tmp = RREG32(RADEON_CONFIG_MEMSIZE);

drivers/gpu/drm/radeon/r100.c

3052

tmp = RREG32(RADEON_MC_FB_LOCATION);

drivers/gpu/drm/radeon/r100.c

3054

tmp = RREG32(RADEON_BUS_CNTL);

drivers/gpu/drm/radeon/r100.c

3056

tmp = RREG32(RADEON_MC_AGP_LOCATION);

drivers/gpu/drm/radeon/r100.c

3058

tmp = RREG32(RADEON_AGP_BASE);

drivers/gpu/drm/radeon/r100.c

3060

tmp = RREG32(RADEON_HOST_PATH_CNTL);

drivers/gpu/drm/radeon/r100.c

3062

tmp = RREG32(0x01D0);

drivers/gpu/drm/radeon/r100.c

3064

tmp = RREG32(RADEON_AIC_LO_ADDR);

drivers/gpu/drm/radeon/r100.c

3066

tmp = RREG32(RADEON_AIC_HI_ADDR);

drivers/gpu/drm/radeon/r100.c

3068

tmp = RREG32(0x01E4);

drivers/gpu/drm/radeon/r100.c

3266

uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);

drivers/gpu/drm/radeon/r100.c

3312

temp = RREG32(RADEON_MEM_TIMING_CNTL);

drivers/gpu/drm/radeon/r100.c

3352

temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);

drivers/gpu/drm/radeon/r100.c

3373

temp = RREG32(RADEON_MEM_CNTL);

drivers/gpu/drm/radeon/r100.c

3377

temp = RREG32(R300_MC_IND_INDEX);

drivers/gpu/drm/radeon/r100.c

3381

temp = RREG32(R300_MC_IND_DATA);

drivers/gpu/drm/radeon/r100.c

3384

temp = RREG32(R300_MC_READ_CNTL_AB);

drivers/gpu/drm/radeon/r100.c

3388

temp = RREG32(R300_MC_READ_CNTL_AB);

drivers/gpu/drm/radeon/r100.c

3524

temp = RREG32(RADEON_GRPH_BUFFER_CNTL);

drivers/gpu/drm/radeon/r100.c

3547

temp = RREG32(RS400_DISP1_REG_CNTL);

drivers/gpu/drm/radeon/r100.c

3553

temp = RREG32(RS400_DMIF_MEM_CNTL1);

drivers/gpu/drm/radeon/r100.c

3564

(unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));

drivers/gpu/drm/radeon/r100.c

3580

grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);

drivers/gpu/drm/radeon/r100.c

3639

temp = RREG32(RS400_DISP2_REQ_CNTL1);

drivers/gpu/drm/radeon/r100.c

3645

temp = RREG32(RS400_DISP2_REQ_CNTL2);

drivers/gpu/drm/radeon/r100.c

3659

(unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));

drivers/gpu/drm/radeon/r100.c

3693

tmp = RREG32(scratch);

drivers/gpu/drm/radeon/r100.c

371

tmp = RREG32(voltage->gpio.reg);

drivers/gpu/drm/radeon/r100.c

3770

tmp = RREG32(scratch);

drivers/gpu/drm/radeon/r100.c

380

tmp = RREG32(voltage->gpio.reg);

drivers/gpu/drm/radeon/r100.c

3800

save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);

drivers/gpu/drm/radeon/r100.c

3801

save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);

drivers/gpu/drm/radeon/r100.c

3802

save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);

drivers/gpu/drm/radeon/r100.c

3804

save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);

drivers/gpu/drm/radeon/r100.c

3805

save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);

drivers/gpu/drm/radeon/r100.c

3818

C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));

drivers/gpu/drm/radeon/r100.c

3938

rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);

drivers/gpu/drm/radeon/r100.c

3967

RREG32(R_000E40_RBBM_STATUS),

drivers/gpu/drm/radeon/r100.c

3968

RREG32(R_0007C0_CP_STAT));

drivers/gpu/drm/radeon/r100.c

4025

tmp = RREG32(RADEON_CP_CSQ_CNTL);

drivers/gpu/drm/radeon/r100.c

4029

tmp = RREG32(RADEON_CP_RB_CNTL);

drivers/gpu/drm/radeon/r100.c

4033

tmp = RREG32(RADEON_SCRATCH_UMSK);

drivers/gpu/drm/radeon/r100.c

4071

RREG32(R_000E40_RBBM_STATUS),

drivers/gpu/drm/radeon/r100.c

4072

RREG32(R_0007C0_CP_STAT));

drivers/gpu/drm/radeon/r100.c

472

tmp = RREG32(RADEON_CRTC2_GEN_CNTL);

drivers/gpu/drm/radeon/r100.c

476

tmp = RREG32(RADEON_CRTC_GEN_CNTL);

drivers/gpu/drm/radeon/r100.c

503

tmp = RREG32(RADEON_CRTC2_GEN_CNTL);

drivers/gpu/drm/radeon/r100.c

507

tmp = RREG32(RADEON_CRTC_GEN_CNTL);

drivers/gpu/drm/radeon/r100.c

525

if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)

drivers/gpu/drm/radeon/r100.c

547

if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)

drivers/gpu/drm/radeon/r100.c

551

if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)

drivers/gpu/drm/radeon/r100.c

576

tmp = RREG32(RADEON_FP_GEN_CNTL);

drivers/gpu/drm/radeon/r100.c

584

tmp = RREG32(RADEON_FP2_GEN_CNTL);

drivers/gpu/drm/radeon/r100.c

676

tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;

drivers/gpu/drm/radeon/r100.c

683

tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;

drivers/gpu/drm/radeon/r100.c

698

tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;

drivers/gpu/drm/radeon/r100.c

752

RREG32(RADEON_GEN_INT_CNTL);

drivers/gpu/drm/radeon/r100.c

764

tmp = RREG32(R_000044_GEN_INT_STATUS);

drivers/gpu/drm/radeon/r100.c

770

uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);

drivers/gpu/drm/radeon/r100.c

81

if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR)

drivers/gpu/drm/radeon/r100.c

833

msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;

drivers/gpu/drm/radeon/r100.c

848

return RREG32(RADEON_CRTC_CRNT_FRAME);

drivers/gpu/drm/radeon/r100.c

850

return RREG32(RADEON_CRTC2_CRNT_FRAME);

drivers/gpu/drm/radeon/r100.c

86

if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR)

drivers/gpu/drm/radeon/r100.c

98

vline1 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;

drivers/gpu/drm/radeon/r100.c

984

tmp = RREG32(R_000E40_RBBM_STATUS);

drivers/gpu/drm/radeon/r100.c

99

vline2 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;

drivers/gpu/drm/radeon/r300.c

1421

rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);

drivers/gpu/drm/radeon/r300.c

1452

RREG32(R_000E40_RBBM_STATUS),

drivers/gpu/drm/radeon/r300.c

1453

RREG32(R_0007C0_CP_STAT));

drivers/gpu/drm/radeon/r300.c

1533

RREG32(R_000E40_RBBM_STATUS),

drivers/gpu/drm/radeon/r300.c

1534

RREG32(R_0007C0_CP_STAT));

drivers/gpu/drm/radeon/r300.c

341

(RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) {

drivers/gpu/drm/radeon/r300.c

353

tmp = RREG32(RADEON_MC_STATUS);

drivers/gpu/drm/radeon/r300.c

398

tmp = RREG32(R300_DST_PIPE_CONFIG);

drivers/gpu/drm/radeon/r300.c

421

status = RREG32(R_000E40_RBBM_STATUS);

drivers/gpu/drm/radeon/r300.c

426

status = RREG32(R_000E40_RBBM_STATUS);

drivers/gpu/drm/radeon/r300.c

430

tmp = RREG32(RADEON_CP_RB_CNTL);

drivers/gpu/drm/radeon/r300.c

441

RREG32(R_0000F0_RBBM_SOFT_RESET);

drivers/gpu/drm/radeon/r300.c

445

status = RREG32(R_000E40_RBBM_STATUS);

drivers/gpu/drm/radeon/r300.c

453

RREG32(R_0000F0_RBBM_SOFT_RESET);

drivers/gpu/drm/radeon/r300.c

457

status = RREG32(R_000E40_RBBM_STATUS);

drivers/gpu/drm/radeon/r300.c

482

tmp = RREG32(RADEON_MEM_CNTL);

drivers/gpu/drm/radeon/r300.c

493

base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;

drivers/gpu/drm/radeon/r300.c

67

r = RREG32(RADEON_PCIE_DATA);

drivers/gpu/drm/radeon/r420.c

104

gb_pipe_select = RREG32(R400_GB_PIPE_SELECT);

drivers/gpu/drm/radeon/r420.c

140

tmp = RREG32(R300_DST_PIPE_CONFIG);

drivers/gpu/drm/radeon/r420.c

144

RREG32(R300_RB2D_DSTCACHE_MODE) |

drivers/gpu/drm/radeon/r420.c

153

tmp = RREG32(RV530_GB_PIPE_SELECT2);

drivers/gpu/drm/radeon/r420.c

172

r = RREG32(R_0001FC_MC_IND_DATA);

drivers/gpu/drm/radeon/r420.c

286

rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);

drivers/gpu/drm/radeon/r420.c

318

RREG32(R_000E40_RBBM_STATUS),

drivers/gpu/drm/radeon/r420.c

319

RREG32(R_0007C0_CP_STAT));

drivers/gpu/drm/radeon/r420.c

409

RREG32(R_000E40_RBBM_STATUS),

drivers/gpu/drm/radeon/r420.c

410

RREG32(R_0007C0_CP_STAT));

drivers/gpu/drm/radeon/r420.c

481

tmp = RREG32(R400_GB_PIPE_SELECT);

drivers/gpu/drm/radeon/r420.c

483

tmp = RREG32(R300_GB_TILE_CONFIG);

drivers/gpu/drm/radeon/r420.c

485

tmp = RREG32(R300_DST_PIPE_CONFIG);

drivers/gpu/drm/radeon/r520.c

203

rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);

drivers/gpu/drm/radeon/r520.c

232

RREG32(R_000E40_RBBM_STATUS),

drivers/gpu/drm/radeon/r520.c

233

RREG32(R_0007C0_CP_STAT));

drivers/gpu/drm/radeon/r520.c

278

RREG32(R_000E40_RBBM_STATUS),

drivers/gpu/drm/radeon/r520.c

279

RREG32(R_0007C0_CP_STAT));

drivers/gpu/drm/radeon/r520.c

82

gb_pipe_select = RREG32(R400_GB_PIPE_SELECT);

drivers/gpu/drm/radeon/r520.c

83

tmp = RREG32(R300_DST_PIPE_CONFIG);

drivers/gpu/drm/radeon/r600.c

1099

tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);

drivers/gpu/drm/radeon/r600.c

1269

tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;

drivers/gpu/drm/radeon/r600.c

127

r = RREG32(R600_RCU_DATA);

drivers/gpu/drm/radeon/r600.c

1284

r = RREG32(R_0028FC_MC_DATA);

drivers/gpu/drm/radeon/r600.c

1424

base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF;

drivers/gpu/drm/radeon/r600.c

1442

tmp = RREG32(RAMCFG);

drivers/gpu/drm/radeon/r600.c

1450

tmp = RREG32(CHMAP);

drivers/gpu/drm/radeon/r600.c

1471

rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);

drivers/gpu/drm/radeon/r600.c

1472

rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);

drivers/gpu/drm/radeon/r600.c

149

r = RREG32(R600_UVD_CTX_DATA);

drivers/gpu/drm/radeon/r600.c

1556

u32 tmp = RREG32(R600_BIOS_3_SCRATCH);

drivers/gpu/drm/radeon/r600.c

1569

RREG32(R_008010_GRBM_STATUS));

drivers/gpu/drm/radeon/r600.c

1571

RREG32(R_008014_GRBM_STATUS2));

drivers/gpu/drm/radeon/r600.c

1573

RREG32(R_000E50_SRBM_STATUS));

drivers/gpu/drm/radeon/r600.c

1575

RREG32(CP_STALLED_STAT1));

drivers/gpu/drm/radeon/r600.c

1577

RREG32(CP_STALLED_STAT2));

drivers/gpu/drm/radeon/r600.c

1579

RREG32(CP_BUSY_STAT));

drivers/gpu/drm/radeon/r600.c

1581

RREG32(CP_STAT));

drivers/gpu/drm/radeon/r600.c

1583

RREG32(DMA_STATUS_REG));

drivers/gpu/drm/radeon/r600.c

1593

if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN) {

drivers/gpu/drm/radeon/r600.c

1594

crtc_status[i] = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]);

drivers/gpu/drm/radeon/r600.c

1602

tmp = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]);

drivers/gpu/drm/radeon/r600.c

1621

tmp = RREG32(R_008010_GRBM_STATUS);

drivers/gpu/drm/radeon/r600.c

1646

tmp = RREG32(DMA_STATUS_REG);

drivers/gpu/drm/radeon/r600.c

1651

tmp = RREG32(R_000E50_SRBM_STATUS);

drivers/gpu/drm/radeon/r600.c

1708

tmp = RREG32(DMA_RB_CNTL);

drivers/gpu/drm/radeon/r600.c

1784

tmp = RREG32(R_008020_GRBM_SOFT_RESET);

drivers/gpu/drm/radeon/r600.c

1788

tmp = RREG32(R_008020_GRBM_SOFT_RESET);

drivers/gpu/drm/radeon/r600.c

1794

tmp = RREG32(R_008020_GRBM_SOFT_RESET);

drivers/gpu/drm/radeon/r600.c

1798

tmp = RREG32(SRBM_SOFT_RESET);

drivers/gpu/drm/radeon/r600.c

1802

tmp = RREG32(SRBM_SOFT_RESET);

drivers/gpu/drm/radeon/r600.c

1808

tmp = RREG32(SRBM_SOFT_RESET);

drivers/gpu/drm/radeon/r600.c

183

*val = RREG32(reg);

drivers/gpu/drm/radeon/r600.c

1839

tmp = RREG32(DMA_RB_CNTL);

drivers/gpu/drm/radeon/r600.c

1857

tmp = RREG32(BUS_CNTL);

drivers/gpu/drm/radeon/r600.c

1861

tmp = RREG32(BIF_SCRATCH0);

drivers/gpu/drm/radeon/r600.c

1875

if (RREG32(CONFIG_MEMSIZE) != 0xffffffff)

drivers/gpu/drm/radeon/r600.c

2087

ramcfg = RREG32(RAMCFG);

drivers/gpu/drm/radeon/r600.c

2119

cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0x00ffff00;

drivers/gpu/drm/radeon/r600.c

2124

disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R6XX_MAX_BACKENDS_MASK;

drivers/gpu/drm/radeon/r600.c

2159

tmp = RREG32(SX_DEBUG_1);

drivers/gpu/drm/radeon/r600.c

2184

tmp = RREG32(SQ_MS_FIFO_SIZES);

drivers/gpu/drm/radeon/r600.c

2203

sq_config = RREG32(SQ_CONFIG);

drivers/gpu/drm/radeon/r600.c

2377

tmp = RREG32(HDP_HOST_PATH_CNTL);

drivers/gpu/drm/radeon/r600.c

2380

tmp = RREG32(ARB_POP);

drivers/gpu/drm/radeon/r600.c

2402

(void)RREG32(PCIE_PORT_INDEX);

drivers/gpu/drm/radeon/r600.c

2403

r = RREG32(PCIE_PORT_DATA);

drivers/gpu/drm/radeon/r600.c

2414

(void)RREG32(PCIE_PORT_INDEX);

drivers/gpu/drm/radeon/r600.c

2416

(void)RREG32(PCIE_PORT_DATA);

drivers/gpu/drm/radeon/r600.c

2626

rptr = RREG32(R600_CP_RB_RPTR);

drivers/gpu/drm/radeon/r600.c

2634

return RREG32(R600_CP_RB_WPTR);

drivers/gpu/drm/radeon/r600.c

2641

(void)RREG32(R600_CP_RB_WPTR);

drivers/gpu/drm/radeon/r600.c

2662

RREG32(GRBM_SOFT_RESET);

drivers/gpu/drm/radeon/r600.c

2725

RREG32(GRBM_SOFT_RESET);

drivers/gpu/drm/radeon/r600.c

2847

tmp = RREG32(scratch);

drivers/gpu/drm/radeon/r600.c

3194

temp = RREG32(CONFIG_CNTL);

drivers/gpu/drm/radeon/r600.c

3436

tmp = RREG32(scratch);

drivers/gpu/drm/radeon/r600.c

352

u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >>

drivers/gpu/drm/radeon/r600.c

3537

RREG32(SRBM_SOFT_RESET);

drivers/gpu/drm/radeon/r600.c

3540

RREG32(SRBM_SOFT_RESET);

drivers/gpu/drm/radeon/r600.c

3592

u32 ih_cntl = RREG32(IH_CNTL);

drivers/gpu/drm/radeon/r600.c

3593

u32 ih_rb_cntl = RREG32(IH_RB_CNTL);

drivers/gpu/drm/radeon/r600.c

3604

u32 ih_rb_cntl = RREG32(IH_RB_CNTL);

drivers/gpu/drm/radeon/r600.c

3605

u32 ih_cntl = RREG32(IH_CNTL);

drivers/gpu/drm/radeon/r600.c

3623

tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE;

drivers/gpu/drm/radeon/r600.c

3632

tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;

drivers/gpu/drm/radeon/r600.c

3634

tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;

drivers/gpu/drm/radeon/r600.c

3636

tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;

drivers/gpu/drm/radeon/r600.c

3638

tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;

drivers/gpu/drm/radeon/r600.c

3641

tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;

drivers/gpu/drm/radeon/r600.c

3643

tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;

drivers/gpu/drm/radeon/r600.c

3645

tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;

drivers/gpu/drm/radeon/r600.c

3647

tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;

drivers/gpu/drm/radeon/r600.c

3650

tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;

drivers/gpu/drm/radeon/r600.c

3652

tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;

drivers/gpu/drm/radeon/r600.c

3658

tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;

drivers/gpu/drm/radeon/r600.c

3660

tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;

drivers/gpu/drm/radeon/r600.c

3662

tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;

drivers/gpu/drm/radeon/r600.c

3664

tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;

drivers/gpu/drm/radeon/r600.c

3666

tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;

drivers/gpu/drm/radeon/r600.c

3698

interrupt_cntl = RREG32(INTERRUPT_CNTL);

drivers/gpu/drm/radeon/r600.c

3784

hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;

drivers/gpu/drm/radeon/r600.c

3785

hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;

drivers/gpu/drm/radeon/r600.c

3786

hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;

drivers/gpu/drm/radeon/r600.c

3787

hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;

drivers/gpu/drm/radeon/r600.c

3789

hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;

drivers/gpu/drm/radeon/r600.c

3790

hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;

drivers/gpu/drm/radeon/r600.c

3791

hdmi0 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~AFMT_AZ_FORMAT_WTRIG_MASK;

drivers/gpu/drm/radeon/r600.c

3792

hdmi1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~AFMT_AZ_FORMAT_WTRIG_MASK;

drivers/gpu/drm/radeon/r600.c

3794

hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;

drivers/gpu/drm/radeon/r600.c

3795

hdmi1 = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;

drivers/gpu/drm/radeon/r600.c

3798

hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;

drivers/gpu/drm/radeon/r600.c

3799

hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;

drivers/gpu/drm/radeon/r600.c

3800

hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;

drivers/gpu/drm/radeon/r600.c

3801

hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;

drivers/gpu/drm/radeon/r600.c

3802

hdmi1 = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;

drivers/gpu/drm/radeon/r600.c

3805

dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE;

drivers/gpu/drm/radeon/r600.c

3808

thermal_int = RREG32(CG_THERMAL_INT) &

drivers/gpu/drm/radeon/r600.c

3811

thermal_int = RREG32(RV770_CG_THERMAL_INT) &

drivers/gpu/drm/radeon/r600.c

3907

RREG32(R_000E50_SRBM_STATUS);

drivers/gpu/drm/radeon/r600.c

3917

rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);

drivers/gpu/drm/radeon/r600.c

3918

rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);

drivers/gpu/drm/radeon/r600.c

3919

rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);

drivers/gpu/drm/radeon/r600.c

3921

rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0);

drivers/gpu/drm/radeon/r600.c

3922

rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1);

drivers/gpu/drm/radeon/r600.c

3924

rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);

drivers/gpu/drm/radeon/r600.c

3925

rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS);

drivers/gpu/drm/radeon/r600.c

3928

rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS);

drivers/gpu/drm/radeon/r600.c

3929

rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);

drivers/gpu/drm/radeon/r600.c

3931

rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);

drivers/gpu/drm/radeon/r600.c

3932

rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS);

drivers/gpu/drm/radeon/r600.c

3934

rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS);

drivers/gpu/drm/radeon/r600.c

3935

rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS);

drivers/gpu/drm/radeon/r600.c

3951

tmp = RREG32(DC_HPD1_INT_CONTROL);

drivers/gpu/drm/radeon/r600.c

3955

tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);

drivers/gpu/drm/radeon/r600.c

3962

tmp = RREG32(DC_HPD2_INT_CONTROL);

drivers/gpu/drm/radeon/r600.c

3966

tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);

drivers/gpu/drm/radeon/r600.c

3973

tmp = RREG32(DC_HPD3_INT_CONTROL);

drivers/gpu/drm/radeon/r600.c

3977

tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);

drivers/gpu/drm/radeon/r600.c

3983

tmp = RREG32(DC_HPD4_INT_CONTROL);

drivers/gpu/drm/radeon/r600.c

3989

tmp = RREG32(DC_HPD5_INT_CONTROL);

drivers/gpu/drm/radeon/r600.c

3994

tmp = RREG32(DC_HPD6_INT_CONTROL);

drivers/gpu/drm/radeon/r600.c

3999

tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0);

drivers/gpu/drm/radeon/r600.c

4004

tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1);

drivers/gpu/drm/radeon/r600.c

4010

tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL);

drivers/gpu/drm/radeon/r600.c

4016

tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL);

drivers/gpu/drm/radeon/r600.c

4020

tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL);

drivers/gpu/drm/radeon/r600.c

4044

wptr = RREG32(IH_RB_WPTR);

drivers/gpu/drm/radeon/r600.c

4055

tmp = RREG32(IH_RB_CNTL);

drivers/gpu/drm/radeon/r600.c

4107

RREG32(IH_RB_WPTR);

drivers/gpu/drm/radeon/r600.c

4549

link_cntl2 = RREG32(0x4088);

drivers/gpu/drm/radeon/r600.c

4563

tmp = RREG32(0x541c);

drivers/gpu/drm/radeon/r600.c

4613

clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |

drivers/gpu/drm/radeon/r600.c

4614

((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);

drivers/gpu/drm/radeon/r600.c

797

if (RREG32(GRBM_STATUS) & GUI_ACTIVE)

drivers/gpu/drm/radeon/r600.c

811

if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)

drivers/gpu/drm/radeon/r600.c

815

if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)

drivers/gpu/drm/radeon/r600.c

819

if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)

drivers/gpu/drm/radeon/r600.c

823

if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)

drivers/gpu/drm/radeon/r600.c

828

if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)

drivers/gpu/drm/radeon/r600.c

832

if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)

drivers/gpu/drm/radeon/r600.c

841

if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)

drivers/gpu/drm/radeon/r600.c

845

if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)

drivers/gpu/drm/radeon/r600.c

849

if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)

drivers/gpu/drm/radeon/r600.c

868

tmp = RREG32(DC_HPD1_INT_CONTROL);

drivers/gpu/drm/radeon/r600.c

876

tmp = RREG32(DC_HPD2_INT_CONTROL);

drivers/gpu/drm/radeon/r600.c

884

tmp = RREG32(DC_HPD3_INT_CONTROL);

drivers/gpu/drm/radeon/r600.c

892

tmp = RREG32(DC_HPD4_INT_CONTROL);

drivers/gpu/drm/radeon/r600.c

900

tmp = RREG32(DC_HPD5_INT_CONTROL);

drivers/gpu/drm/radeon/r600.c

909

tmp = RREG32(DC_HPD6_INT_CONTROL);

drivers/gpu/drm/radeon/r600.c

922

tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);

drivers/gpu/drm/radeon/r600.c

930

tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);

drivers/gpu/drm/radeon/r600.c

938

tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);

drivers/gpu/drm/radeon/r600_dma.c

100

u32 rb_cntl = RREG32(DMA_RB_CNTL);

drivers/gpu/drm/radeon/r600_dma.c

159

dma_cntl = RREG32(DMA_CNTL);

drivers/gpu/drm/radeon/r600_dma.c

58

rptr = RREG32(DMA_RB_RPTR);

drivers/gpu/drm/radeon/r600_dma.c

74

return (RREG32(DMA_RB_WPTR) & 0x3fffc) >> 2;

drivers/gpu/drm/radeon/r600_dpm.c

252

if (((RREG32(CG_RLC_REQ_AND_RSP) & CG_RLC_RSP_TYPE_MASK) >> CG_RLC_RSP_TYPE_SHIFT) == 1)

drivers/gpu/drm/radeon/r600_dpm.c

260

RREG32(GRBM_PWR_CNTL);

drivers/gpu/drm/radeon/r600_dpm.c

295

if (RREG32(GENERAL_PWRMGT) & GLOBAL_PWRMGT_EN)

drivers/gpu/drm/radeon/r600_dpm.c

330

if (RREG32(CG_SPLL_FUNC_CNTL) & SPLL_CHG_STATUS)

drivers/gpu/drm/radeon/r600_dpm.c

536

tmp = RREG32(VID_UPPER_GPIO_CNTL);

drivers/gpu/drm/radeon/r600_dpm.c

546

gpio = RREG32(GPIOPAD_MASK);

drivers/gpu/drm/radeon/r600_dpm.c

550

gpio = RREG32(GPIOPAD_EN);

drivers/gpu/drm/radeon/r600_dpm.c

554

gpio = RREG32(GPIOPAD_A);

drivers/gpu/drm/radeon/r600_dpm.c

626

tmp = RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK;

drivers/gpu/drm/radeon/r600_dpm.c

635

tmp = RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & TARGET_PROFILE_INDEX_MASK;

drivers/gpu/drm/radeon/r600_hdmi.c

101

value = RREG32(R600_AUDIO_STATUS_BITS);

drivers/gpu/drm/radeon/r600_hdmi.c

146

u32 tmp = RREG32(AZ_HOT_PLUG_CONTROL);

drivers/gpu/drm/radeon/r600_hdmi.c

271

return (RREG32(HDMI0_STATUS + offset) & 0x10) != 0;

drivers/gpu/drm/radeon/r600_hdmi.c

427

value = RREG32(HDMI0_AUDIO_PACKET_CONTROL + offset);

drivers/gpu/drm/radeon/r600_hdmi.c

65

value = RREG32(R600_AUDIO_RATE_BPS_CHANNEL);

drivers/gpu/drm/radeon/radeon.h

2537

uint32_t tmp_ = RREG32(reg); \

drivers/gpu/drm/radeon/radeon_agp.c

258

agp_status = (RREG32(RADEON_AGP_STATUS) | RADEON_AGPv3_MODE) & mode.mode;

drivers/gpu/drm/radeon/radeon_agp.c

346

WREG32(RADEON_AGP_CNTL, RREG32(RADEON_AGP_CNTL) | 0x000e0000);

drivers/gpu/drm/radeon/radeon_atombios.c

4070

bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);

drivers/gpu/drm/radeon/radeon_atombios.c

4071

bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);

drivers/gpu/drm/radeon/radeon_atombios.c

4073

bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);

drivers/gpu/drm/radeon/radeon_atombios.c

4074

bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);

drivers/gpu/drm/radeon/radeon_atombios.c

4108

rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));

drivers/gpu/drm/radeon/radeon_atombios.c

4132

bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);

drivers/gpu/drm/radeon/radeon_atombios.c

4134

bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);

drivers/gpu/drm/radeon/radeon_atombios.c

4164

bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);

drivers/gpu/drm/radeon/radeon_atombios.c

4165

bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);

drivers/gpu/drm/radeon/radeon_atombios.c

4166

bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);

drivers/gpu/drm/radeon/radeon_atombios.c

4168

bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);

drivers/gpu/drm/radeon/radeon_atombios.c

4169

bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);

drivers/gpu/drm/radeon/radeon_atombios.c

4170

bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);

drivers/gpu/drm/radeon/radeon_atombios.c

4349

bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);

drivers/gpu/drm/radeon/radeon_atombios.c

4351

bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);

drivers/gpu/drm/radeon/radeon_atombios.c

4404

bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);

drivers/gpu/drm/radeon/radeon_atombios.c

4406

bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);

drivers/gpu/drm/radeon/radeon_audio.c

59

return RREG32(reg);

drivers/gpu/drm/radeon/radeon_bios.c

259

bus_cntl = RREG32(R600_BUS_CNTL);

drivers/gpu/drm/radeon/radeon_bios.c

260

d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);

drivers/gpu/drm/radeon/radeon_bios.c

261

d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);

drivers/gpu/drm/radeon/radeon_bios.c

262

vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);

drivers/gpu/drm/radeon/radeon_bios.c

263

rom_cntl = RREG32(R600_ROM_CNTL);

drivers/gpu/drm/radeon/radeon_bios.c

305

viph_control = RREG32(RADEON_VIPH_CONTROL);

drivers/gpu/drm/radeon/radeon_bios.c

306

bus_cntl = RREG32(R600_BUS_CNTL);

drivers/gpu/drm/radeon/radeon_bios.c

307

d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);

drivers/gpu/drm/radeon/radeon_bios.c

308

d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);

drivers/gpu/drm/radeon/radeon_bios.c

309

vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);

drivers/gpu/drm/radeon/radeon_bios.c

310

rom_cntl = RREG32(R600_ROM_CNTL);

drivers/gpu/drm/radeon/radeon_bios.c

327

cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL);

drivers/gpu/drm/radeon/radeon_bios.c

336

cg_spll_status = RREG32(R600_CG_SPLL_STATUS);

drivers/gpu/drm/radeon/radeon_bios.c

351

cg_spll_status = RREG32(R600_CG_SPLL_STATUS);

drivers/gpu/drm/radeon/radeon_bios.c

378

viph_control = RREG32(RADEON_VIPH_CONTROL);

drivers/gpu/drm/radeon/radeon_bios.c

379

bus_cntl = RREG32(R600_BUS_CNTL);

drivers/gpu/drm/radeon/radeon_bios.c

380

d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);

drivers/gpu/drm/radeon/radeon_bios.c

381

d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);

drivers/gpu/drm/radeon/radeon_bios.c

382

vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);

drivers/gpu/drm/radeon/radeon_bios.c

383

rom_cntl = RREG32(R600_ROM_CNTL);

drivers/gpu/drm/radeon/radeon_bios.c

384

general_pwrmgt = RREG32(R600_GENERAL_PWRMGT);

drivers/gpu/drm/radeon/radeon_bios.c

385

low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL);

drivers/gpu/drm/radeon/radeon_bios.c

386

medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL);

drivers/gpu/drm/radeon/radeon_bios.c

387

high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL);

drivers/gpu/drm/radeon/radeon_bios.c

388

ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL);

drivers/gpu/drm/radeon/radeon_bios.c

389

lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE);

drivers/gpu/drm/radeon/radeon_bios.c

452

seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);

drivers/gpu/drm/radeon/radeon_bios.c

453

viph_control = RREG32(RADEON_VIPH_CONTROL);

drivers/gpu/drm/radeon/radeon_bios.c

454

bus_cntl = RREG32(RV370_BUS_CNTL);

drivers/gpu/drm/radeon/radeon_bios.c

455

d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);

drivers/gpu/drm/radeon/radeon_bios.c

456

d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);

drivers/gpu/drm/radeon/radeon_bios.c

457

vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);

drivers/gpu/drm/radeon/radeon_bios.c

458

gpiopad_a = RREG32(RADEON_GPIOPAD_A);

drivers/gpu/drm/radeon/radeon_bios.c

459

gpiopad_en = RREG32(RADEON_GPIOPAD_EN);

drivers/gpu/drm/radeon/radeon_bios.c

460

gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK);

drivers/gpu/drm/radeon/radeon_bios.c

511

seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);

drivers/gpu/drm/radeon/radeon_bios.c

512

viph_control = RREG32(RADEON_VIPH_CONTROL);

drivers/gpu/drm/radeon/radeon_bios.c

514

bus_cntl = RREG32(RV370_BUS_CNTL);

drivers/gpu/drm/radeon/radeon_bios.c

516

bus_cntl = RREG32(RADEON_BUS_CNTL);

drivers/gpu/drm/radeon/radeon_bios.c

517

crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);

drivers/gpu/drm/radeon/radeon_bios.c

519

crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);

drivers/gpu/drm/radeon/radeon_bios.c

523

fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);

drivers/gpu/drm/radeon/radeon_bios.c

527

crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);

drivers/gpu/drm/radeon/radeon_clocks.c

483

if ((RREG32(RADEON_CONFIG_CNTL) &

drivers/gpu/drm/radeon/radeon_clocks.c

622

if (RREG32(RADEON_MEM_CNTL) &

drivers/gpu/drm/radeon/radeon_clocks.c

675

((RREG32(RADEON_CONFIG_CNTL) &

drivers/gpu/drm/radeon/radeon_clocks.c

680

((RREG32(RADEON_CONFIG_CNTL) &

drivers/gpu/drm/radeon/radeon_clocks.c

698

((RREG32(RADEON_CONFIG_CNTL) &

drivers/gpu/drm/radeon/radeon_clocks.c

710

((RREG32(RADEON_CONFIG_CNTL) &

drivers/gpu/drm/radeon/radeon_combios.c

1090

uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);

drivers/gpu/drm/radeon/radeon_combios.c

1097

fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);

drivers/gpu/drm/radeon/radeon_combios.c

1098

fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);

drivers/gpu/drm/radeon/radeon_combios.c

1104

lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);

drivers/gpu/drm/radeon/radeon_combios.c

1114

(RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;

drivers/gpu/drm/radeon/radeon_combios.c

1122

((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;

drivers/gpu/drm/radeon/radeon_combios.c

2902

val = RREG32(reg);

drivers/gpu/drm/radeon/radeon_combios.c

2956

val = RREG32(reg);

drivers/gpu/drm/radeon/radeon_combios.c

3023

tmp = RREG32(addr);

drivers/gpu/drm/radeon/radeon_combios.c

3033

tmp = RREG32(addr);

drivers/gpu/drm/radeon/radeon_combios.c

3058

if ((RREG32(RADEON_MC_STATUS) &

drivers/gpu/drm/radeon/radeon_combios.c

3186

if ((RREG32(RADEON_MEM_STR_CNTL) &

drivers/gpu/drm/radeon/radeon_combios.c

3195

tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);

drivers/gpu/drm/radeon/radeon_combios.c

3201

tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);

drivers/gpu/drm/radeon/radeon_combios.c

3219

mem_cntl = RREG32(RADEON_MEM_CNTL);

drivers/gpu/drm/radeon/radeon_combios.c

3226

RREG32(RADEON_MEM_CNTL);

drivers/gpu/drm/radeon/radeon_combios.c

3402

bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);

drivers/gpu/drm/radeon/radeon_combios.c

3403

bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);

drivers/gpu/drm/radeon/radeon_combios.c

3404

bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);

drivers/gpu/drm/radeon/radeon_combios.c

3427

bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);

drivers/gpu/drm/radeon/radeon_combios.c

3447

uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);

drivers/gpu/drm/radeon/radeon_combios.c

3448

uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);

drivers/gpu/drm/radeon/radeon_combios.c

3546

uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);

drivers/gpu/drm/radeon/radeon_combios.c

3581

uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);

drivers/gpu/drm/radeon/radeon_cursor.c

39

cur_lock = RREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset);

drivers/gpu/drm/radeon/radeon_cursor.c

46

cur_lock = RREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset);

drivers/gpu/drm/radeon/radeon_cursor.c

53

cur_lock = RREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset);

drivers/gpu/drm/radeon/radeon_device.c

220

tmp = RREG32(reg);

drivers/gpu/drm/radeon/radeon_device.c

676

reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |

drivers/gpu/drm/radeon/radeon_device.c

677

RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);

drivers/gpu/drm/radeon/radeon_device.c

679

reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |

drivers/gpu/drm/radeon/radeon_device.c

680

RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);

drivers/gpu/drm/radeon/radeon_device.c

683

reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |

drivers/gpu/drm/radeon/radeon_device.c

684

RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);

drivers/gpu/drm/radeon/radeon_device.c

689

reg = RREG32(AVIVO_D1CRTC_CONTROL) |

drivers/gpu/drm/radeon/radeon_device.c

690

RREG32(AVIVO_D2CRTC_CONTROL);

drivers/gpu/drm/radeon/radeon_device.c

695

reg = RREG32(RADEON_CRTC_GEN_CNTL) |

drivers/gpu/drm/radeon/radeon_device.c

696

RREG32(RADEON_CRTC2_GEN_CNTL);

drivers/gpu/drm/radeon/radeon_device.c

705

reg = RREG32(R600_CONFIG_MEMSIZE);

drivers/gpu/drm/radeon/radeon_device.c

707

reg = RREG32(RADEON_CONFIG_MEMSIZE);

drivers/gpu/drm/radeon/radeon_device.c

926

r = RREG32(reg*4);

drivers/gpu/drm/radeon/radeon_display.c

1838

vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +

drivers/gpu/drm/radeon/radeon_display.c

1840

position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +

drivers/gpu/drm/radeon/radeon_display.c

1845

vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +

drivers/gpu/drm/radeon/radeon_display.c

1847

position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +

drivers/gpu/drm/radeon/radeon_display.c

1852

vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +

drivers/gpu/drm/radeon/radeon_display.c

1854

position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +

drivers/gpu/drm/radeon/radeon_display.c

1859

vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +

drivers/gpu/drm/radeon/radeon_display.c

1861

position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +

drivers/gpu/drm/radeon/radeon_display.c

1866

vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +

drivers/gpu/drm/radeon/radeon_display.c

1868

position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +

drivers/gpu/drm/radeon/radeon_display.c

1873

vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +

drivers/gpu/drm/radeon/radeon_display.c

1875

position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +

drivers/gpu/drm/radeon/radeon_display.c

1881

vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);

drivers/gpu/drm/radeon/radeon_display.c

1882

position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);

drivers/gpu/drm/radeon/radeon_display.c

1886

vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);

drivers/gpu/drm/radeon/radeon_display.c

1887

position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);

drivers/gpu/drm/radeon/radeon_display.c

1896

vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &

drivers/gpu/drm/radeon/radeon_display.c

1899

position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;

drivers/gpu/drm/radeon/radeon_display.c

1900

stat_crtc = RREG32(RADEON_CRTC_STATUS);

drivers/gpu/drm/radeon/radeon_display.c

1907

vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &

drivers/gpu/drm/radeon/radeon_display.c

1909

position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;

drivers/gpu/drm/radeon/radeon_display.c

1910

stat_crtc = RREG32(RADEON_CRTC2_STATUS);

drivers/gpu/drm/radeon/radeon_display.c

203

dac2_cntl = RREG32(RADEON_DAC_CNTL2);

drivers/gpu/drm/radeon/radeon_dp_auxch.c

104

tmp = RREG32(AUX_CONTROL + aux_offset[instance]);

drivers/gpu/drm/radeon/radeon_dp_auxch.c

153

tmp = RREG32(AUX_SW_STATUS + aux_offset[instance]);

drivers/gpu/drm/radeon/radeon_dp_auxch.c

181

tmp = RREG32(AUX_SW_DATA + aux_offset[instance]);

drivers/gpu/drm/radeon/radeon_dp_auxch.c

185

tmp = RREG32(AUX_SW_DATA + aux_offset[instance]);

drivers/gpu/drm/radeon/radeon_dp_auxch.c

99

tmp = RREG32(chan->rec.mask_clk_reg);

drivers/gpu/drm/radeon/radeon_fence.c

99

seq = RREG32(drv->scratch_reg);

drivers/gpu/drm/radeon/radeon_i2c.c

124

temp = RREG32(rec->mask_clk_reg);

drivers/gpu/drm/radeon/radeon_i2c.c

130

temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask;

drivers/gpu/drm/radeon/radeon_i2c.c

133

temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask;

drivers/gpu/drm/radeon/radeon_i2c.c

137

temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;

drivers/gpu/drm/radeon/radeon_i2c.c

140

temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask;

drivers/gpu/drm/radeon/radeon_i2c.c

144

temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask;

drivers/gpu/drm/radeon/radeon_i2c.c

146

temp = RREG32(rec->mask_clk_reg);

drivers/gpu/drm/radeon/radeon_i2c.c

148

temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask;

drivers/gpu/drm/radeon/radeon_i2c.c

150

temp = RREG32(rec->mask_data_reg);

drivers/gpu/drm/radeon/radeon_i2c.c

163

temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask;

drivers/gpu/drm/radeon/radeon_i2c.c

165

temp = RREG32(rec->mask_clk_reg);

drivers/gpu/drm/radeon/radeon_i2c.c

167

temp = RREG32(rec->mask_data_reg) & ~rec->mask_data_mask;

drivers/gpu/drm/radeon/radeon_i2c.c

169

temp = RREG32(rec->mask_data_reg);

drivers/gpu/drm/radeon/radeon_i2c.c

182

val = RREG32(rec->y_clk_reg);

drivers/gpu/drm/radeon/radeon_i2c.c

197

val = RREG32(rec->y_data_reg);

drivers/gpu/drm/radeon/radeon_i2c.c

211

val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;

drivers/gpu/drm/radeon/radeon_i2c.c

224

val = RREG32(rec->en_data_reg) & ~rec->en_data_mask;

drivers/gpu/drm/radeon/radeon_i2c.c

346

tmp = RREG32(RADEON_BIOS_6_SCRATCH);

drivers/gpu/drm/radeon/radeon_i2c.c

474

tmp = RREG32(i2c_cntl_0);

drivers/gpu/drm/radeon/radeon_i2c.c

477

tmp = RREG32(i2c_cntl_0);

drivers/gpu/drm/radeon/radeon_i2c.c

506

tmp = RREG32(i2c_cntl_0);

drivers/gpu/drm/radeon/radeon_i2c.c

509

tmp = RREG32(i2c_cntl_0);

drivers/gpu/drm/radeon/radeon_i2c.c

519

p->buf[j] = RREG32(i2c_data) & 0xff;

drivers/gpu/drm/radeon/radeon_i2c.c

534

tmp = RREG32(i2c_cntl_0);

drivers/gpu/drm/radeon/radeon_i2c.c

537

tmp = RREG32(i2c_cntl_0);

drivers/gpu/drm/radeon/radeon_i2c.c

560

tmp = RREG32(RADEON_BIOS_6_SCRATCH);

drivers/gpu/drm/radeon/radeon_i2c.c

593

tmp = RREG32(rec->mask_clk_reg);

drivers/gpu/drm/radeon/radeon_i2c.c

596

tmp = RREG32(rec->mask_clk_reg);

drivers/gpu/drm/radeon/radeon_i2c.c

598

tmp = RREG32(rec->mask_data_reg);

drivers/gpu/drm/radeon/radeon_i2c.c

601

tmp = RREG32(rec->mask_data_reg);

drivers/gpu/drm/radeon/radeon_i2c.c

604

tmp = RREG32(rec->a_clk_reg);

drivers/gpu/drm/radeon/radeon_i2c.c

607

tmp = RREG32(rec->a_clk_reg);

drivers/gpu/drm/radeon/radeon_i2c.c

609

tmp = RREG32(rec->a_data_reg);

drivers/gpu/drm/radeon/radeon_i2c.c

612

tmp = RREG32(rec->a_data_reg);

drivers/gpu/drm/radeon/radeon_i2c.c

615

tmp = RREG32(rec->en_clk_reg);

drivers/gpu/drm/radeon/radeon_i2c.c

618

tmp = RREG32(rec->en_clk_reg);

drivers/gpu/drm/radeon/radeon_i2c.c

620

tmp = RREG32(rec->en_data_reg);

drivers/gpu/drm/radeon/radeon_i2c.c

623

tmp = RREG32(rec->en_data_reg);

drivers/gpu/drm/radeon/radeon_i2c.c

626

tmp = RREG32(RADEON_BIOS_6_SCRATCH);

drivers/gpu/drm/radeon/radeon_i2c.c

628

saved1 = RREG32(AVIVO_DC_I2C_CONTROL1);

drivers/gpu/drm/radeon/radeon_i2c.c

629

saved2 = RREG32(0x494);

drivers/gpu/drm/radeon/radeon_i2c.c

635

if (RREG32(AVIVO_DC_I2C_ARBITRATION) & AVIVO_DC_I2C_SW_CAN_USE_I2C)

drivers/gpu/drm/radeon/radeon_i2c.c

682

tmp = RREG32(AVIVO_DC_I2C_STATUS1);

drivers/gpu/drm/radeon/radeon_i2c.c

685

tmp = RREG32(AVIVO_DC_I2C_STATUS1);

drivers/gpu/drm/radeon/radeon_i2c.c

724

tmp = RREG32(AVIVO_DC_I2C_STATUS1);

drivers/gpu/drm/radeon/radeon_i2c.c

727

tmp = RREG32(AVIVO_DC_I2C_STATUS1);

drivers/gpu/drm/radeon/radeon_i2c.c

738

p->buf[buffer_offset + j] = RREG32(AVIVO_DC_I2C_DATA) & 0xff;

drivers/gpu/drm/radeon/radeon_i2c.c

767

tmp = RREG32(AVIVO_DC_I2C_STATUS1);

drivers/gpu/drm/radeon/radeon_i2c.c

770

tmp = RREG32(AVIVO_DC_I2C_STATUS1);

drivers/gpu/drm/radeon/radeon_i2c.c

797

tmp = RREG32(RADEON_BIOS_6_SCRATCH);

drivers/gpu/drm/radeon/radeon_irq_kms.c

592

u32 tmp = RREG32(reg);

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

528

gen_cntl_val = RREG32(gen_cntl_reg);

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

645

crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0x00718080;

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

665

disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

678

crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0x00718000;

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

68

fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) &

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

696

crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

702

disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

71

fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH) &

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

103

lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1044

fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1047

tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1049

crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1050

tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1163

tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1207

gpiopad_a = RREG32(RADEON_GPIOPAD_A) | 1;

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1208

disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1210

disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1212

fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1215

disp_tv_out_cntl = RREG32(RADEON_DISP_TV_OUT_CNTL);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1220

dac_cntl = RREG32(RADEON_DAC_CNTL);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1225

gpiopad_a = RREG32(RADEON_GPIOPAD_A) & ~1;

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1227

dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~RADEON_DAC2_DAC2_CLK_SEL;

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1253

dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC2_CLK_SEL;

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1309

gpiopad_a = RREG32(RADEON_GPIOPAD_A);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1310

dac_cntl2 = RREG32(RADEON_DAC_CNTL2);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1311

crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1312

dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1313

tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1314

disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1338

RREG32(RADEON_TV_DAC_CNTL);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1349

RREG32(RADEON_TV_DAC_CNTL);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1352

tmp = RREG32(RADEON_TV_DAC_CNTL);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1382

dac_cntl2 = RREG32(RADEON_DAC_CNTL2);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1383

tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1384

tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1385

config_cntl = RREG32(RADEON_CONFIG_CNTL);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1386

tv_pre_dac_mux_cntl = RREG32(RADEON_TV_PRE_DAC_MUX_CNTL);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1418

tmp = RREG32(RADEON_TV_DAC_CNTL);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1448

gpio_monid = RREG32(RADEON_GPIO_MONID);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1449

fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1450

disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1451

crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1452

disp_lin_trans_grph_a = RREG32(RADEON_DISP_LIN_TRANS_GRPH_A);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1453

disp_lin_trans_grph_b = RREG32(RADEON_DISP_LIN_TRANS_GRPH_B);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1454

disp_lin_trans_grph_c = RREG32(RADEON_DISP_LIN_TRANS_GRPH_C);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1455

disp_lin_trans_grph_d = RREG32(RADEON_DISP_LIN_TRANS_GRPH_D);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1456

disp_lin_trans_grph_e = RREG32(RADEON_DISP_LIN_TRANS_GRPH_E);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1457

disp_lin_trans_grph_f = RREG32(RADEON_DISP_LIN_TRANS_GRPH_F);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1458

crtc2_h_total_disp = RREG32(RADEON_CRTC2_H_TOTAL_DISP);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1459

crtc2_v_total_disp = RREG32(RADEON_CRTC2_V_TOTAL_DISP);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1460

crtc2_h_sync_strt_wid = RREG32(RADEON_CRTC2_H_SYNC_STRT_WID);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1461

crtc2_v_sync_strt_wid = RREG32(RADEON_CRTC2_V_SYNC_STRT_WID);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1463

tmp = RREG32(RADEON_GPIO_MONID);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1492

tmp = RREG32(RADEON_GPIO_MONID);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1579

crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1582

gpiopad_a = RREG32(RADEON_GPIOPAD_A);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1583

disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1585

disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1587

crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1589

tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1590

dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1591

dac_cntl2 = RREG32(RADEON_DAC_CNTL2);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1645

if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUT_B)

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1648

if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUTPUT)

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

198

lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

201

lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

208

lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

219

lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

289

backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >>

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

361

backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >>

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

417

backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >>

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

516

uint32_t crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

517

uint32_t dac_cntl = RREG32(RADEON_DAC_CNTL);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

518

uint32_t dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

591

disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

595

dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~(RADEON_DAC2_DAC_CLK_SEL);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

600

disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

605

dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC_CLK_SEL;

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

624

dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

654

crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

655

dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

656

dac_cntl = RREG32(RADEON_DAC_CNTL);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

657

dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

67

lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

696

if (RREG32(RADEON_DAC_CNTL) & RADEON_DAC_CMP_OUTPUT)

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

728

uint32_t fp_gen_cntl = RREG32(RADEON_FP_GEN_CNTL);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

787

tmp = tmds_pll_cntl = RREG32(RADEON_TMDS_PLL_CNTL);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

818

tmds_transmitter_cntl = RREG32(RADEON_TMDS_TRANSMITTER_CNTL) &

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

828

fp_gen_cntl = (RREG32(RADEON_FP_GEN_CNTL) |

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

892

uint32_t fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

95

disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

954

fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

956

fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

98

lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);

drivers/gpu/drm/radeon/radeon_legacy_tv.c

284

WREG32(RADEON_TEST_DEBUG_MUX, (RREG32(RADEON_TEST_DEBUG_MUX) & 0xffff60ff) | 0x100);

drivers/gpu/drm/radeon/radeon_legacy_tv.c

296

WREG32(RADEON_TEST_DEBUG_MUX, RREG32(RADEON_TEST_DEBUG_MUX) & 0xffffe0ff);

drivers/gpu/drm/radeon/radeon_legacy_tv.c

314

tmp = RREG32(RADEON_TV_HOST_RD_WT_CNTL);

drivers/gpu/drm/radeon/radeon_legacy_tv.c

334

tmp = RREG32(RADEON_TV_HOST_RD_WT_CNTL);

drivers/gpu/drm/radeon/radeon_legacy_tv.c

340

return RREG32(RADEON_TV_HOST_READ_DATA);

drivers/gpu/drm/radeon/radeon_legacy_tv.c

612

tmp = RREG32(RADEON_TV_VSCALER_CNTL1);

drivers/gpu/drm/radeon/radeon_legacy_tv.c

654

tv_vscaler_cntl2 = RREG32(RADEON_TV_VSCALER_CNTL2) & 0x00fffff0;

drivers/gpu/drm/radeon/radeon_legacy_tv.c

749

tmp = RREG32(RADEON_TV_DAC_CNTL);

drivers/gpu/drm/radeon/radeon_ring.c

307

ptr = RREG32(ring->rptr_save_reg);

drivers/gpu/drm/radeon/radeon_ring.c

487

rptr_next = RREG32(ring->rptr_save_reg);

drivers/gpu/drm/radeon/radeon_ttm.c

812

value = RREG32(RADEON_MM_DATA);

drivers/gpu/drm/radeon/radeon_uvd.c

1027

if ((RREG32(cg_upll_func_cntl) & mask) == mask)

drivers/gpu/drm/radeon/rs400.c

157

tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;

drivers/gpu/drm/radeon/rs400.c

161

tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;

drivers/gpu/drm/radeon/rs400.c

248

tmp = RREG32(RADEON_MC_STATUS);

drivers/gpu/drm/radeon/rs400.c

277

RREG32(RADEON_MC_STATUS));

drivers/gpu/drm/radeon/rs400.c

291

base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;

drivers/gpu/drm/radeon/rs400.c

305

r = RREG32(RS480_NB_MC_DATA);

drivers/gpu/drm/radeon/rs400.c

328

tmp = RREG32(RADEON_HOST_PATH_CNTL);

drivers/gpu/drm/radeon/rs400.c

330

tmp = RREG32(RADEON_BUS_CNTL);

drivers/gpu/drm/radeon/rs400.c

343

tmp = RREG32(RS690_HDP_FB_LOCATION);

drivers/gpu/drm/radeon/rs400.c

346

tmp = RREG32(RADEON_AGP_BASE);

drivers/gpu/drm/radeon/rs400.c

348

tmp = RREG32(RS480_AGP_BASE_2);

drivers/gpu/drm/radeon/rs400.c

350

tmp = RREG32(RADEON_MC_AGP_LOCATION);

drivers/gpu/drm/radeon/rs400.c

457

rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);

drivers/gpu/drm/radeon/rs400.c

487

RREG32(R_000E40_RBBM_STATUS),

drivers/gpu/drm/radeon/rs400.c

488

RREG32(R_0007C0_CP_STAT));

drivers/gpu/drm/radeon/rs400.c

561

RREG32(R_000E40_RBBM_STATUS),

drivers/gpu/drm/radeon/rs400.c

562

RREG32(R_0007C0_CP_STAT));

drivers/gpu/drm/radeon/rs600.c

1019

rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);

drivers/gpu/drm/radeon/rs600.c

1053

RREG32(R_000E40_RBBM_STATUS),

drivers/gpu/drm/radeon/rs600.c

1054

RREG32(R_0007C0_CP_STAT));

drivers/gpu/drm/radeon/rs600.c

1128

RREG32(R_000E40_RBBM_STATUS),

drivers/gpu/drm/radeon/rs600.c

1129

RREG32(R_0007C0_CP_STAT));

drivers/gpu/drm/radeon/rs600.c

123

u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);

drivers/gpu/drm/radeon/rs600.c

144

if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)

drivers/gpu/drm/radeon/rs600.c

160

return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) &

drivers/gpu/drm/radeon/rs600.c

238

tmp = RREG32(voltage->gpio.reg);

drivers/gpu/drm/radeon/rs600.c

247

tmp = RREG32(voltage->gpio.reg);

drivers/gpu/drm/radeon/rs600.c

333

tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);

drivers/gpu/drm/radeon/rs600.c

351

tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);

drivers/gpu/drm/radeon/rs600.c

366

tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS);

drivers/gpu/drm/radeon/rs600.c

371

tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS);

drivers/gpu/drm/radeon/rs600.c

389

tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);

drivers/gpu/drm/radeon/rs600.c

397

tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);

drivers/gpu/drm/radeon/rs600.c

468

status = RREG32(R_000E40_RBBM_STATUS);

drivers/gpu/drm/radeon/rs600.c

474

status = RREG32(R_000E40_RBBM_STATUS);

drivers/gpu/drm/radeon/rs600.c

478

tmp = RREG32(RADEON_CP_RB_CNTL);

drivers/gpu/drm/radeon/rs600.c

490

RREG32(R_0000F0_RBBM_SOFT_RESET);

drivers/gpu/drm/radeon/rs600.c

494

status = RREG32(R_000E40_RBBM_STATUS);

drivers/gpu/drm/radeon/rs600.c

498

RREG32(R_0000F0_RBBM_SOFT_RESET);

drivers/gpu/drm/radeon/rs600.c

502

status = RREG32(R_000E40_RBBM_STATUS);

drivers/gpu/drm/radeon/rs600.c

506

RREG32(R_0000F0_RBBM_SOFT_RESET);

drivers/gpu/drm/radeon/rs600.c

510

status = RREG32(R_000E40_RBBM_STATUS);

drivers/gpu/drm/radeon/rs600.c

575

tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;

drivers/gpu/drm/radeon/rs600.c

64

if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK)

drivers/gpu/drm/radeon/rs600.c

670

u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) &

drivers/gpu/drm/radeon/rs600.c

672

u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) &

drivers/gpu/drm/radeon/rs600.c

676

hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) &

drivers/gpu/drm/radeon/rs600.c

714

RREG32(R_000040_GEN_INT_CNTL);

drivers/gpu/drm/radeon/rs600.c

721

uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS);

drivers/gpu/drm/radeon/rs600.c

726

rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);

drivers/gpu/drm/radeon/rs600.c

736

tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);

drivers/gpu/drm/radeon/rs600.c

74

pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);

drivers/gpu/drm/radeon/rs600.c

741

tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);

drivers/gpu/drm/radeon/rs600.c

75

pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);

drivers/gpu/drm/radeon/rs600.c

750

rdev->irq.stat_regs.r500.hdmi0_status = RREG32(R_007404_HDMI0_STATUS) &

drivers/gpu/drm/radeon/rs600.c

753

tmp = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL);

drivers/gpu/drm/radeon/rs600.c

768

u32 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) &

drivers/gpu/drm/radeon/rs600.c

839

msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM;

drivers/gpu/drm/radeon/rs600.c

854

return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT);

drivers/gpu/drm/radeon/rs600.c

856

return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT);

drivers/gpu/drm/radeon/rs600.c

887

rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);

drivers/gpu/drm/radeon/rs600.c

919

d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT);

drivers/gpu/drm/radeon/rs600.c

920

d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT);

drivers/gpu/drm/radeon/rs600.c

938

r = RREG32(R_000074_MC_IND_DATA);

drivers/gpu/drm/radeon/rs600.c

98

if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN))

drivers/gpu/drm/radeon/rs690.c

159

rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);

drivers/gpu/drm/radeon/rs690.c

228

tmp = RREG32(R_006520_DC_LB_MEMORY_SPLIT) & C_006520_DC_LB_MEMORY_SPLIT;

drivers/gpu/drm/radeon/rs690.c

658

r = RREG32(R_00007C_MC_DATA);

drivers/gpu/drm/radeon/rs690.c

730

rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);

drivers/gpu/drm/radeon/rs690.c

764

RREG32(R_000E40_RBBM_STATUS),

drivers/gpu/drm/radeon/rs690.c

765

RREG32(R_0007C0_CP_STAT));

drivers/gpu/drm/radeon/rs690.c

840

RREG32(R_000E40_RBBM_STATUS),

drivers/gpu/drm/radeon/rs690.c

841

RREG32(R_0007C0_CP_STAT));

drivers/gpu/drm/radeon/rs780_dpm.c

1007

u32 current_fb_div = RREG32(FVTHROT_STATUS_REG0) & CURRENT_FEEDBACK_DIV_MASK;

drivers/gpu/drm/radeon/rs780_dpm.c

1008

u32 func_cntl = RREG32(CG_SPLL_FUNC_CNTL);

drivers/gpu/drm/radeon/rs780_dpm.c

212

u32 fbdiv = (RREG32(CG_SPLL_FUNC_CNTL) & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;

drivers/gpu/drm/radeon/rs780_dpm.c

985

u32 current_fb_div = RREG32(FVTHROT_STATUS_REG0) & CURRENT_FEEDBACK_DIV_MASK;

drivers/gpu/drm/radeon/rs780_dpm.c

986

u32 func_cntl = RREG32(CG_SPLL_FUNC_CNTL);

drivers/gpu/drm/radeon/rv515.c

138

RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL);

drivers/gpu/drm/radeon/rv515.c

150

gb_pipe_select = RREG32(R400_GB_PIPE_SELECT);

drivers/gpu/drm/radeon/rv515.c

151

tmp = RREG32(R300_DST_PIPE_CONFIG);

drivers/gpu/drm/radeon/rv515.c

203

r = RREG32(MC_IND_DATA);

drivers/gpu/drm/radeon/rv515.c

227

tmp = RREG32(GB_PIPE_SELECT);

drivers/gpu/drm/radeon/rv515.c

229

tmp = RREG32(SU_REG_DEST);

drivers/gpu/drm/radeon/rv515.c

231

tmp = RREG32(GB_TILE_CONFIG);

drivers/gpu/drm/radeon/rv515.c

233

tmp = RREG32(DST_PIPE_CONFIG);

drivers/gpu/drm/radeon/rv515.c

243

tmp = RREG32(0x2140);

drivers/gpu/drm/radeon/rv515.c

246

tmp = RREG32(0x425C);

drivers/gpu/drm/radeon/rv515.c

273

save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL);

drivers/gpu/drm/radeon/rv515.c

274

save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL);

drivers/gpu/drm/radeon/rv515.c

280

crtc_enabled = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN;

drivers/gpu/drm/radeon/rv515.c

283

tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);

drivers/gpu/drm/radeon/rv515.c

301

tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);

drivers/gpu/drm/radeon/rv515.c

316

blackout = RREG32(R700_MC_CITF_CNTL);

drivers/gpu/drm/radeon/rv515.c

318

blackout = RREG32(R600_CITF_CNTL);

drivers/gpu/drm/radeon/rv515.c

336

tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);

drivers/gpu/drm/radeon/rv515.c

341

tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]);

drivers/gpu/drm/radeon/rv515.c

380

tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i]);

drivers/gpu/drm/radeon/rv515.c

386

tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);

drivers/gpu/drm/radeon/rv515.c

391

tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]);

drivers/gpu/drm/radeon/rv515.c

397

tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);

drivers/gpu/drm/radeon/rv515.c

408

tmp = RREG32(R700_MC_CITF_CNTL);

drivers/gpu/drm/radeon/rv515.c

410

tmp = RREG32(R600_CITF_CNTL);

drivers/gpu/drm/radeon/rv515.c

422

tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);

drivers/gpu/drm/radeon/rv515.c

523

rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);

drivers/gpu/drm/radeon/rv515.c

552

RREG32(R_000E40_RBBM_STATUS),

drivers/gpu/drm/radeon/rv515.c

553

RREG32(R_0007C0_CP_STAT));

drivers/gpu/drm/radeon/rv515.c

632

RREG32(R_000E40_RBBM_STATUS),

drivers/gpu/drm/radeon/rv515.c

633

RREG32(R_0007C0_CP_STAT));

drivers/gpu/drm/radeon/rv6xx_dpm.c

1182

u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);

drivers/gpu/drm/radeon/rv6xx_dpm.c

2034

(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK) >>

drivers/gpu/drm/radeon/rv6xx_dpm.c

2059

(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK) >>

drivers/gpu/drm/radeon/rv6xx_dpm.c

2082

(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK) >>

drivers/gpu/drm/radeon/rv6xx_dpm.c

787

tmp = (RREG32(RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;

drivers/gpu/drm/radeon/rv6xx_dpm.c

789

dram_refresh_rate = 1 << ((RREG32(MC_SEQ_RESERVE_M) & 0x3) + 3);

drivers/gpu/drm/radeon/rv730_dpm.c

200

RREG32(CG_SPLL_FUNC_CNTL);

drivers/gpu/drm/radeon/rv730_dpm.c

202

RREG32(CG_SPLL_FUNC_CNTL_2);

drivers/gpu/drm/radeon/rv730_dpm.c

204

RREG32(CG_SPLL_FUNC_CNTL_3);

drivers/gpu/drm/radeon/rv730_dpm.c

206

RREG32(CG_SPLL_SPREAD_SPECTRUM);

drivers/gpu/drm/radeon/rv730_dpm.c

208

RREG32(CG_SPLL_SPREAD_SPECTRUM_2);

drivers/gpu/drm/radeon/rv730_dpm.c

211

RREG32(TCI_MCLK_PWRMGT_CNTL);

drivers/gpu/drm/radeon/rv730_dpm.c

213

RREG32(TCI_DLL_CNTL);

drivers/gpu/drm/radeon/rv730_dpm.c

215

RREG32(CG_MPLL_FUNC_CNTL);

drivers/gpu/drm/radeon/rv730_dpm.c

217

RREG32(CG_MPLL_FUNC_CNTL_2);

drivers/gpu/drm/radeon/rv730_dpm.c

219

RREG32(CG_MPLL_FUNC_CNTL_3);

drivers/gpu/drm/radeon/rv730_dpm.c

221

RREG32(CG_TCI_MPLL_SPREAD_SPECTRUM);

drivers/gpu/drm/radeon/rv730_dpm.c

223

RREG32(CG_TCI_MPLL_SPREAD_SPECTRUM_2);

drivers/gpu/drm/radeon/rv730_dpm.c

400

arb_refresh_rate = RREG32(MC_ARB_RFSH_RATE) &

drivers/gpu/drm/radeon/rv730_dpm.c

409

old_dram_timing = RREG32(MC_ARB_DRAM_TIMING);

drivers/gpu/drm/radeon/rv730_dpm.c

410

old_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);

drivers/gpu/drm/radeon/rv730_dpm.c

416

dram_timing = RREG32(MC_ARB_DRAM_TIMING);

drivers/gpu/drm/radeon/rv730_dpm.c

417

dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);

drivers/gpu/drm/radeon/rv730_dpm.c

426

dram_timing = RREG32(MC_ARB_DRAM_TIMING);

drivers/gpu/drm/radeon/rv730_dpm.c

427

dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);

drivers/gpu/drm/radeon/rv730_dpm.c

436

dram_timing = RREG32(MC_ARB_DRAM_TIMING);

drivers/gpu/drm/radeon/rv730_dpm.c

437

dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);

drivers/gpu/drm/radeon/rv730_dpm.c

479

mc4_io_pad_cntl = RREG32(MC4_IO_DQ_PAD_CNTL_D0_I0);

drivers/gpu/drm/radeon/rv730_dpm.c

485

mc4_io_pad_cntl = RREG32(MC4_IO_QS_PAD_CNTL_D0_I0);

drivers/gpu/drm/radeon/rv730_dpm.c

500

mc4_io_pad_cntl = RREG32(MC4_IO_DQ_PAD_CNTL_D0_I0);

drivers/gpu/drm/radeon/rv730_dpm.c

503

mc4_io_pad_cntl = RREG32(MC4_IO_QS_PAD_CNTL_D0_I0);

drivers/gpu/drm/radeon/rv740_dpm.c

292

RREG32(CG_SPLL_FUNC_CNTL);

drivers/gpu/drm/radeon/rv740_dpm.c

294

RREG32(CG_SPLL_FUNC_CNTL_2);

drivers/gpu/drm/radeon/rv740_dpm.c

296

RREG32(CG_SPLL_FUNC_CNTL_3);

drivers/gpu/drm/radeon/rv740_dpm.c

298

RREG32(CG_SPLL_SPREAD_SPECTRUM);

drivers/gpu/drm/radeon/rv740_dpm.c

300

RREG32(CG_SPLL_SPREAD_SPECTRUM_2);

drivers/gpu/drm/radeon/rv740_dpm.c

303

RREG32(MPLL_AD_FUNC_CNTL);

drivers/gpu/drm/radeon/rv740_dpm.c

305

RREG32(MPLL_AD_FUNC_CNTL_2);

drivers/gpu/drm/radeon/rv740_dpm.c

307

RREG32(MPLL_DQ_FUNC_CNTL);

drivers/gpu/drm/radeon/rv740_dpm.c

309

RREG32(MPLL_DQ_FUNC_CNTL_2);

drivers/gpu/drm/radeon/rv740_dpm.c

311

RREG32(MCLK_PWRMGT_CNTL);

drivers/gpu/drm/radeon/rv740_dpm.c

312

pi->clk_regs.rv770.dll_cntl = RREG32(DLL_CNTL);

drivers/gpu/drm/radeon/rv740_dpm.c

313

pi->clk_regs.rv770.mpll_ss1 = RREG32(MPLL_SS1);

drivers/gpu/drm/radeon/rv740_dpm.c

314

pi->clk_regs.rv770.mpll_ss2 = RREG32(MPLL_SS2);

drivers/gpu/drm/radeon/rv770.c

1022

tmp = RREG32(HDP_DEBUG1);

drivers/gpu/drm/radeon/rv770.c

1106

RREG32(GRBM_SOFT_RESET);

drivers/gpu/drm/radeon/rv770.c

1142

tmp = RREG32(CG_SPLL_FUNC_CNTL_2);

drivers/gpu/drm/radeon/rv770.c

1148

if (RREG32(CG_SPLL_STATUS) & SPLL_CHG_STATUS)

drivers/gpu/drm/radeon/rv770.c

1156

tmp = RREG32(MPLL_CNTL_MODE);

drivers/gpu/drm/radeon/rv770.c

1300

mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);

drivers/gpu/drm/radeon/rv770.c

1302

shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG);

drivers/gpu/drm/radeon/rv770.c

1316

cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;

drivers/gpu/drm/radeon/rv770.c

1338

disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R7XX_MAX_BACKENDS_MASK;

drivers/gpu/drm/radeon/rv770.c

1403

ta_aux_cntl = RREG32(TA_CNTL_AUX);

drivers/gpu/drm/radeon/rv770.c

1406

sx_debug_1 = RREG32(SX_DEBUG_1);

drivers/gpu/drm/radeon/rv770.c

1410

smx_dc_ctl0 = RREG32(SMX_DC_CTL0);

drivers/gpu/drm/radeon/rv770.c

1424

db_debug3 = RREG32(DB_DEBUG3);

drivers/gpu/drm/radeon/rv770.c

1440

db_debug4 = RREG32(DB_DEBUG4);

drivers/gpu/drm/radeon/rv770.c

1480

sq_config = RREG32(SQ_CONFIG);

drivers/gpu/drm/radeon/rv770.c

1593

hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);

drivers/gpu/drm/radeon/rv770.c

1649

tmp = RREG32(MC_ARB_RAMCFG);

drivers/gpu/drm/radeon/rv770.c

1657

tmp = RREG32(MC_SHARED_CHMAP);

drivers/gpu/drm/radeon/rv770.c

1678

rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);

drivers/gpu/drm/radeon/rv770.c

1679

rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);

drivers/gpu/drm/radeon/rv770.c

2065

tmp = RREG32(0x541c);

drivers/gpu/drm/radeon/rv770.c

789

u32 tmp = RREG32(CG_CLKPIN_CNTL);

drivers/gpu/drm/radeon/rv770.c

804

u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);

drivers/gpu/drm/radeon/rv770.c

832

if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)

drivers/gpu/drm/radeon/rv770.c

848

return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) &

drivers/gpu/drm/radeon/rv770.c

855

u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>

drivers/gpu/drm/radeon/rv770_dpm.c

1307

return (u8) ((RREG32(BIOS_SCRATCH_4) >> 16) & 0xff);

drivers/gpu/drm/radeon/rv770_dpm.c

1345

u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);

drivers/gpu/drm/radeon/rv770_dpm.c

140

RREG32(GB_TILING_CONFIG);

drivers/gpu/drm/radeon/rv770_dpm.c

1523

RREG32(CG_SPLL_FUNC_CNTL);

drivers/gpu/drm/radeon/rv770_dpm.c

1525

RREG32(CG_SPLL_FUNC_CNTL_2);

drivers/gpu/drm/radeon/rv770_dpm.c

1527

RREG32(CG_SPLL_FUNC_CNTL_3);

drivers/gpu/drm/radeon/rv770_dpm.c

1529

RREG32(CG_SPLL_SPREAD_SPECTRUM);

drivers/gpu/drm/radeon/rv770_dpm.c

1531

RREG32(CG_SPLL_SPREAD_SPECTRUM_2);

drivers/gpu/drm/radeon/rv770_dpm.c

1533

RREG32(MPLL_AD_FUNC_CNTL);

drivers/gpu/drm/radeon/rv770_dpm.c

1535

RREG32(MPLL_AD_FUNC_CNTL_2);

drivers/gpu/drm/radeon/rv770_dpm.c

1537

RREG32(MPLL_DQ_FUNC_CNTL);

drivers/gpu/drm/radeon/rv770_dpm.c

1539

RREG32(MPLL_DQ_FUNC_CNTL_2);

drivers/gpu/drm/radeon/rv770_dpm.c

1541

RREG32(MCLK_PWRMGT_CNTL);

drivers/gpu/drm/radeon/rv770_dpm.c

1542

pi->clk_regs.rv770.dll_cntl = RREG32(DLL_CNTL);

drivers/gpu/drm/radeon/rv770_dpm.c

1560

RREG32(S0_VID_LOWER_SMIO_CNTL);

drivers/gpu/drm/radeon/rv770_dpm.c

1569

(RREG32(GENERAL_PWRMGT) & SW_SMIO_INDEX_MASK) >> SW_SMIO_INDEX_SHIFT;

drivers/gpu/drm/radeon/rv770_dpm.c

1572

vid_smio_cntl = RREG32(S3_VID_LOWER_SMIO_CNTL);

drivers/gpu/drm/radeon/rv770_dpm.c

1575

vid_smio_cntl = RREG32(S2_VID_LOWER_SMIO_CNTL);

drivers/gpu/drm/radeon/rv770_dpm.c

1578

vid_smio_cntl = RREG32(S1_VID_LOWER_SMIO_CNTL);

drivers/gpu/drm/radeon/rv770_dpm.c

1596

tmp = RREG32(MC_SEQ_MISC0);

drivers/gpu/drm/radeon/rv770_dpm.c

1637

RREG32(GB_TILING_CONFIG);

drivers/gpu/drm/radeon/rv770_dpm.c

1659

if (((RREG32(SMC_MSG) & HOST_SMC_RESP_MASK) >> HOST_SMC_RESP_SHIFT) == 1)

drivers/gpu/drm/radeon/rv770_dpm.c

172

if (RREG32(GENERAL_PWRMGT) & GLOBAL_PWRMGT_EN)

drivers/gpu/drm/radeon/rv770_dpm.c

174

if (RREG32(SCLK_PWRMGT_CNTL) & DYN_GFX_CLK_OFF_EN)

drivers/gpu/drm/radeon/rv770_dpm.c

208

if (RREG32(GENERAL_PWRMGT) & GLOBAL_PWRMGT_EN)

drivers/gpu/drm/radeon/rv770_dpm.c

2473

(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK) >>

drivers/gpu/drm/radeon/rv770_dpm.c

2502

(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK) >>

drivers/gpu/drm/radeon/rv770_dpm.c

2524

(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK) >>

drivers/gpu/drm/radeon/rv770_dpm.c

731

tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;

drivers/gpu/drm/radeon/rv770_dpm.c

733

tmp = RREG32(MC_SEQ_MISC0) & 3;

drivers/gpu/drm/radeon/rv770_dpm.c

881

u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);

drivers/gpu/drm/radeon/rv770_smc.c

323

original_data = RREG32(SMC_SRAM_DATA);

drivers/gpu/drm/radeon/rv770_smc.c

404

tmp = RREG32(SMC_IO);

drivers/gpu/drm/radeon/rv770_smc.c

424

tmp = RREG32(SMC_MSG) & HOST_SMC_RESP_MASK;

drivers/gpu/drm/radeon/rv770_smc.c

431

tmp = RREG32(SMC_MSG) & HOST_SMC_RESP_MASK;

drivers/gpu/drm/radeon/rv770_smc.c

447

if (RREG32(SMC_IO) & SMC_STOP_MODE)

drivers/gpu/drm/radeon/rv770_smc.c

600

*value = RREG32(SMC_SRAM_DATA);

drivers/gpu/drm/radeon/si.c

1300

*val = RREG32(reg);

drivers/gpu/drm/radeon/si.c

1323

tmp = RREG32(CG_CLKPIN_CNTL_2);

drivers/gpu/drm/radeon/si.c

1327

tmp = RREG32(CG_CLKPIN_CNTL);

drivers/gpu/drm/radeon/si.c

1340

temp = (RREG32(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >>

drivers/gpu/drm/radeon/si.c

1603

running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;

drivers/gpu/drm/radeon/si.c

1635

if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0)

drivers/gpu/drm/radeon/si.c

1640

if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1)

drivers/gpu/drm/radeon/si.c

1756

if (((RREG32(MC_SEQ_MISC0) & 0xff000000) >> 24) == 0x58)

drivers/gpu/drm/radeon/si.c

1986

if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &

drivers/gpu/drm/radeon/si.c

2008

u32 tmp = RREG32(MC_SHARED_CHMAP);

drivers/gpu/drm/radeon/si.c

2411

arb_control3 = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);

drivers/gpu/drm/radeon/si.c

2420

tmp = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);

drivers/gpu/drm/radeon/si.c

2958

data = RREG32(CC_GC_SHADER_ARRAY_CONFIG);

drivers/gpu/drm/radeon/si.c

2963

data |= RREG32(GC_USER_SHADER_ARRAY_CONFIG);

drivers/gpu/drm/radeon/si.c

2982

data = RREG32(SPI_STATIC_THREAD_MGMT_3);

drivers/gpu/drm/radeon/si.c

3005

data = RREG32(CC_RB_BACKEND_DISABLE);

drivers/gpu/drm/radeon/si.c

3010

data |= RREG32(GC_USER_RB_BACKEND_DISABLE);

drivers/gpu/drm/radeon/si.c

3184

RREG32(MC_SHARED_CHMAP);

drivers/gpu/drm/radeon/si.c

3185

mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);

drivers/gpu/drm/radeon/si.c

3289

sx_debug_1 = RREG32(SX_DEBUG_1);

drivers/gpu/drm/radeon/si.c

3323

tmp = RREG32(HDP_MISC_CNTL);

drivers/gpu/drm/radeon/si.c

3327

hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);

drivers/gpu/drm/radeon/si.c

3760

tmp = RREG32(GRBM_STATUS);

drivers/gpu/drm/radeon/si.c

3777

tmp = RREG32(GRBM_STATUS2);

drivers/gpu/drm/radeon/si.c

3782

tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET);

drivers/gpu/drm/radeon/si.c

3787

tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET);

drivers/gpu/drm/radeon/si.c

3792

tmp = RREG32(SRBM_STATUS2);

drivers/gpu/drm/radeon/si.c

3800

tmp = RREG32(SRBM_STATUS);

drivers/gpu/drm/radeon/si.c

3822

tmp = RREG32(VM_L2_STATUS);

drivers/gpu/drm/radeon/si.c

3848

RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR));

drivers/gpu/drm/radeon/si.c

3850

RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));

drivers/gpu/drm/radeon/si.c

3864

tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);

drivers/gpu/drm/radeon/si.c

3870

tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);

drivers/gpu/drm/radeon/si.c

3931

tmp = RREG32(GRBM_SOFT_RESET);

drivers/gpu/drm/radeon/si.c

3935

tmp = RREG32(GRBM_SOFT_RESET);

drivers/gpu/drm/radeon/si.c

3941

tmp = RREG32(GRBM_SOFT_RESET);

drivers/gpu/drm/radeon/si.c

3945

tmp = RREG32(SRBM_SOFT_RESET);

drivers/gpu/drm/radeon/si.c

3949

tmp = RREG32(SRBM_SOFT_RESET);

drivers/gpu/drm/radeon/si.c

3955

tmp = RREG32(SRBM_SOFT_RESET);

drivers/gpu/drm/radeon/si.c

3971

tmp = RREG32(CG_SPLL_FUNC_CNTL);

drivers/gpu/drm/radeon/si.c

3975

tmp = RREG32(CG_SPLL_FUNC_CNTL_2);

drivers/gpu/drm/radeon/si.c

3980

if (RREG32(SPLL_STATUS) & SPLL_CHG_STATUS)

drivers/gpu/drm/radeon/si.c

3985

tmp = RREG32(CG_SPLL_FUNC_CNTL_2);

drivers/gpu/drm/radeon/si.c

3989

tmp = RREG32(MPLL_CNTL_MODE);

drivers/gpu/drm/radeon/si.c

3998

tmp = RREG32(SPLL_CNTL_MODE);

drivers/gpu/drm/radeon/si.c

4002

tmp = RREG32(CG_SPLL_FUNC_CNTL);

drivers/gpu/drm/radeon/si.c

4006

tmp = RREG32(CG_SPLL_FUNC_CNTL);

drivers/gpu/drm/radeon/si.c

4010

tmp = RREG32(SPLL_CNTL_MODE);

drivers/gpu/drm/radeon/si.c

4031

tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);

drivers/gpu/drm/radeon/si.c

4035

tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);

drivers/gpu/drm/radeon/si.c

4061

if (RREG32(CONFIG_MEMSIZE) != 0xffffffff)

drivers/gpu/drm/radeon/si.c

4193

tmp = RREG32(MC_ARB_RAMCFG);

drivers/gpu/drm/radeon/si.c

4201

tmp = RREG32(MC_SHARED_CHMAP);

drivers/gpu/drm/radeon/si.c

4237

tmp = RREG32(CONFIG_MEMSIZE);

drivers/gpu/drm/radeon/si.c

4363

rdev->vm_manager.saved_table_addr[i] = RREG32(reg);

drivers/gpu/drm/radeon/si.c

5113

if (RREG32(RLC_SERDES_MASTER_BUSY_0) == 0)

drivers/gpu/drm/radeon/si.c

5119

if (RREG32(RLC_SERDES_MASTER_BUSY_1) == 0)

drivers/gpu/drm/radeon/si.c

5128

u32 tmp = RREG32(CP_INT_CNTL_RING0);

drivers/gpu/drm/radeon/si.c

5140

tmp = RREG32(DB_DEPTH_INFO);

drivers/gpu/drm/radeon/si.c

5144

if ((RREG32(RLC_STAT) & mask) == (GFX_CLOCK_STATUS | GFX_POWER_STATUS))

drivers/gpu/drm/radeon/si.c

5156

tmp = RREG32(UVD_CGC_CTRL);

drivers/gpu/drm/radeon/si.c

5179

u32 tmp = RREG32(UVD_CGC_CTRL);

drivers/gpu/drm/radeon/si.c

5189

orig = data = RREG32(RLC_CNTL);

drivers/gpu/drm/radeon/si.c

5205

tmp = RREG32(RLC_CNTL);

drivers/gpu/drm/radeon/si.c

5214

orig = data = RREG32(DMA_PG);

drivers/gpu/drm/radeon/si.c

5243

tmp = RREG32(RLC_PG_CNTL);

drivers/gpu/drm/radeon/si.c

5247

tmp = RREG32(RLC_AUTO_PG_CTRL);

drivers/gpu/drm/radeon/si.c

5251

tmp = RREG32(RLC_AUTO_PG_CTRL);

drivers/gpu/drm/radeon/si.c

5255

tmp = RREG32(DB_RENDER_CONTROL);

drivers/gpu/drm/radeon/si.c

5265

tmp = RREG32(RLC_PG_CNTL);

drivers/gpu/drm/radeon/si.c

5271

tmp = RREG32(RLC_AUTO_PG_CTRL);

drivers/gpu/drm/radeon/si.c

5285

tmp = RREG32(CC_GC_SHADER_ARRAY_CONFIG);

drivers/gpu/drm/radeon/si.c

5286

tmp1 = RREG32(GC_USER_SHADER_ARRAY_CONFIG);

drivers/gpu/drm/radeon/si.c

5329

tmp = RREG32(RLC_MAX_PG_CU);

drivers/gpu/drm/radeon/si.c

5340

orig = data = RREG32(RLC_CGCG_CGLS_CTRL);

drivers/gpu/drm/radeon/si.c

5363

RREG32(CB_CGTT_SCLK_CTRL);

drivers/gpu/drm/radeon/si.c

5364

RREG32(CB_CGTT_SCLK_CTRL);

drivers/gpu/drm/radeon/si.c

5365

RREG32(CB_CGTT_SCLK_CTRL);

drivers/gpu/drm/radeon/si.c

5366

RREG32(CB_CGTT_SCLK_CTRL);

drivers/gpu/drm/radeon/si.c

5381

orig = data = RREG32(CGTS_SM_CTRL_REG);

drivers/gpu/drm/radeon/si.c

5387

orig = data = RREG32(CP_MEM_SLP_CNTL);

drivers/gpu/drm/radeon/si.c

5393

orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/radeon/si.c

5406

orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE);

drivers/gpu/drm/radeon/si.c

5411

data = RREG32(CP_MEM_SLP_CNTL);

drivers/gpu/drm/radeon/si.c

5416

orig = data = RREG32(CGTS_SM_CTRL_REG);

drivers/gpu/drm/radeon/si.c

5441

orig = data = RREG32(UVD_CGC_CTRL);

drivers/gpu/drm/radeon/si.c

5453

orig = data = RREG32(UVD_CGC_CTRL);

drivers/gpu/drm/radeon/si.c

5483

orig = data = RREG32(mc_cg_registers[i]);

drivers/gpu/drm/radeon/si.c

5500

orig = data = RREG32(mc_cg_registers[i]);

drivers/gpu/drm/radeon/si.c

5522

orig = data = RREG32(DMA_POWER_CNTL + offset);

drivers/gpu/drm/radeon/si.c

5534

orig = data = RREG32(DMA_POWER_CNTL + offset);

drivers/gpu/drm/radeon/si.c

5539

orig = data = RREG32(DMA_CLK_CTRL + offset);

drivers/gpu/drm/radeon/si.c

5570

orig = data = RREG32(HDP_HOST_PATH_CNTL);

drivers/gpu/drm/radeon/si.c

5586

orig = data = RREG32(HDP_MEM_POWER_LS);

drivers/gpu/drm/radeon/si.c

5789

u32 tmp = RREG32(GRBM_SOFT_RESET);

drivers/gpu/drm/radeon/si.c

5822

tmp = RREG32(MC_SEQ_MISC0);

drivers/gpu/drm/radeon/si.c

5832

tmp = RREG32(RLC_LB_CNTL);

drivers/gpu/drm/radeon/si.c

5902

u32 ih_cntl = RREG32(IH_CNTL);

drivers/gpu/drm/radeon/si.c

5903

u32 ih_rb_cntl = RREG32(IH_RB_CNTL);

drivers/gpu/drm/radeon/si.c

5914

u32 ih_rb_cntl = RREG32(IH_RB_CNTL);

drivers/gpu/drm/radeon/si.c

5915

u32 ih_cntl = RREG32(IH_CNTL);

drivers/gpu/drm/radeon/si.c

5933

tmp = RREG32(CP_INT_CNTL_RING0) &

drivers/gpu/drm/radeon/si.c

5938

tmp = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;

drivers/gpu/drm/radeon/si.c

5940

tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;

drivers/gpu/drm/radeon/si.c

5982

interrupt_cntl = RREG32(INTERRUPT_CNTL);

drivers/gpu/drm/radeon/si.c

6051

cp_int_cntl = RREG32(CP_INT_CNTL_RING0) &

drivers/gpu/drm/radeon/si.c

6054

dma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;

drivers/gpu/drm/radeon/si.c

6055

dma_cntl1 = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;

drivers/gpu/drm/radeon/si.c

6057

thermal_int = RREG32(CG_THERMAL_INT) &

drivers/gpu/drm/radeon/si.c

6119

RREG32(SRBM_STATUS);

drivers/gpu/drm/radeon/si.c

6135

disp_int[i] = RREG32(si_disp_int_status[i]);

drivers/gpu/drm/radeon/si.c

6137

grph_int[i] = RREG32(GRPH_INT_STATUS + crtc_offsets[i]);

drivers/gpu/drm/radeon/si.c

6197

wptr = RREG32(IH_RB_WPTR);

drivers/gpu/drm/radeon/si.c

6208

tmp = RREG32(IH_RB_CNTL);

drivers/gpu/drm/radeon/si.c

6343

DRM_ERROR("SRBM_READ_ERROR: 0x%x\n", RREG32(SRBM_READ_ERROR));

drivers/gpu/drm/radeon/si.c

6352

addr = RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR);

drivers/gpu/drm/radeon/si.c

6353

status = RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS);

drivers/gpu/drm/radeon/si.c

6969

clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |

drivers/gpu/drm/radeon/si.c

6970

((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);

drivers/gpu/drm/radeon/si.c

7371

orig = data = RREG32(THM_CLK_CNTL);

drivers/gpu/drm/radeon/si.c

7377

orig = data = RREG32(MISC_CLK_CNTL);

drivers/gpu/drm/radeon/si.c

7383

orig = data = RREG32(CG_CLKPIN_CNTL);

drivers/gpu/drm/radeon/si.c

7388

orig = data = RREG32(CG_CLKPIN_CNTL_2);

drivers/gpu/drm/radeon/si.c

7393

orig = data = RREG32(MPLL_BYPASSCLK_SEL);

drivers/gpu/drm/radeon/si.c

7399

orig = data = RREG32(SPLL_CNTL_MODE);

drivers/gpu/drm/radeon/si_dpm.c

2045

cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK;

drivers/gpu/drm/radeon/si_dpm.c

2606

reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK;

drivers/gpu/drm/radeon/si_dpm.c

2689

data = RREG32(config_regs->offset << 2);

drivers/gpu/drm/radeon/si_dpm.c

3154

tmp = RREG32(MC_SEQ_MISC0);

drivers/gpu/drm/radeon/si_dpm.c

3160

width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32;

drivers/gpu/drm/radeon/si_dpm.c

3162

tmp = RREG32(MC_ARB_RAMCFG);

drivers/gpu/drm/radeon/si_dpm.c

3515

si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);

drivers/gpu/drm/radeon/si_dpm.c

3516

si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);

drivers/gpu/drm/radeon/si_dpm.c

3517

si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);

drivers/gpu/drm/radeon/si_dpm.c

3518

si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);

drivers/gpu/drm/radeon/si_dpm.c

3519

si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);

drivers/gpu/drm/radeon/si_dpm.c

3520

si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);

drivers/gpu/drm/radeon/si_dpm.c

3521

si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);

drivers/gpu/drm/radeon/si_dpm.c

3522

si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);

drivers/gpu/drm/radeon/si_dpm.c

3523

si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);

drivers/gpu/drm/radeon/si_dpm.c

3524

si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);

drivers/gpu/drm/radeon/si_dpm.c

3525

si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);

drivers/gpu/drm/radeon/si_dpm.c

3526

si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);

drivers/gpu/drm/radeon/si_dpm.c

3527

si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);

drivers/gpu/drm/radeon/si_dpm.c

3528

si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);

drivers/gpu/drm/radeon/si_dpm.c

3529

si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);

drivers/gpu/drm/radeon/si_dpm.c

3565

if (RREG32(SMC_RESP_0) == 1)

drivers/gpu/drm/radeon/si_dpm.c

3629

tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);

drivers/gpu/drm/radeon/si_dpm.c

3642

tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);

drivers/gpu/drm/radeon/si_dpm.c

3743

u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);

drivers/gpu/drm/radeon/si_dpm.c

4222

u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;

drivers/gpu/drm/radeon/si_dpm.c

4229

dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3);

drivers/gpu/drm/radeon/si_dpm.c

4250

dram_timing = RREG32(MC_ARB_DRAM_TIMING);

drivers/gpu/drm/radeon/si_dpm.c

4251

dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);

drivers/gpu/drm/radeon/si_dpm.c

4252

burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;

drivers/gpu/drm/radeon/si_dpm.c

4948

(RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&

drivers/gpu/drm/radeon/si_dpm.c

4967

((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))

drivers/gpu/drm/radeon/si_dpm.c

4968

dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;

drivers/gpu/drm/radeon/si_dpm.c

4970

dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;

drivers/gpu/drm/radeon/si_dpm.c

4978

dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;

drivers/gpu/drm/radeon/si_dpm.c

5311

temp_reg = RREG32(MC_PMG_CMD_EMRS);

drivers/gpu/drm/radeon/si_dpm.c

5322

temp_reg = RREG32(MC_PMG_CMD_MRS);

drivers/gpu/drm/radeon/si_dpm.c

5348

temp_reg = RREG32(MC_PMG_CMD_MRS1);

drivers/gpu/drm/radeon/si_dpm.c

5488

WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));

drivers/gpu/drm/radeon/si_dpm.c

5489

WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));

drivers/gpu/drm/radeon/si_dpm.c

5490

WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));

drivers/gpu/drm/radeon/si_dpm.c

5491

WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));

drivers/gpu/drm/radeon/si_dpm.c

5492

WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));

drivers/gpu/drm/radeon/si_dpm.c

5493

WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));

drivers/gpu/drm/radeon/si_dpm.c

5494

WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));

drivers/gpu/drm/radeon/si_dpm.c

5495

WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));

drivers/gpu/drm/radeon/si_dpm.c

5496

WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));

drivers/gpu/drm/radeon/si_dpm.c

5497

WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));

drivers/gpu/drm/radeon/si_dpm.c

5498

WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));

drivers/gpu/drm/radeon/si_dpm.c

5499

WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));

drivers/gpu/drm/radeon/si_dpm.c

5500

WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));

drivers/gpu/drm/radeon/si_dpm.c

5501

WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));

drivers/gpu/drm/radeon/si_dpm.c

5904

u32 thermal_int = RREG32(CG_THERMAL_INT);

drivers/gpu/drm/radeon/si_dpm.c

5957

tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;

drivers/gpu/drm/radeon/si_dpm.c

5959

tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;

drivers/gpu/drm/radeon/si_dpm.c

5964

tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;

drivers/gpu/drm/radeon/si_dpm.c

5968

tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;

drivers/gpu/drm/radeon/si_dpm.c

5989

duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;

drivers/gpu/drm/radeon/si_dpm.c

6033

tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;

drivers/gpu/drm/radeon/si_dpm.c

6088

duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;

drivers/gpu/drm/radeon/si_dpm.c

6089

duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT;

drivers/gpu/drm/radeon/si_dpm.c

6121

duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;

drivers/gpu/drm/radeon/si_dpm.c

6130

tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;

drivers/gpu/drm/radeon/si_dpm.c

6161

tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;

drivers/gpu/drm/radeon/si_dpm.c

6178

tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT;

drivers/gpu/drm/radeon/si_dpm.c

6207

tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK;

drivers/gpu/drm/radeon/si_dpm.c

6223

tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;

drivers/gpu/drm/radeon/si_dpm.c

6227

tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;

drivers/gpu/drm/radeon/si_dpm.c

6247

tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK;

drivers/gpu/drm/radeon/si_dpm.c

6252

tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;

drivers/gpu/drm/radeon/si_dpm.c

7040

(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>

drivers/gpu/drm/radeon/si_dpm.c

7060

(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>

drivers/gpu/drm/radeon/si_dpm.c

7078

(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>

drivers/gpu/drm/radeon/si_smc.c

126

RREG32(CB_CGTT_SCLK_CTRL);

drivers/gpu/drm/radeon/si_smc.c

127

RREG32(CB_CGTT_SCLK_CTRL);

drivers/gpu/drm/radeon/si_smc.c

128

RREG32(CB_CGTT_SCLK_CTRL);

drivers/gpu/drm/radeon/si_smc.c

129

RREG32(CB_CGTT_SCLK_CTRL);

drivers/gpu/drm/radeon/si_smc.c

183

tmp = RREG32(SMC_RESP_0);

drivers/gpu/drm/radeon/si_smc.c

188

tmp = RREG32(SMC_RESP_0);

drivers/gpu/drm/radeon/si_smc.c

291

*value = RREG32(SMC_IND_DATA_0);

drivers/gpu/drm/radeon/si_smc.c

86

original_data = RREG32(SMC_IND_DATA_0);

drivers/gpu/drm/radeon/sumo_dpm.c

106

local0 = RREG32(CG_CGTT_LOCAL_0);

drivers/gpu/drm/radeon/sumo_dpm.c

107

local1 = RREG32(CG_CGTT_LOCAL_1);

drivers/gpu/drm/radeon/sumo_dpm.c

1744

u32 hw_rev = (RREG32(HW_REV) & ATI_REV_ID_MASK) >> ATI_REV_ID_SHIFT;

drivers/gpu/drm/radeon/sumo_dpm.c

1821

(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_INDEX_MASK) >>

drivers/gpu/drm/radeon/sumo_dpm.c

1848

(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_INDEX_MASK) >>

drivers/gpu/drm/radeon/sumo_dpm.c

1876

(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_INDEX_MASK) >>

drivers/gpu/drm/radeon/sumo_dpm.c

278

RREG32(GB_ADDR_CONFIG);

drivers/gpu/drm/radeon/sumo_dpm.c

497

u32 dpm_ctrl = RREG32(CG_SCLK_DPM_CTRL_6);

drivers/gpu/drm/radeon/sumo_dpm.c

511

u32 dpm_ctrl = RREG32(CG_SCLK_DPM_CTRL_11);

drivers/gpu/drm/radeon/sumo_dpm.c

521

u32 voltage_cntl = RREG32(CG_DPM_VOLTAGE_CNTL);

drivers/gpu/drm/radeon/sumo_dpm.c

537

cg_sclk_dpm_ctrl_3 = RREG32(CG_SCLK_DPM_CTRL_3);

drivers/gpu/drm/radeon/sumo_dpm.c

550

u32 ds_en = RREG32(DEEP_SLEEP_CNTL) & ENABLE_DS;

drivers/gpu/drm/radeon/sumo_dpm.c

599

if (RREG32(CG_SCLK_DPM_CTRL_3) & DPM_SCLK_ENABLE)

drivers/gpu/drm/radeon/sumo_dpm.c

629

if (RREG32(CG_SCLK_STATUS) & SCLK_OVERCLK_DETECT)

drivers/gpu/drm/radeon/sumo_dpm.c

640

if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_SCLK_INDEX_MASK) == 0)

drivers/gpu/drm/radeon/sumo_dpm.c

645

if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_INDEX_MASK) == 0)

drivers/gpu/drm/radeon/sumo_dpm.c

738

u32 dpm_ctrl4 = RREG32(CG_SCLK_DPM_CTRL_4);

drivers/gpu/drm/radeon/sumo_dpm.c

800

u32 dpm_ctrl4 = RREG32(CG_SCLK_DPM_CTRL_4);

drivers/gpu/drm/radeon/sumo_dpm.c

875

u32 v = RREG32(DOUT_SCRATCH3);

drivers/gpu/drm/radeon/sumo_dpm.c

889

u32 deep_sleep_cntl = RREG32(DEEP_SLEEP_CNTL);

drivers/gpu/drm/radeon/sumo_dpm.c

890

u32 deep_sleep_cntl2 = RREG32(DEEP_SLEEP_CNTL2);

drivers/gpu/drm/radeon/sumo_dpm.c

927

u32 cg_sclk_dpm_ctrl_5 = RREG32(CG_SCLK_DPM_CTRL_5);

drivers/gpu/drm/radeon/sumo_dpm.c

94

RREG32(GB_ADDR_CONFIG);

drivers/gpu/drm/radeon/sumo_dpm.c

940

u32 cg_sclk_dpm_ctrl_3 = RREG32(CG_SCLK_DPM_CTRL_3);

drivers/gpu/drm/radeon/sumo_dpm.c

969

u32 cg_sclk_dpm_ctrl_4 = RREG32(CG_SCLK_DPM_CTRL_4);

drivers/gpu/drm/radeon/sumo_smc.c

39

if (RREG32(GFX_INT_STATUS) & INT_DONE)

drivers/gpu/drm/radeon/sumo_smc.c

48

if (RREG32(GFX_INT_REQ) & INT_REQ)

drivers/gpu/drm/radeon/sumo_smc.c

54

if (RREG32(GFX_INT_STATUS) & INT_ACK)

drivers/gpu/drm/radeon/sumo_smc.c

60

if (RREG32(GFX_INT_STATUS) & INT_DONE)

drivers/gpu/drm/radeon/trinity_dpm.c

1990

(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_MASK) >>

drivers/gpu/drm/radeon/trinity_dpm.c

2011

(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_MASK) >>

drivers/gpu/drm/radeon/trinity_dpm.c

323

u32 hw_rev = (RREG32(HW_REV) & ATI_REV_ID_MASK) >> ATI_REV_ID_SHIFT;

drivers/gpu/drm/radeon/trinity_dpm.c

403

RREG32(GB_ADDR_CONFIG);

drivers/gpu/drm/radeon/trinity_dpm.c

464

RREG32(GB_ADDR_CONFIG);

drivers/gpu/drm/radeon/trinity_dpm.c

725

if (RREG32(SCLK_PWRMGT_CNTL) & DYNAMIC_PM_EN)

drivers/gpu/drm/radeon/trinity_dpm.c

730

if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & TARGET_STATE_MASK) == 0)

drivers/gpu/drm/radeon/trinity_dpm.c

735

if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_MASK) == 0)

drivers/gpu/drm/radeon/trinity_dpm.c

770

if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_MASK) == 0)

drivers/gpu/drm/radeon/trinity_dpm.c

891

u32 tmp = RREG32(CG_MISC_REG);

drivers/gpu/drm/radeon/trinity_smc.c

117

if ((RREG32(SMC_INT_REQ) & 0xffff) == 1)

drivers/gpu/drm/radeon/trinity_smc.c

36

if (RREG32(SMC_RESP_0) != 0)

drivers/gpu/drm/radeon/trinity_smc.c

40

v = RREG32(SMC_RESP_0);

drivers/gpu/drm/radeon/uvd_v1_0.c

332

status = RREG32(UVD_STATUS);

drivers/gpu/drm/radeon/uvd_v1_0.c

370

ring->wptr = RREG32(UVD_RBC_RB_RPTR);

drivers/gpu/drm/radeon/uvd_v1_0.c

42

return RREG32(UVD_RBC_RB_RPTR);

drivers/gpu/drm/radeon/uvd_v1_0.c

438

tmp = RREG32(UVD_CONTEXT_ID);

drivers/gpu/drm/radeon/uvd_v1_0.c

56

return RREG32(UVD_RBC_RB_WPTR);

drivers/gpu/drm/radeon/vce_v1_0.c

108

tmp = RREG32(VCE_CLOCK_GATING_A);

drivers/gpu/drm/radeon/vce_v1_0.c

112

tmp = RREG32(VCE_UENC_CLOCK_GATING);

drivers/gpu/drm/radeon/vce_v1_0.c

117

tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);

drivers/gpu/drm/radeon/vce_v1_0.c

121

tmp = RREG32(VCE_CLOCK_GATING_A);

drivers/gpu/drm/radeon/vce_v1_0.c

125

tmp = RREG32(VCE_UENC_CLOCK_GATING);

drivers/gpu/drm/radeon/vce_v1_0.c

130

tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);

drivers/gpu/drm/radeon/vce_v1_0.c

140

tmp = RREG32(VCE_CLOCK_GATING_A);

drivers/gpu/drm/radeon/vce_v1_0.c

144

tmp = RREG32(VCE_CLOCK_GATING_B);

drivers/gpu/drm/radeon/vce_v1_0.c

149

tmp = RREG32(VCE_UENC_CLOCK_GATING);

drivers/gpu/drm/radeon/vce_v1_0.c

153

tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);

drivers/gpu/drm/radeon/vce_v1_0.c

258

if (RREG32(VCE_FW_REG_STATUS) & VCE_FW_REG_STATUS_DONE)

drivers/gpu/drm/radeon/vce_v1_0.c

265

if (!(RREG32(VCE_FW_REG_STATUS) & VCE_FW_REG_STATUS_PASS))

drivers/gpu/drm/radeon/vce_v1_0.c

270

if (!(RREG32(VCE_FW_REG_STATUS) & VCE_FW_REG_STATUS_BUSY))

drivers/gpu/drm/radeon/vce_v1_0.c

328

status = RREG32(VCE_STATUS);

drivers/gpu/drm/radeon/vce_v1_0.c

64

return RREG32(VCE_RB_RPTR);

drivers/gpu/drm/radeon/vce_v1_0.c

66

return RREG32(VCE_RB_RPTR2);

drivers/gpu/drm/radeon/vce_v1_0.c

81

return RREG32(VCE_RB_WPTR);

drivers/gpu/drm/radeon/vce_v1_0.c

83

return RREG32(VCE_RB_WPTR2);

drivers/gpu/drm/radeon/vce_v2_0.c

135

tmp = RREG32(VCE_CLOCK_GATING_A);

drivers/gpu/drm/radeon/vce_v2_0.c

141

tmp = RREG32(VCE_UENC_CLOCK_GATING);

drivers/gpu/drm/radeon/vce_v2_0.c

146

tmp = RREG32(VCE_CLOCK_GATING_B);

drivers/gpu/drm/radeon/vce_v2_0.c

44

tmp = RREG32(VCE_CLOCK_GATING_B);

drivers/gpu/drm/radeon/vce_v2_0.c

48

tmp = RREG32(VCE_UENC_CLOCK_GATING);

drivers/gpu/drm/radeon/vce_v2_0.c

52

tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);

drivers/gpu/drm/radeon/vce_v2_0.c

58

tmp = RREG32(VCE_CLOCK_GATING_B);

drivers/gpu/drm/radeon/vce_v2_0.c

63

tmp = RREG32(VCE_UENC_CLOCK_GATING);

drivers/gpu/drm/radeon/vce_v2_0.c

68

tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);

drivers/gpu/drm/radeon/vce_v2_0.c

78

tmp = RREG32(VCE_CLOCK_GATING_B);

drivers/gpu/drm/radeon/vce_v2_0.c

88

orig = tmp = RREG32(VCE_UENC_CLOCK_GATING);

drivers/gpu/drm/radeon/vce_v2_0.c

94

orig = tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);