RK3588_DSU_CLKSEL_CON
.reg = RK3588_DSU_CLKSEL_CON(6 + _offs), \
.reg = RK3588_DSU_CLKSEL_CON(0), \
.reg = RK3588_DSU_CLKSEL_CON(1), \
.reg = RK3588_DSU_CLKSEL_CON(2), \
.reg = RK3588_DSU_CLKSEL_CON(3), \
.core_reg[0] = RK3588_DSU_CLKSEL_CON(6),
.core_reg[1] = RK3588_DSU_CLKSEL_CON(6),
.core_reg[2] = RK3588_DSU_CLKSEL_CON(7),
.core_reg[3] = RK3588_DSU_CLKSEL_CON(7),
.mux_core_reg = RK3588_DSU_CLKSEL_CON(5),
RK3588_DSU_CLKSEL_CON(0), 12, 2, MFLAGS, 0, 5, DFLAGS,
RK3588_DSU_CLKSEL_CON(3), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK3588_DSU_CLKSEL_CON(3), 5, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK3588_DSU_CLKSEL_CON(1), 11, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK3588_DSU_CLKSEL_CON(1), 1, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK3588_DSU_CLKSEL_CON(1), 6, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK3588_DSU_CLKSEL_CON(2), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK3588_DSU_CLKSEL_CON(2), 5, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK3588_DSU_CLKSEL_CON(2), 10, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK3588_DSU_CLKSEL_CON(4), 11, 2, MFLAGS,
RK3588_DSU_CLKSEL_CON(4), 5, 2, MFLAGS, 0, 5, DFLAGS,
RK3588_DSU_CLKSEL_CON(4), 7, 2, MFLAGS,