ROFDM0_TRXPATHENABLE
u1_tmp = rtl_read_byte(rtlpriv, ROFDM0_TRXPATHENABLE);
rtl_write_byte(rtlpriv, ROFDM0_TRXPATHENABLE, u1_tmp);
ROFDM0_TRXPATHENABLE, ROFDM0_TRMUXPAR,
rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x23);
u1_tmp = rtl_read_byte(rtlpriv, ROFDM0_TRXPATHENABLE);
rtl_write_byte(rtlpriv, ROFDM0_TRXPATHENABLE, u1_tmp);
rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0);
RFPGA0_XCD_RFINTERFACESW, ROFDM0_TRXPATHENABLE,
rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600);
RFPGA0_XCD_RFINTERFACESW, ROFDM0_TRXPATHENABLE,
rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600);
rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x11);
rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x33);
rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x00);
rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x13);
rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x23);
rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x33);
RFPGA0_XCD_RFINTERFACESW, ROFDM0_TRXPATHENABLE,
rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600);
RFPGA0_XCD_RFINTERFACESW, ROFDM0_TRXPATHENABLE,
rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600);
rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x11);
rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x33);
rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x00);
ROFDM0_TRXPATHENABLE, ROFDM0_TRMUXPAR,
rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600);
rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
ROFDM0_TRXPATHENABLE,
rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
ROFDM0_TRXPATHENABLE,
rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
path2 = (u8)(rtl92s_phy_query_bb_reg(hw, ROFDM0_TRXPATHENABLE, 0xf));
rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x23);
ROFDM0_TRXPATHENABLE, ROFDM0_TRMUXPAR,