RMWREG32
RMWREG32(base + (ch * 0x1000) + 0x060, 0x1C8, 0x1FF);
RMWREG32(base + (ch * 0x1000) + 0x070, 0x1C8, 0x1FF);
RMWREG32(base + (ch * 0x1000) + 0x060, 0x0, 0xF);
RMWREG32(base + (ch * 0x1000) + 0x070, 0x0, 0xF);
RMWREG32(reg_addr, 0x1, DCORE0_TPC0_EML_CFG_DBG_CNT_DBG_EXIT_MASK);
RMWREG32(mmu_base + MMU_STATIC_MULTI_PAGE_SIZE_OFFSET, 5 /* 64MB */,
RMWREG32(stlb_base + STLB_HOP_CONFIGURATION_OFFSET, 1,
RMWREG32(mmROT0_CPL_QUEUE_AWUSER + offset, asid, MMUBP_ASID_MASK);
RMWREG32(mmROT0_DESC_HBW_ARUSER_LO + offset, asid, MMUBP_ASID_MASK);
RMWREG32(mmROT0_DESC_HBW_AWUSER_LO + offset, asid, MMUBP_ASID_MASK);
RMWREG32(mmPSOC_GLOBAL_CONF_TRACE_AWUSER, ctx->asid, MMUBP_ASID_MASK);
RMWREG32(mmPSOC_GLOBAL_CONF_TRACE_ARUSER, ctx->asid, MMUBP_ASID_MASK);