drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

5473

tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

5516

WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

7861

return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2263

tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2304

WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5309

return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

1922

tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

1963

WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

3915

return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1531

tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1594

WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, RLC_ENABLE_F32, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2910

return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4043

WREG32_FIELD(RLC_CNTL, RLC_ENABLE_F32, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4060

WREG32_FIELD(RLC_CNTL, RLC_ENABLE_F32, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3125

WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3144

WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1524

WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1560

WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL,

drivers/gpu/drm/radeon/cik.c

5810

tmp = RREG32(RLC_CNTL);

drivers/gpu/drm/radeon/cik.c

5812

WREG32(RLC_CNTL, rlc);

drivers/gpu/drm/radeon/cik.c

5819

orig = data = RREG32(RLC_CNTL);

drivers/gpu/drm/radeon/cik.c

5825

WREG32(RLC_CNTL, data);

drivers/gpu/drm/radeon/cik.c

5877

WREG32(RLC_CNTL, 0);

drivers/gpu/drm/radeon/cik.c

5893

WREG32(RLC_CNTL, RLC_ENABLE);

drivers/gpu/drm/radeon/evergreen.c

4383

WREG32(RLC_CNTL, mask);

drivers/gpu/drm/radeon/r600.c

1704

WREG32(RLC_CNTL, 0);

drivers/gpu/drm/radeon/r600.c

1836

WREG32(RLC_CNTL, 0);

drivers/gpu/drm/radeon/r600.c

3543

WREG32(RLC_CNTL, 0);

drivers/gpu/drm/radeon/r600.c

3548

WREG32(RLC_CNTL, RLC_ENABLE);

drivers/gpu/drm/radeon/si.c

5189

orig = data = RREG32(RLC_CNTL);

drivers/gpu/drm/radeon/si.c

5193

WREG32(RLC_CNTL, data);

drivers/gpu/drm/radeon/si.c

5205

tmp = RREG32(RLC_CNTL);

drivers/gpu/drm/radeon/si.c

5207

WREG32(RLC_CNTL, rlc);

drivers/gpu/drm/radeon/si.c

5801

WREG32(RLC_CNTL, 0);

drivers/gpu/drm/radeon/si.c

5810

WREG32(RLC_CNTL, RLC_ENABLE);