B2
func(B2) \
func(B2) \
calib->B2 = be16_to_cpu(data->bmp180_cal_buf[B2]);
x1 = (calib->B2 * (b6 * b6 >> 12)) >> 11;
s16 B2;
u16 B1, u16 B2, u16 B3, u16 B4,
adv7511_wr_and_or(sd, 0x22, 0xe0, B2>>8);
adv7511_wr(sd, 0x23, B2);
sdp_io_write_and_or(sd, 0xea, 0xe0, c->B2 >> 8);
sdp_io_write(sd, 0xeb, c->B2);
IWL_MLD_ENC_EHT_RU(2_2_1, B2);
IWL_MVM_ENC_EHT_RU(2_2_1, B2);
CASE_BTC_SLOT_STR(B2);
ASPEED_PINCTRL_PIN(B2),
SIG_EXPR_LIST_DECL_SINGLE(B2, SD1CD, SD1, SD1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(B2, SCL13, I2C13, I2C13_DESC);
PIN_DECL_2(B2, GPIOC6, SD1CD, SCL13);
FUNC_GROUP_DECL(I2C13, B2, A1);
FUNC_GROUP_DECL(SD1, C4, B3, A2, E5, D4, C3, B2, A1);
SIG_EXPR_LIST_DECL_SINGLE(B2, GPIOT6, GPIOT6, SIG_DESC_SET(SCUA0, 6));
SIG_EXPR_LIST_DECL_SINGLE(B2, RMII2RCLKO, RMII2, RMII2_DESC,
SIG_EXPR_LIST_DECL_SINGLE(B2, RGMII2TXCK, RGMII2);
PIN_DECL_(B2, SIG_EXPR_LIST_PTR(B2, GPIOT6), SIG_EXPR_LIST_PTR(B2, RMII2RCLKO),
SIG_EXPR_LIST_PTR(B2, RGMII2TXCK));
FUNC_GROUP_DECL(RGMII2, B2, B1, A2, B3, D5, D4, C2, C1, C3, D1, D2, E6);
FUNC_GROUP_DECL(RMII2, B2, B1, A2, B3, C2, C3, D1, D2, E6);
ASPEED_PINCTRL_PIN(B2),
ASPEED_SB_PINCONF(PIN_CONFIG_DRIVE_STRENGTH, B2, B2, SCU90, 10),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, B2, D4, SCU90, 14),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, B2, D4, SCU90, 14),
SIG_EXPR_LIST_DECL_SESG(B2, RGMII1RXD0, RGMII1, SIG_DESC_SET(SCU400, 8),
SIG_EXPR_LIST_DECL_SESG(B2, RMII1RXD0, RMII1, SIG_DESC_SET(SCU400, 8),
PIN_DECL_2(B2, GPIO18B0, RGMII1RXD0, RMII1RXD0);
FUNC_GROUP_DECL(RGMII1, C6, D6, D5, A3, C5, E6, B3, A2, B2, B1, C4, E5);
FUNC_GROUP_DECL(RMII1, C6, D6, D5, A3, B3, B2, B1, C4, E5);
ASPEED_PINCTRL_PIN(B2),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, B2, D3, SCU40C, 1),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, B2, D3, SCU40C, 1),
PIC32_PINCTRL_GROUP(18, B2,
u32 B2;
u16 B2;