RK3288_CLKSEL_CON
.reg = RK3288_CLKSEL_CON(0), \
.reg = RK3288_CLKSEL_CON(37), \
.core_reg[0] = RK3288_CLKSEL_CON(0),
RK3288_CLKSEL_CON(4), 8, 2, MFLAGS);
RK3288_CLKSEL_CON(5), 8, 2, MFLAGS);
RK3288_CLKSEL_CON(40), 8, 2, MFLAGS);
RK3288_CLKSEL_CON(13), 8, 2, MFLAGS);
RK3288_CLKSEL_CON(14), 8, 2, MFLAGS);
RK3288_CLKSEL_CON(15), 8, 2, MFLAGS);
RK3288_CLKSEL_CON(16), 8, 2, MFLAGS);
RK3288_CLKSEL_CON(3), 8, 2, MFLAGS);
RK3288_CLKSEL_CON(36), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK3288_CLKSEL_CON(36), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK3288_CLKSEL_CON(36), 8, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK3288_CLKSEL_CON(36), 12, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK3288_CLKSEL_CON(37), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK3288_CLKSEL_CON(0), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK3288_CLKSEL_CON(0), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK3288_CLKSEL_CON(37), 4, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK3288_CLKSEL_CON(37), 9, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK3288_CLKSEL_CON(26), 2, 1, MFLAGS, 0, 2,
RK3288_CLKSEL_CON(1), 15, 1, MFLAGS, 3, 5, DFLAGS),
RK3288_CLKSEL_CON(1), 0, 3, DFLAGS),
RK3288_CLKSEL_CON(1), 12, 3, DFLAGS,
RK3288_CLKSEL_CON(1), 8, 2, DFLAGS, div_hclk_cpu_t,
RK3288_CLKSEL_CON(26), 6, 2, DFLAGS,
RK3288_CLKSEL_CON(4), 15, 1, MFLAGS, 0, 7, DFLAGS,
RK3288_CLKSEL_CON(8), 0,
RK3288_CLKSEL_CON(4), 12, 1, MFLAGS,
RK3288_CLKSEL_CON(5), 15, 1, MFLAGS),
RK3288_CLKSEL_CON(5), 0, 7, DFLAGS,
RK3288_CLKSEL_CON(9), 0,
RK3288_CLKSEL_CON(40), 0, 7, DFLAGS,
RK3288_CLKSEL_CON(41), 0,
RK3288_CLKSEL_CON(32), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3288_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK3288_CLKSEL_CON(31), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3288_CLKSEL_CON(31), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK3288_CLKSEL_CON(30), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3288_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK3288_CLKSEL_CON(27), 0, 2, MFLAGS, 8, 8, DFLAGS,
RK3288_CLKSEL_CON(29), 6, 2, MFLAGS, 8, 8, DFLAGS,
RK3288_CLKSEL_CON(28), 15, 1, MFLAGS,
RK3288_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 6, DFLAGS,
RK3288_CLKSEL_CON(6), 6, 2, MFLAGS, 0, 6, DFLAGS,
RK3288_CLKSEL_CON(6), 14, 2, MFLAGS, 8, 6, DFLAGS,
RK3288_CLKSEL_CON(39), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK3288_CLKSEL_CON(40), 12, 2, DFLAGS),
RK3288_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3288_CLKSEL_CON(42), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK3288_CLKSEL_CON(26), 8, 1, MFLAGS,
RK3288_CLKSEL_CON(26), 15, 1, MFLAGS, 9, 5, DFLAGS),
RK3288_CLKSEL_CON(33), 8, 5, DFLAGS),
RK3288_CLKSEL_CON(33), 0, 5, DFLAGS,
RK3288_CLKSEL_CON(34), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3288_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 5, DFLAGS,
RK3288_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
RK3288_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
RK3288_CLKSEL_CON(25), 7, 1, MFLAGS, 0, 7, DFLAGS,
RK3288_CLKSEL_CON(25), 15, 1, MFLAGS, 8, 7, DFLAGS,
RK3288_CLKSEL_CON(39), 7, 1, MFLAGS, 0, 7, DFLAGS,
RK3288_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 6, DFLAGS,
RK3288_CLKSEL_CON(12), 6, 2, MFLAGS, 0, 6, DFLAGS,
RK3288_CLKSEL_CON(34), 14, 2, MFLAGS, 8, 6, DFLAGS,
RK3288_CLKSEL_CON(12), 14, 2, MFLAGS, 8, 6, DFLAGS,
RK3288_CLKSEL_CON(35), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK3288_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3288_CLKSEL_CON(2), 0, 6, DFLAGS,
RK3288_CLKSEL_CON(24), 8, 8, DFLAGS,
RK3288_CLKSEL_CON(38), 7, 1, MFLAGS, 0, 5, DFLAGS,
RK3288_CLKSEL_CON(38), 15, 1, MFLAGS, 8, 5, DFLAGS,
RK3288_CLKSEL_CON(13), 13, 2, MFLAGS, 0, 7, DFLAGS,
RK3288_CLKSEL_CON(17), 0,
RK3288_CLKSEL_CON(13), 15, 1, MFLAGS),
RK3288_CLKSEL_CON(14), 0, 7, DFLAGS,
RK3288_CLKSEL_CON(18), 0,
RK3288_CLKSEL_CON(15), 0, 7, DFLAGS,
RK3288_CLKSEL_CON(19), 0,
RK3288_CLKSEL_CON(16), 0, 7, DFLAGS,
RK3288_CLKSEL_CON(20), 0,
RK3288_CLKSEL_CON(3), 0, 7, DFLAGS,
RK3288_CLKSEL_CON(7), 0,
RK3288_CLKSEL_CON(21), 0, 2, MFLAGS, 8, 5, DFLAGS,
RK3288_CLKSEL_CON(21), 4, 1, MFLAGS),
RK3288_CLKSEL_CON(22), 0, 1, MFLAGS, 8, 8, DFLAGS,
RK3288_CLKSEL_CON(22), 4, 1, MFLAGS),
RK3288_CLKSEL_CON(22), 7, IFLAGS),
RK3288_CLKSEL_CON(13), 11, 2, MFLAGS,
RK3288_CLKSEL_CON(29), 0, 2, MFLAGS,
RK3288_CLKSEL_CON(11), 8, 6, DFLAGS),
RK3288_CLKSEL_CON(22), 4, 1, MFLAGS),
INVERTER(0, "pclk_vip", "pclk_vip_in", RK3288_CLKSEL_CON(29), 4, IFLAGS),
INVERTER(0, "pclk_isp", "pclk_isp_in", RK3288_CLKSEL_CON(29), 3, IFLAGS),
RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
RK3288_CLKSEL_CON(0),
RK3288_CLKSEL_CON(1),
RK3288_CLKSEL_CON(10),
RK3288_CLKSEL_CON(33),
RK3288_CLKSEL_CON(37),