Symbol: RISCV_IOMMU_QUEUE_INTR_ENABLE
drivers/iommu/riscv/iommu-bits.h
152
#define RISCV_IOMMU_CQCSR_CIE RISCV_IOMMU_QUEUE_INTR_ENABLE
drivers/iommu/riscv/iommu-bits.h
163
#define RISCV_IOMMU_FQCSR_FIE RISCV_IOMMU_QUEUE_INTR_ENABLE
drivers/iommu/riscv/iommu-bits.h
172
#define RISCV_IOMMU_PQCSR_PIE RISCV_IOMMU_QUEUE_INTR_ENABLE
drivers/iommu/riscv/iommu.c
258
RISCV_IOMMU_QUEUE_INTR_ENABLE |