RING_TAIL
ENGINE_READ_FW(engine, RING_TAIL) & TAIL_ADDR);
(ENGINE_READ_FW(engine, RING_TAIL) & TAIL_ADDR))
(ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR))
ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR);
ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR,
intel_uncore_write(uncore, RING_TAIL(base), 0);
RING_TAIL(RENDER_RING_BASE));
ENGINE_WRITE_FW(engine, RING_HEAD, ENGINE_READ_FW(engine, RING_TAIL));
ENGINE_WRITE_FW(engine, RING_TAIL, 0);
ENGINE_WRITE_FW(engine, RING_TAIL, ring->head);
if (ENGINE_READ_FW(engine, RING_HEAD) != ENGINE_READ_FW(engine, RING_TAIL)) {
ENGINE_READ_FW(engine, RING_TAIL),
ENGINE_WRITE_FW(engine, RING_TAIL, ring->tail);
ENGINE_POSTING_READ(engine, RING_TAIL);
ENGINE_READ(engine, RING_TAIL), ring->tail,
ENGINE_READ_FW(engine, RING_TAIL),
ENGINE_READ_FW(engine, RING_TAIL),
ENGINE_WRITE(request->engine, RING_TAIL,
i915_mmio_reg_offset(RING_TAIL(engine->mmio_base)),
*cs++ = i915_mmio_reg_offset(RING_TAIL(engine->mmio_base));
{ RING_TAIL(0), 0, 0, "TAIL" }, \
MMIO_RING_DFH(RING_TAIL, D_ALL, 0, NULL, NULL);
vgpu_vreg_t(vgpu, RING_TAIL(ring_base)) = tail;
ee->tail = ENGINE_READ(engine, RING_TAIL);
tail = ENGINE_READ_FW(engine, RING_TAIL);
MMIO_RING_D(RING_TAIL);
{ RING_TAIL(0), REG_32BIT, 0, 0, 0, "RING_TAIL"}, \