RING_START
ENGINE_READ(engine, RING_START));
ENGINE_READ(engine, RING_START),
intel_uncore_write(uncore, RING_START(base), 0);
ENGINE_WRITE_FW(engine, RING_START, i915_ggtt_offset(ring->vma));
ENGINE_READ(engine, RING_START),
ENGINE_READ_FW(engine, RING_START));
ENGINE_READ_FW(engine, RING_START));
*cs++ = i915_mmio_reg_offset(RING_START(0));
i915_mmio_reg_offset(RING_START(engine->mmio_base)),
*cs++ = i915_mmio_reg_offset(RING_START(engine->mmio_base));
{ RING_START(0), 0, 0, "START" }, \
MMIO_RING_GM(RING_START, D_ALL, NULL, NULL);
vgpu_vreg_t(workload->vgpu, RING_START(workload->engine->mmio_base)) =
ee->start = ENGINE_READ(engine, RING_START);
u32 ring = ENGINE_READ(engine, RING_START);
MMIO_RING_D(RING_START);
{ RING_START(0), REG_64BIT_LOW_DW, 0, 0, 0, NULL}, \