drivers/gpu/drm/i915/gt/gen6_engine_cs.c

427

ENGINE_WRITE(engine, RING_IMR,

drivers/gpu/drm/i915/gt/gen6_engine_cs.c

431

ENGINE_POSTING_READ(engine, RING_IMR);

drivers/gpu/drm/i915/gt/gen6_engine_cs.c

438

ENGINE_WRITE(engine, RING_IMR, ~engine->irq_keep_mask);

drivers/gpu/drm/i915/gt/gen6_engine_cs.c

444

ENGINE_WRITE(engine, RING_IMR, ~engine->irq_enable_mask);

drivers/gpu/drm/i915/gt/gen6_engine_cs.c

447

ENGINE_POSTING_READ(engine, RING_IMR);

drivers/gpu/drm/i915/gt/gen6_engine_cs.c

454

ENGINE_WRITE(engine, RING_IMR, ~0);

drivers/gpu/drm/i915/gt/intel_engine_cs.c

2107

ENGINE_READ(engine, RING_IMR));

drivers/gpu/drm/i915/gt/intel_execlists_submission.c

3258

ENGINE_WRITE(engine, RING_IMR,

drivers/gpu/drm/i915/gt/intel_execlists_submission.c

3260

ENGINE_POSTING_READ(engine, RING_IMR);

drivers/gpu/drm/i915/gt/intel_execlists_submission.c

3265

ENGINE_WRITE(engine, RING_IMR, ~engine->irq_keep_mask);

drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c

393

ret |= GUC_MMIO_REG_ADD(gt, regset, RING_IMR(base), false);

drivers/gpu/drm/i915/gvt/handlers.c

2214

MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

69

MMIO_RING_D(RING_IMR);

drivers/gpu/drm/xe/xe_guc_ads.c

747

{ .reg = RING_IMR(hwe->mmio_base), },

drivers/gpu/drm/xe/xe_guc_capture.c

118

{ RING_IMR(0), REG_32BIT, 0, 0, 0, "RING_IMR"}, \

drivers/gpu/drm/xe/xe_lrc.c

659

regs[CTX_INT_MASK_ENABLE_REG] = RING_IMR(0).addr;