RING_IMR
ENGINE_WRITE(engine, RING_IMR,
ENGINE_POSTING_READ(engine, RING_IMR);
ENGINE_WRITE(engine, RING_IMR, ~engine->irq_keep_mask);
ENGINE_WRITE(engine, RING_IMR, ~engine->irq_enable_mask);
ENGINE_POSTING_READ(engine, RING_IMR);
ENGINE_WRITE(engine, RING_IMR, ~0);
ENGINE_READ(engine, RING_IMR));
ENGINE_WRITE(engine, RING_IMR,
ENGINE_POSTING_READ(engine, RING_IMR);
ENGINE_WRITE(engine, RING_IMR, ~engine->irq_keep_mask);
ret |= GUC_MMIO_REG_ADD(gt, regset, RING_IMR(base), false);
MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
MMIO_RING_D(RING_IMR);
{ .reg = RING_IMR(hwe->mmio_base), },
{ RING_IMR(0), REG_32BIT, 0, 0, 0, "RING_IMR"}, \
regs[CTX_INT_MASK_ENABLE_REG] = RING_IMR(0).addr;