drivers/gpu/drm/i915/gt/intel_workarounds.c

2178

RING_FORCE_TO_NONPRIV(base, i),

drivers/gpu/drm/i915/gt/intel_workarounds.c

2184

RING_FORCE_TO_NONPRIV(base, i),

drivers/gpu/drm/i915/gt/selftest_workarounds.c

157

*cs++ = i915_mmio_reg_offset(RING_FORCE_TO_NONPRIV(base, i));

drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c

410

RING_FORCE_TO_NONPRIV(base, i),

drivers/gpu/drm/i915/gvt/mmio_context.c

100

{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */

drivers/gpu/drm/i915/gvt/mmio_context.c

101

{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */

drivers/gpu/drm/i915/gvt/mmio_context.c

102

{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */

drivers/gpu/drm/i915/gvt/mmio_context.c

103

{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */

drivers/gpu/drm/i915/gvt/mmio_context.c

104

{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */

drivers/gpu/drm/i915/gvt/mmio_context.c

105

{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */

drivers/gpu/drm/i915/gvt/mmio_context.c

106

{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */

drivers/gpu/drm/i915/gvt/mmio_context.c

107

{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */

drivers/gpu/drm/i915/gvt/mmio_context.c

108

{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */

drivers/gpu/drm/i915/gvt/mmio_context.c

109

{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */

drivers/gpu/drm/i915/gvt/mmio_context.c

66

{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */

drivers/gpu/drm/i915/gvt/mmio_context.c

67

{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */

drivers/gpu/drm/i915/gvt/mmio_context.c

68

{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */

drivers/gpu/drm/i915/gvt/mmio_context.c

69

{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */

drivers/gpu/drm/i915/gvt/mmio_context.c

70

{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */

drivers/gpu/drm/i915/gvt/mmio_context.c

71

{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */

drivers/gpu/drm/i915/gvt/mmio_context.c

72

{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */

drivers/gpu/drm/i915/gvt/mmio_context.c

73

{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */

drivers/gpu/drm/i915/gvt/mmio_context.c

74

{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */

drivers/gpu/drm/i915/gvt/mmio_context.c

75

{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */

drivers/gpu/drm/i915/gvt/mmio_context.c

76

{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */

drivers/gpu/drm/i915/gvt/mmio_context.c

77

{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */

drivers/gpu/drm/i915/gvt/mmio_context.c

98

{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */

drivers/gpu/drm/i915/gvt/mmio_context.c

99

{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */

drivers/gpu/drm/xe/xe_reg_whitelist.c

151

.reg = RING_FORCE_TO_NONPRIV(hwe->mmio_base, slot),