drivers/gpu/drm/i915/gt/intel_lrc.c

1276

*cs++ = i915_mmio_reg_offset(RING_CTX_TIMESTAMP(0));

drivers/gpu/drm/i915/gt/intel_lrc.c

1282

*cs++ = i915_mmio_reg_offset(RING_CTX_TIMESTAMP(0));

drivers/gpu/drm/i915/gt/intel_workarounds.c

1998

RING_CTX_TIMESTAMP(engine->mmio_base),

drivers/gpu/drm/i915/gt/selftest_engine_pm.c

103

cs = emit_srm(cs, RING_CTX_TIMESTAMP(engine->mmio_base), offset + 4012);

drivers/gpu/drm/i915/gt/selftest_engine_pm.c

97

cs = emit_srm(cs, RING_CTX_TIMESTAMP(engine->mmio_base), offset + 4004);

drivers/gpu/drm/i915/gt/selftest_lrc.c

350

i915_mmio_reg_offset(RING_CTX_TIMESTAMP(engine->mmio_base)),

drivers/gpu/drm/i915/gt/selftest_lrc.c

769

*cs++ = i915_mmio_reg_offset(RING_CTX_TIMESTAMP(rq->engine->mmio_base));

drivers/gpu/drm/i915/i915_cmd_parser.c

689

REG32_IDX(RING_CTX_TIMESTAMP, BLT_RING_BASE),

drivers/gpu/drm/xe/xe_lrc.c

1116

*cmd++ = RING_CTX_TIMESTAMP(0).addr;

drivers/gpu/drm/xe/xe_lrc.c

1122

*cmd++ = RING_CTX_TIMESTAMP(0).addr;

drivers/gpu/drm/xe/xe_lrc.c

1127

*cmd++ = RING_CTX_TIMESTAMP(0).addr;

drivers/gpu/drm/xe/xe_lrc.c

2401

RING_CTX_TIMESTAMP(hwe->mmio_base));

drivers/gpu/drm/xe/xe_lrc.c

2404

RING_CTX_TIMESTAMP(hwe->mmio_base));

drivers/gpu/drm/xe/xe_reg_whitelist.c

53

XE_RTP_ACTIONS(WHITELIST(RING_CTX_TIMESTAMP(0),

drivers/gpu/drm/xe/xe_ring_ops.c

240

dw[i++] = RING_CTX_TIMESTAMP(0).addr;

drivers/gpu/drm/xe/xe_ring_ops.c

251

dw[i++] = RING_CTX_TIMESTAMP(0).addr;