drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

104

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

105

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, trap_mask_bits);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

106

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE, trap_override);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

117

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, LAUNCH_MODE, wave_launch_mode);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

140

watch_address_cntl = REG_SET_FIELD(watch_address_cntl,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

145

watch_address_cntl = REG_SET_FIELD(watch_address_cntl,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

150

watch_address_cntl = REG_SET_FIELD(watch_address_cntl,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

46

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

47

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, 0);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

48

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE, 0);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

60

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, keep_trap_enabled);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

61

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, 0);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

62

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE, 0);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c

155

data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c

185

data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c

329

data = REG_SET_FIELD(data, SQ_CONFIG, DISABLE_BARRIER_WAITCNT,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

121

data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA_RLC0_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

307

data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

352

REG_SET_FIELD(m->cp_hqd_eop_rptr, CP_HQD_EOP_RPTR, INIT_FETCHER, 1));

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

354

data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

369

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

370

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, 0);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

371

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE, 0);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

415

ret = REG_SET_FIELD(0, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, excp_en);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

416

ret = REG_SET_FIELD(ret, SPI_GDBG_PER_VMID_CNTL, TRAP_ON_START, trap_on_start);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

417

ret = REG_SET_FIELD(ret, SPI_GDBG_PER_VMID_CNTL, TRAP_ON_END, trap_on_end);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

454

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

455

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE, trap_override);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

478

watch_address_cntl = REG_SET_FIELD(watch_address_cntl,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

483

watch_address_cntl = REG_SET_FIELD(watch_address_cntl,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

488

watch_address_cntl = REG_SET_FIELD(watch_address_cntl,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

91

data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA_RLC0_DOORBELL,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

1034

*reg_data = REG_SET_FIELD(*reg_data,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

1039

*reg_data = REG_SET_FIELD(*reg_data,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

232

data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

279

REG_SET_FIELD(m->cp_hqd_eop_rptr,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

282

data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

405

data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

435

data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

688

data = REG_SET_FIELD(data, GRBM_GFX_INDEX,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

690

data = REG_SET_FIELD(data, GRBM_GFX_INDEX,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

692

data = REG_SET_FIELD(data, GRBM_GFX_INDEX,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

741

data = REG_SET_FIELD(data, SPI_GDBG_WAVE_CNTL, STALL_VMID,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

766

data = REG_SET_FIELD(data, SPI_GDBG_TRAP_CONFIG,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

768

data = REG_SET_FIELD(data, SPI_GDBG_TRAP_CONFIG,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

847

data = REG_SET_FIELD(data, SPI_GDBG_TRAP_MASK, EXCP_EN, trap_mask_bits);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

848

data = REG_SET_FIELD(data, SPI_GDBG_TRAP_MASK, REPLACE, trap_override);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

870

data = REG_SET_FIELD(data, SPI_GDBG_WAVE_CNTL2,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

872

data = REG_SET_FIELD(data, SPI_GDBG_WAVE_CNTL2,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

905

tcp_watch_address_cntl = REG_SET_FIELD(tcp_watch_address_cntl,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

909

tcp_watch_address_cntl = REG_SET_FIELD(tcp_watch_address_cntl,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

913

tcp_watch_address_cntl = REG_SET_FIELD(tcp_watch_address_cntl,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

919

sq_watch_address_cntl = REG_SET_FIELD(sq_watch_address_cntl,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

923

sq_watch_address_cntl = REG_SET_FIELD(sq_watch_address_cntl,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

927

sq_watch_address_cntl = REG_SET_FIELD(sq_watch_address_cntl,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

933

tcp_watch_address_cntl = REG_SET_FIELD(tcp_watch_address_cntl,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

941

sq_watch_address_cntl = REG_SET_FIELD(sq_watch_address_cntl,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

965

tcp_watch_address_cntl = REG_SET_FIELD(tcp_watch_address_cntl,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

973

sq_watch_address_cntl = REG_SET_FIELD(sq_watch_address_cntl,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

203

value = REG_SET_FIELD(value, RLC_CP_SCHEDULERS, scheduler1,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

218

data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

265

REG_SET_FIELD(m->cp_hqd_eop_rptr,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

268

data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

391

data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

421

data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

600

data = REG_SET_FIELD(data, GRBM_GFX_INDEX,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

602

data = REG_SET_FIELD(data, GRBM_GFX_INDEX,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

604

data = REG_SET_FIELD(data, GRBM_GFX_INDEX,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

188

value = REG_SET_FIELD(value, RLC_CP_SCHEDULERS, scheduler1,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

203

data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

250

REG_SET_FIELD(m->cp_hqd_eop_rptr,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

253

data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

376

data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_QUEUE0_DOORBELL,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

406

data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_QUEUE0_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

585

data = REG_SET_FIELD(data, GRBM_GFX_INDEX,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

587

data = REG_SET_FIELD(data, GRBM_GFX_INDEX,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

589

data = REG_SET_FIELD(data, GRBM_GFX_INDEX,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

626

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

627

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, 0);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

628

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE, 0);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

640

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

641

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, 0);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

642

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE, 0);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

687

ret = REG_SET_FIELD(0, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, excp_en);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

688

ret = REG_SET_FIELD(ret, SPI_GDBG_PER_VMID_CNTL, TRAP_ON_START, trap_on_start);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

689

ret = REG_SET_FIELD(ret, SPI_GDBG_PER_VMID_CNTL, TRAP_ON_END, trap_on_end);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

723

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

724

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE, trap_override);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

735

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, LAUNCH_MODE, wave_launch_mode);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

757

watch_address_cntl = REG_SET_FIELD(watch_address_cntl,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

762

watch_address_cntl = REG_SET_FIELD(watch_address_cntl,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

767

watch_address_cntl = REG_SET_FIELD(watch_address_cntl,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

174

data = REG_SET_FIELD(data, GRBM_GFX_INDEX,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

176

data = REG_SET_FIELD(data, GRBM_GFX_INDEX,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

178

data = REG_SET_FIELD(data, GRBM_GFX_INDEX,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

194

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

195

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, 0);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

196

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE, 0);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

208

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

209

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, 0);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

210

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE, 0);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

254

ret = REG_SET_FIELD(0, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, excp_en);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

255

ret = REG_SET_FIELD(ret, SPI_GDBG_PER_VMID_CNTL, TRAP_ON_START, trap_on_start);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

256

ret = REG_SET_FIELD(ret, SPI_GDBG_PER_VMID_CNTL, TRAP_ON_END, trap_on_end);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

291

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

292

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE, trap_override);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

306

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, STALL_VMID,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

309

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, LAUNCH_MODE,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

332

watch_address_cntl = REG_SET_FIELD(watch_address_cntl,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

337

watch_address_cntl = REG_SET_FIELD(watch_address_cntl,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c

342

watch_address_cntl = REG_SET_FIELD(watch_address_cntl,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c

177

data = REG_SET_FIELD(data, GRBM_GFX_INDEX,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c

179

data = REG_SET_FIELD(data, GRBM_GFX_INDEX,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c

181

data = REG_SET_FIELD(data, GRBM_GFX_INDEX,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c

197

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c

198

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, 0);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c

199

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE, 0);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c

211

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c

212

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, 0);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c

213

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE, 0);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c

257

ret = REG_SET_FIELD(0, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, excp_en);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c

258

ret = REG_SET_FIELD(ret, SPI_GDBG_PER_VMID_CNTL, TRAP_ON_START, trap_on_start);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c

259

ret = REG_SET_FIELD(ret, SPI_GDBG_PER_VMID_CNTL, TRAP_ON_END, trap_on_end);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c

294

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c

295

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE, trap_override);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c

309

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, STALL_VMID,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c

312

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, LAUNCH_MODE,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c

335

watch_address_cntl = REG_SET_FIELD(watch_address_cntl,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c

340

watch_address_cntl = REG_SET_FIELD(watch_address_cntl,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c

345

watch_address_cntl = REG_SET_FIELD(watch_address_cntl,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

182

data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

196

data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

265

data = REG_SET_FIELD(m->sdma_rlc_doorbell, SDMA0_RLC0_DOORBELL,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

287

data = REG_SET_FIELD(m->sdma_rlc_rb_cntl, SDMA0_RLC0_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

178

value = REG_SET_FIELD(value, RLC_CP_SCHEDULERS, scheduler1,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

206

data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

220

data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

288

data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

310

data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

553

data = REG_SET_FIELD(data, GRBM_GFX_INDEX,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

555

data = REG_SET_FIELD(data, GRBM_GFX_INDEX,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

557

data = REG_SET_FIELD(data, GRBM_GFX_INDEX,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1090

*reg_data = REG_SET_FIELD(*reg_data,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1095

*reg_data = REG_SET_FIELD(*reg_data,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1208

pipe_reset_data = REG_SET_FIELD(pipe_reset_data, CP_MEC_CNTL, MEC_ME1_PIPE0_RESET, 1);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

246

data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

291

REG_SET_FIELD(m->cp_hqd_eop_rptr, CP_HQD_EOP_RPTR, INIT_FETCHER, 1));

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

293

data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

416

data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

446

data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

638

data = REG_SET_FIELD(data, GRBM_GFX_INDEX,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

640

data = REG_SET_FIELD(data, GRBM_GFX_INDEX,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

642

data = REG_SET_FIELD(data, GRBM_GFX_INDEX,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

679

data = REG_SET_FIELD(data, SPI_GDBG_WAVE_CNTL, STALL_VMID,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

682

data = REG_SET_FIELD(data, SPI_GDBG_WAVE_CNTL, STALL_RA,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

781

data = REG_SET_FIELD(data, SPI_GDBG_TRAP_MASK, EXCP_EN, trap_mask_bits);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

782

data = REG_SET_FIELD(data, SPI_GDBG_TRAP_MASK, REPLACE, trap_override);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

804

data = REG_SET_FIELD(data, SPI_GDBG_WAVE_CNTL2,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

806

data = REG_SET_FIELD(data, SPI_GDBG_WAVE_CNTL2,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

835

watch_address_cntl = REG_SET_FIELD(watch_address_cntl,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

839

watch_address_cntl = REG_SET_FIELD(watch_address_cntl,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

843

watch_address_cntl = REG_SET_FIELD(watch_address_cntl,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

849

watch_address_cntl = REG_SET_FIELD(watch_address_cntl,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

867

watch_address_cntl = REG_SET_FIELD(watch_address_cntl,

drivers/gpu/drm/amd/amdgpu/cik.c

1900

perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);

drivers/gpu/drm/amd/amdgpu/cik.c

1901

perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);

drivers/gpu/drm/amd/amdgpu/cik_sdma.c

372

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,

drivers/gpu/drm/amd/amdgpu/cik_sdma.c

381

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,

drivers/gpu/drm/amd/amdgpu/cz_ih.c

121

interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);

drivers/gpu/drm/amd/amdgpu/cz_ih.c

123

interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);

drivers/gpu/drm/amd/amdgpu/cz_ih.c

130

ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/cz_ih.c

131

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);

drivers/gpu/drm/amd/amdgpu/cz_ih.c

132

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);

drivers/gpu/drm/amd/amdgpu/cz_ih.c

135

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/cz_ih.c

149

ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, MC_VMID, 0);

drivers/gpu/drm/amd/amdgpu/cz_ih.c

152

ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, RPTR_REARM, 1);

drivers/gpu/drm/amd/amdgpu/cz_ih.c

212

wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);

drivers/gpu/drm/amd/amdgpu/cz_ih.c

222

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);

drivers/gpu/drm/amd/amdgpu/cz_ih.c

228

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);

drivers/gpu/drm/amd/amdgpu/cz_ih.c

388

srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET,

drivers/gpu/drm/amd/amdgpu/cz_ih.c

65

ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 1);

drivers/gpu/drm/amd/amdgpu/cz_ih.c

66

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/cz_ih.c

84

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/cz_ih.c

85

ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 0);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1126

tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1129

tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1130

tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1133

tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1136

tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1137

tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1220

tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1257

tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1259

tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1262

tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1264

tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1310

tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1313

tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1316

tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1319

tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1389

tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1391

tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1393

tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1405

tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1486

tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1489

tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1493

tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1496

tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1500

tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1503

tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1551

tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1595

tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1607

tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1608

tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1613

tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1614

tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1619

tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1620

tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1628

tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1629

tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1630

tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1635

tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1637

tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1642

tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1647

tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1654

tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1656

tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1661

tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1667

tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1670

tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1672

tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1678

tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1682

tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1686

tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1687

tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1688

tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1689

tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1690

tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1691

tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1719

tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1721

tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1725

tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1730

tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1851

u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1889

fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1890

fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1894

fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1895

fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1897

fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1903

fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1904

fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1906

fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1912

fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1913

fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1915

fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1920

fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1921

fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1923

fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1929

fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1930

fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1932

fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1938

fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1939

fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1941

fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1949

fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1950

fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1952

fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1960

fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1961

fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1962

fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_RED_CROSSBAR, 2);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1963

fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_BLUE_CROSSBAR, 2);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1965

fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1984

fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1985

fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1987

fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1989

fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1990

fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1991

fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1993

fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

1996

fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

2000

fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

2009

tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

2031

tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

2033

tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

2091

tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

2093

tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

2109

tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

2110

tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_OVL_MODE, 0);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

2114

tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

2118

tmp = REG_SET_FIELD(tmp, PRESCALE_OVL_CONTROL, OVL_PRESCALE_BYPASS, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

2122

tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

2123

tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, OVL_INPUT_GAMMA_MODE, 0);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

2151

tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

2152

tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, OVL_DEGAMMA_MODE, 0);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

2153

tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

2157

tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

2158

tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, OVL_GAMUT_REMAP_MODE, 0);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

2162

tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

2163

tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, OVL_REGAMMA_MODE, 0);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

2167

tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

2168

tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_OVL_MODE, 0);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

2177

tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

2277

cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

2279

cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

2290

tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

2306

tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

2307

tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

243

tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

3007

lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

3013

lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

3036

lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

3042

lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

3066

tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

3071

tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

314

tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

316

tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

3216

tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

3231

tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

3246

tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

350

tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

356

tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

360

tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

363

tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

399

tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

451

tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

453

tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

459

tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

461

tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

496

tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

537

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

538

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

539

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

540

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

542

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

543

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

549

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

550

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

551

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

552

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

553

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

555

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

556

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

562

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

563

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

564

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

565

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

566

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

568

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

569

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

629

tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

633

tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1192

REG_SET_FIELD(0, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT,

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1227

tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1229

tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1232

tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1234

tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1277

tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1279

tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1283

tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1286

tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1290

tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1293

tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1471

tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1472

tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1473

tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1488

tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1489

tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE,

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1494

tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1497

tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1501

tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1504

tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1508

tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1511

tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1553

tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1,

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1573

tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE,

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1576

tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE,

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1579

tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE,

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1601

tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1605

tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1609

tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1613

tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1614

tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1615

tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1616

tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1617

tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1618

tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1622

tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, 0xff);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1626

tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1627

tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1631

tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_RESET_FIFO_WHEN_AUDIO_DIS, 1);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1632

tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1645

tmp = REG_SET_FIELD(tmp, HDMI_GC, HDMI_GC_AVMUTE, mute ? 1 : 0);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1659

tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1660

tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1661

tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1662

tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1666

tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1670

tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1674

tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 0);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1675

tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 0);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1676

tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 0);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1677

tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 0);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1681

tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 0);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1696

tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1700

tmp = REG_SET_FIELD(tmp, DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, 1);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1704

tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1705

tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_ATP_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1706

tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_AIP_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

1707

tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

402

tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

404

tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

410

tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

412

tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

454

tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

3848

tmp = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

3850

tmp = REG_SET_FIELD(tmp, CP_VMID_RESET, PIPE0_QUEUES, 1 << queue_id);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

3852

tmp = REG_SET_FIELD(tmp, CP_VMID_RESET, PIPE1_QUEUES, 1 << queue_id);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

5063

data = REG_SET_FIELD(0, GRBM_GFX_INDEX,

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

5066

data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

5070

data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

5073

data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

5076

data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

5079

data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

5187

data = REG_SET_FIELD(0, SPI_GDBG_TRAP_CONFIG,

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

5189

data = REG_SET_FIELD(data, SPI_GDBG_TRAP_CONFIG,

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

5371

tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

5373

tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

5443

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

5445

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

5447

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

5449

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

5482

tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

5900

tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

5937

tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

5974

tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6011

tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6087

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6088

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6089

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6147

tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6168

tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6169

tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6170

tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6171

tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6225

tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6246

tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6247

tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6248

tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6249

tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6302

tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6323

tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6324

tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6325

tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6326

tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6459

tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6472

tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6474

tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6477

tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6491

tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6499

tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6529

tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6530

tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6532

tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6572

tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6573

tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6677

tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6698

tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6699

tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6700

tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6768

tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, priority);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6790

tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6791

tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6792

tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6797

tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6805

tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6827

tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6828

tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6830

tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6837

tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6839

tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6842

tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6937

tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6946

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6948

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6950

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6952

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6955

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6973

tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6983

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6985

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6988

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6990

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6991

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH,

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6993

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

6994

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

7015

tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

7020

tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

7023

tmp = REG_SET_FIELD(0, CP_HQD_QUANTUM, QUANTUM_EN, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

7024

tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_SCALE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

7025

tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_DURATION, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

7655

grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

7658

grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

7664

grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

7680

grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

7687

grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

9077

cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

9083

cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

9130

mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

9136

mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

9244

cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

9258

cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

9290

cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

9304

cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

9335

cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

9429

tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

9434

tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

9439

tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

9444

tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

9537

tmp = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

9539

tmp = REG_SET_FIELD(tmp, CP_VMID_RESET, PIPE0_QUEUES, 1 << ring->queue);

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

9541

tmp = REG_SET_FIELD(tmp, CP_VMID_RESET, PIPE1_QUEUES, 1 << ring->queue);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2002

data = REG_SET_FIELD(0, GRBM_GFX_INDEX,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2005

data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2009

data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2012

data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2015

data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2018

data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2120

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2198

tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2200

tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2269

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2271

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2273

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2275

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2300

tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2416

tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, PDEBUG_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2417

tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2446

tmp = REG_SET_FIELD(tmp, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2465

tmp = REG_SET_FIELD(tmp, RLC_GPU_IOV_F32_CNTL, ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2544

tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2565

tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2566

tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2567

tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2568

tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2588

tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2609

tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2610

tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2611

tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2612

tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2632

tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2654

tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2655

tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2656

tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2684

tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2685

tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2686

tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2709

tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2740

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2743

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2749

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2752

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2765

tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2766

tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2771

tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2806

tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2807

tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2808

tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2831

tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2863

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2866

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2872

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2875

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2888

tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2889

tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2894

tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2924

tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2925

tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2926

tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2930

tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2931

tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2957

tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2976

tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3023

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3024

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3028

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3029

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3045

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3046

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3050

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3051

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3067

tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3068

tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3069

tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3070

tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3074

tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3075

tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3076

tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3077

tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3171

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3172

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3299

tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3300

tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3301

tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3324

tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3355

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3358

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3364

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3367

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3380

tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3381

tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3386

tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3517

tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3518

tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3519

tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3542

tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3574

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3577

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3583

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3586

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3599

tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3600

tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3605

tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3736

tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3748

tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3750

tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3753

tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3758

tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3786

tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3787

tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3826

tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3827

tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3872

data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_INVALIDATE_ICACHE,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3874

data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3876

data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3878

data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3880

data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3882

data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_ACTIVE,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3884

data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_ACTIVE,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3886

data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_ACTIVE,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3888

data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_ACTIVE,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3890

data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_HALT,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3897

data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3899

data = REG_SET_FIELD(data, CP_MEC_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3902

data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

3903

data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME2_HALT, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4022

tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4023

tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4024

tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4028

tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4029

tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4055

tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4074

tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4135

tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, priority);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4157

tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4158

tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4159

tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4164

tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4172

tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4194

tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4195

tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4197

tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4200

tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, TMZ_MATCH, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4202

tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_NON_PRIV, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4208

tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4210

tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4213

tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4333

tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4342

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4344

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4346

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4348

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4351

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4369

tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4379

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4381

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4383

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4384

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4387

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4388

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4391

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TMZ, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4409

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4412

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4414

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4416

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4429

tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4434

tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4441

tmp = REG_SET_FIELD(0, CP_HQD_QUANTUM, QUANTUM_EN, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4442

tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_SCALE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4443

tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_DURATION, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4770

tmp = REG_SET_FIELD(tmp, CP_GFX_CNTL, ENGINE_SEL, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

4774

tmp = REG_SET_FIELD(tmp, CP_MEC_ISA_CNTL, ISA_MODE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5115

tmp = REG_SET_FIELD(0, CP_GFX_INDEX_MUTEX, REQUEST, req);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5116

tmp = REG_SET_FIELD(tmp, CP_GFX_INDEX_MUTEX, CLIENTID, 4);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5124

tmp = REG_SET_FIELD(tmp, CP_GFX_INDEX_MUTEX,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5150

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5151

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5152

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5153

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5217

grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5219

grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5221

grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5223

grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5225

grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5230

grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5232

grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5234

grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5236

grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5238

grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5243

tmp = REG_SET_FIELD(tmp, CP_SOFT_RESET_CNTL, CMP_HQD_REG_RESET, 0x1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5260

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5261

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5262

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5263

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5626

data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5627

data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5628

data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5629

data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5633

data = REG_SET_FIELD(data, SDMA0_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

5639

data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

6419

cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

6421

cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

6427

cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

6429

cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

6476

mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

6478

mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

6484

mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

6486

mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

6602

cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

6616

cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

6648

cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

6662

cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

6693

cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

6798

tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

6803

tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

6808

tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

6813

tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

6872

reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

6874

reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

6876

clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

6878

clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

6882

reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

6884

reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

6886

clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

6888

clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

6969

reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

6971

clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

6975

reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

6977

clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

6981

reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

6983

clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

6987

reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

6989

clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

7003

reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

7005

clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

7009

reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

7011

clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

7015

reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

7017

clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

7021

reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

7023

clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

7033

reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

7035

clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

7039

reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

7041

clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

7045

reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

7047

clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

7051

reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

7053

clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

1353

data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD0_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

1354

data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

1680

data = REG_SET_FIELD(0, GRBM_GFX_INDEX,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

1683

data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

1687

data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

1690

data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

1693

data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

1696

data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

1797

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

1834

tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

1836

tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

1898

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

1900

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

1902

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

1904

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

1929

tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2045

tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, PDEBUG_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2046

tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2143

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2144

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2148

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2149

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2165

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2166

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2170

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2171

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2187

tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2188

tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2189

tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2190

tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2194

tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2195

tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2196

tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2197

tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2223

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2226

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2232

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2235

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2265

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2268

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2274

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2277

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2344

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2345

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2423

tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2424

tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2425

tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2448

tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2477

tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2478

tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2483

tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2567

tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2568

tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2569

tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2592

tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2622

tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2623

tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2628

tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2692

tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2704

tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2706

tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2709

tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2714

tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2742

tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2743

tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2790

data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_INVALIDATE_ICACHE,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2792

data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2794

data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2796

data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2798

data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2800

data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_ACTIVE,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2802

data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_ACTIVE,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2804

data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_ACTIVE,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2806

data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_ACTIVE,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2808

data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_HALT,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2877

tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2878

tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2879

tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2883

tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2884

tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2908

tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2927

tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2994

tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2995

tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

2996

tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

3001

tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

3007

tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

3012

tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

3034

tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

3035

tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

3037

tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

3040

tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, TMZ_MATCH, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

3042

tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_NON_PRIV, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

3048

tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

3050

tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

3053

tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

3171

tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

3180

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

3182

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

3184

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

3186

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

3189

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

3207

tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

3217

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

3219

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

3221

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

3222

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

3224

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

3225

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

3228

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TMZ, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

3246

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

3249

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

3251

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

3253

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

3266

tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

3271

tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

3278

tmp = REG_SET_FIELD(0, CP_HQD_QUANTUM, QUANTUM_EN, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

3279

tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_SCALE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

3280

tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_DURATION, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

4198

data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

4199

data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

4200

data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

4201

data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

4205

data = REG_SET_FIELD(data, SDMA0_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

4211

data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

4742

cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

4744

cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

4750

cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

4752

cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

4793

mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

4795

mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

4801

mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

4803

mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

4919

cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

4933

cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

4965

cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

4979

cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

5010

cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

5286

reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

5288

reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

5290

clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

5292

clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

5296

reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

5298

reset_pipe = REG_SET_FIELD(reset_pipe, CP_ME_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

5300

clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

5302

clean_pipe = REG_SET_FIELD(clean_pipe, CP_ME_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

5381

reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

5383

clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

5387

reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

5389

clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

5393

reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

5395

clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

5399

reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_RS64_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

5401

clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_RS64_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

5414

reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

5416

clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

5420

reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

5422

clean_pipe = REG_SET_FIELD(clean_pipe, CP_MEC_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1143

data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD0_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1144

data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1336

data = REG_SET_FIELD(0, GRBM_GFX_INDEX,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1339

data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1343

data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1346

data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1349

data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1352

data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1443

sh_mem_bases = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1445

sh_mem_bases = REG_SET_FIELD(sh_mem_bases, SH_MEM_BASES, SHARED_BASE,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1457

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1462

data = REG_SET_FIELD(data, SQ_DEBUG, DISABLE_VGPR_DEALLOC, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1506

tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1508

tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1547

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1549

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1551

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1553

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1579

tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1738

tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, PDEBUG_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1739

tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1847

tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1848

tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1849

tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1850

tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1854

tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1855

tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1856

tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1857

tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1943

data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_INVALIDATE_ICACHE,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1945

data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1947

data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1949

data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1951

data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1953

data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_ACTIVE,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1955

data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_ACTIVE,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1957

data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_ACTIVE,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1959

data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_ACTIVE,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

1961

data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_HALT,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2055

tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2056

tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2057

tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2061

tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2062

tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2088

tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2107

tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2183

tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2192

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2194

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2196

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2198

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2201

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2219

tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2229

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2231

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2233

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2234

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2235

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2236

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2254

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2257

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2259

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2261

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2274

tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x63);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2279

tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2289

tmp = REG_SET_FIELD(0, CP_HQD_QUANTUM, QUANTUM_EN, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2290

tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_SCALE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2291

tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_DURATION, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2701

data = REG_SET_FIELD(data, TCP_UTCL0_CNTL1, ATOMIC_REQUESTER_EN, 0x1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2719

data = REG_SET_FIELD(data, TCP_CNTL3, DISABLE_EARLY_WRITE_ACK, 0x1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

2730

data = REG_SET_FIELD(data, TCP_CNTL, TCP_SPILL_CACHE_DISABLE, 0x1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3193

data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3194

data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3195

data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3196

data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3647

mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3649

mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3655

mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

3657

mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

1310

data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

1312

data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

1630

tcp_addr_config = REG_SET_FIELD(RREG32(mmTCP_ADDR_CONFIG),

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1565

data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1567

data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1923

sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1925

sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, DEFAULT_MTYPE,

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1927

sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, APE1_MTYPE,

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1929

sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, PRIVATE_ATC, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1931

sh_static_mem_cfg = REG_SET_FIELD(0, SH_STATIC_MEM_CONFIG,

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1933

sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

1935

sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

2012

tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS0, 2);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

2013

tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS1, 2);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

2014

tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS2, 2);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

2015

tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS3, 2);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

2928

tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_EN, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

2929

tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_SCALE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

2930

tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_DURATION, 10);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

2951

tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

4003

value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

4004

value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

4005

value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

4006

value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

1546

REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

1572

REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

1598

REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

1618

tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, DED_MODE, 2);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

1619

tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, PROP_FED, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

1623

tmp = REG_SET_FIELD(tmp, CC_GC_EDC_CONFIG, DIS_EDC, 0) | 1;

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

1832

gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

1835

gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

1838

gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 2);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

3394

data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

3396

data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

3399

data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

3401

data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

3404

data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

3406

data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

3739

sh_static_mem_cfg = REG_SET_FIELD(0, SH_STATIC_MEM_CONFIG,

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

3741

sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

3743

sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

3752

tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_UC);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

3753

tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

3754

tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

3759

tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_NC);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

3760

tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

3761

tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

3795

tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS0, 2);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

3796

tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS1, 2);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

3797

tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS2, 2);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

3798

tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS3, 2);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

3848

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

3849

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

3850

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

3851

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

3992

data = REG_SET_FIELD(0, RLC_PG_DELAY, POWER_UP_DELAY, 0x10);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

3993

data = REG_SET_FIELD(data, RLC_PG_DELAY, POWER_DOWN_DELAY, 0x10);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

3994

data = REG_SET_FIELD(data, RLC_PG_DELAY, CMD_PROPAGATE_DELAY, 0x10);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

3995

data = REG_SET_FIELD(data, RLC_PG_DELAY, MEM_SLEEP_DELAY, 0x10);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4089

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4090

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4091

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4093

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4094

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4095

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4203

tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4205

tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4207

tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4210

tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4218

tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4243

tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4244

tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4245

tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MTYPE, 3);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4246

tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MIN_IB_AVAILSZ, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4248

tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4423

tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4429

tmp = REG_SET_FIELD(RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL),

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4442

tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4452

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4454

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4457

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4459

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4460

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4461

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4462

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4480

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4483

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4485

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4487

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4502

tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4507

tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4508

tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MTYPE, 3);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4512

tmp = REG_SET_FIELD(tmp, CP_HQD_IQ_TIMER, MTYPE, 3);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4516

tmp = REG_SET_FIELD(tmp, CP_HQD_CTX_SAVE_CONTROL, MTYPE, 3);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4536

tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_EN, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4537

tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_SCALE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4538

tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_DURATION, 10);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4909

grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4911

grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4913

srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4920

grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4926

grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4928

grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4930

grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4932

srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET,

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4939

srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

4942

srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

5012

tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_STALL, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

5013

tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_CLEAR, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

5048

tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_STALL, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

5049

tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_CLEAR, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

6379

value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

6380

value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

6381

value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

6382

value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

1732

data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

1733

data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

1734

data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

1751

data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

1752

data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

1781

data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

1782

data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

1783

data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

1800

data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

1801

data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

2508

data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

2510

data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

2513

data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

2515

data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

2518

data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

2520

data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

2577

data = REG_SET_FIELD(0, SPI_GDBG_TRAP_CONFIG,

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

2579

data = REG_SET_FIELD(data, SPI_GDBG_TRAP_CONFIG,

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

2652

tmp = REG_SET_FIELD(tmp, SQ_CONFIG, DISABLE_BARRIER_WAITCNT,

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

2688

tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

2690

tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE,

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

2695

tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

2697

tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE,

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

2700

tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

2702

tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

2763

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

2764

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

2765

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

2767

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3004

data = REG_SET_FIELD(data, RLC_PG_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3018

data = REG_SET_FIELD(data, RLC_PG_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3032

data = REG_SET_FIELD(data, RLC_PG_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3045

data = REG_SET_FIELD(data, RLC_PG_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3058

data = REG_SET_FIELD(data, RLC_PG_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3075

data = REG_SET_FIELD(data, RLC_PG_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3088

data = REG_SET_FIELD(data, RLC_PG_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3249

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_INVALIDATE_ICACHE, enable ? 0 : 1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3250

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_INVALIDATE_ICACHE, enable ? 0 : 1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3251

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_INVALIDATE_ICACHE, enable ? 0 : 1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3252

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_PIPE0_RESET, enable ? 0 : 1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3253

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_PIPE1_RESET, enable ? 0 : 1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3254

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, enable ? 0 : 1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3255

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, enable ? 0 : 1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3256

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, enable ? 0 : 1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3257

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, enable ? 0 : 1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3258

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3259

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3260

tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3408

tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3409

tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3411

tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3438

tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3440

tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3443

tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3447

tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3500

tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3501

tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3581

tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3590

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3592

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3594

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3596

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3599

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3618

tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3628

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3630

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3633

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3635

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3636

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3637

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3638

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3660

tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3665

tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3671

tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_EN, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3672

tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_SCALE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

3673

tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_DURATION, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

4010

tmp = REG_SET_FIELD(tmp, TCP_ADDR_CONFIG, ENABLE64KHASH,

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

4012

tmp = REG_SET_FIELD(tmp, TCP_ADDR_CONFIG, ENABLE2MHASH,

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

4014

tmp = REG_SET_FIELD(tmp, TCP_ADDR_CONFIG, ENABLE1GHASH,

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

4211

grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

4213

grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

4218

grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

4225

grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

4772

REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

4800

REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

4828

REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

5989

value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

5990

value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

5991

value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

5992

value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

6051

mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

6057

mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

6112

cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

6148

cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

7263

tmp = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c

101

data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c

105

data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c

108

data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c

111

data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c

114

data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c

98

data = REG_SET_FIELD(0, GRBM_GFX_INDEX,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c

1425

REG_SET_FIELD(0, VML2_MEM_ECC_CNTL, WRITE_COUNTERS, 1) },

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c

1431

REG_SET_FIELD(0, VML2_WALKER_MEM_ECC_CNTL, WRITE_COUNTERS, 1) },

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c

1437

REG_SET_FIELD(0, UTCL2_MEM_ECC_CNTL, WRITE_COUNTERS, 1) },

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c

1443

REG_SET_FIELD(0, ATC_L2_CACHE_2M_DSM_CNTL, WRITE_COUNTERS, 1) },

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c

1449

REG_SET_FIELD(0, ATC_L2_CACHE_32K_DSM_CNTL, WRITE_COUNTERS, 1) },

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c

1455

REG_SET_FIELD(0, ATC_L2_CACHE_4K_DSM_CNTL, WRITE_COUNTERS, 1) },

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c

1698

value = REG_SET_FIELD(value, GCEA_ERR_STATUS, CLEAR_ERROR_STATUS, 0x1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c

1736

reg_value = REG_SET_FIELD(reg_value, GCEA_ERR_STATUS,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c

1794

data = REG_SET_FIELD(0, SQ_TIMEOUT_CONFIG, TIMEOUT_FATAL_DISABLE,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c

1804

data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, PERIOD_SEL,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c

409

REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c

758

data = REG_SET_FIELD(data, SQ_CONFIG1, DISABLE_XNACK_CHECK_IN_RETRY_DISABLE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c

775

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c

776

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c

777

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c

796

tmp = REG_SET_FIELD(tmp, GC_THROTTLE_CTRL, PATTERN_MODE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c

800

tmp = REG_SET_FIELD(tmp, GC_THROTTLE_CTRL1, PWRBRK_STALL_EN, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c

805

tmp = REG_SET_FIELD(tmp, PWRBRK_STALL_PATTERN_CTRL, PWRBRK_END_STEP, 0x12);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c

865

data = REG_SET_FIELD(0, GRBM_GFX_INDEX,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c

868

data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c

872

data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c

875

data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c

878

data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c

881

data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1245

data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1293

data = REG_SET_FIELD(data, SQ_CONFIG1, DISABLE_XNACK_CHECK_IN_RETRY_DISABLE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1310

tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1312

tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1319

tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1321

tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1325

tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1328

tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1515

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1516

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1517

tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1774

tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1775

tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1854

tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1863

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1865

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1867

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1869

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1872

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1875

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1894

tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1904

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1906

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1909

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1911

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1912

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1913

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1914

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1936

tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1941

tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1947

tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_EN, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1948

tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_SCALE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

1949

tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_DURATION, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2539

grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2541

grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2546

grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

2553

grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

3126

value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

3127

value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

3128

value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

3129

value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

3173

mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

3179

mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

3236

mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

3276

mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

3594

reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

3598

reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

3602

reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

3606

reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

3614

reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

3617

reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

4588

data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, TIMEOUT_FATAL_DISABLE,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

4597

data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, PERIOD_SEL,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

5030

tmp = REG_SET_FIELD(tmp, CP_CPC_DEBUG, CPC_HARVESTING_RELAUNCH_DISABLE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

5031

tmp = REG_SET_FIELD(tmp, CP_CPC_DEBUG, CPC_HARVESTING_DISPATCH_DISABLE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

695

data = REG_SET_FIELD(0, GRBM_GFX_INDEX,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

698

data = REG_SET_FIELD(0, GRBM_GFX_INDEX,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

702

data = REG_SET_FIELD(data, GRBM_GFX_INDEX,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

705

data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

708

data = REG_SET_FIELD(data, GRBM_GFX_INDEX,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

711

data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

813

tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, NUM_XCC_IN_XCP,

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

815

tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, VIRTUAL_XCC_ID,

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

194

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

195

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

196

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

198

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

200

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

201

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

219

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

220

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

221

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

224

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

226

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

227

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

228

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

232

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

233

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

238

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12);

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

239

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

242

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9);

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

243

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

249

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

250

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

254

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

263

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

264

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

265

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

301

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

302

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

304

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

306

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

308

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

310

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

312

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

314

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

316

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

318

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

322

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

396

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

397

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

419

tmp = REG_SET_FIELD(tmp, CP_DEBUG, CPG_UTCL1_ERROR_HALT_DISABLE, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

429

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

431

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

433

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

435

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

437

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

440

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

442

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

444

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

446

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

448

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

450

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

452

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

454

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

65

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

67

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

68

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

69

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

70

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

71

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

72

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

73

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

199

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

200

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

201

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

203

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

205

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

206

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

224

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

225

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

226

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

229

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

231

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

232

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

233

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

237

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

238

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

243

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

244

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

247

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

248

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

254

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

255

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

259

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

268

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

269

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

270

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

306

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

307

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

309

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

311

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

313

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

315

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

317

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

319

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

321

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

323

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

327

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

401

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

402

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

424

tmp = REG_SET_FIELD(tmp, CP_DEBUG, CPG_UTCL1_ERROR_HALT_DISABLE, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

434

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

436

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

438

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

440

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

442

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

445

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

447

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

449

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

451

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

453

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

455

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

457

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

459

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

67

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

69

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

70

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

71

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

72

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

73

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

74

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

75

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

243

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL2,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

245

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL2,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

263

tmp = REG_SET_FIELD(tmp,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

266

tmp = REG_SET_FIELD(tmp,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

269

tmp = REG_SET_FIELD(tmp,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

272

tmp = REG_SET_FIELD(tmp,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

275

tmp = REG_SET_FIELD(tmp,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

278

tmp = REG_SET_FIELD(tmp,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

296

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

299

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

301

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

303

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

305

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

307

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

309

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

315

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

317

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

324

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

325

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

328

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

329

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

336

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

338

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

341

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

343

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

350

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

365

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

367

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

370

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

373

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

427

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

429

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

431

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

433

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

435

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

437

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

439

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

441

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

443

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

445

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

448

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

559

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

561

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

569

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

593

tmp = REG_SET_FIELD(tmp,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

596

tmp = REG_SET_FIELD(tmp,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

599

tmp = REG_SET_FIELD(tmp,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

602

tmp = REG_SET_FIELD(tmp,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

605

tmp = REG_SET_FIELD(tmp,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

608

tmp = REG_SET_FIELD(tmp,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

612

tmp = REG_SET_FIELD(tmp,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

615

tmp = REG_SET_FIELD(tmp,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

618

tmp = REG_SET_FIELD(tmp,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

621

tmp = REG_SET_FIELD(tmp,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

624

tmp = REG_SET_FIELD(tmp,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

627

tmp = REG_SET_FIELD(tmp,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

630

tmp = REG_SET_FIELD(tmp,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

633

tmp = REG_SET_FIELD(tmp,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

636

tmp = REG_SET_FIELD(tmp,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

644

tmp = REG_SET_FIELD(tmp,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

673

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

675

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

677

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

679

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

681

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

683

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

685

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

687

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

689

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

161

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

162

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

163

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

165

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

167

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

169

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

180

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

181

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

183

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

185

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

186

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

187

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

191

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

192

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

197

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

198

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

201

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

202

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

209

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

210

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

212

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

213

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

223

tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

224

tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

226

tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_BLOCK_SIZE,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

228

tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

266

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

267

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

269

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

271

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

274

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

276

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

278

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

280

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

282

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

284

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

291

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

358

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

359

tmp = REG_SET_FIELD(tmp,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

382

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

384

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

386

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

388

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

390

tmp = REG_SET_FIELD(tmp,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

394

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

396

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

398

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

400

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

402

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

404

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

406

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

408

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

177

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

206

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

208

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

210

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

212

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

214

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

216

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

231

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

232

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

234

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

236

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

237

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

238

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

242

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

243

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

248

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

249

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

252

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

253

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

261

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

262

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

264

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

265

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

279

tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

280

tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

282

tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_BLOCK_SIZE,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

284

tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

348

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

349

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

351

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

353

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

356

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

358

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

360

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

362

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

364

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

366

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

374

tmp = REG_SET_FIELD(

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

461

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

462

tmp = REG_SET_FIELD(tmp,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

471

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

495

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

497

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

499

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

501

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

503

tmp = REG_SET_FIELD(tmp,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

507

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

509

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

511

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

513

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

515

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

517

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

519

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

521

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

193

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

194

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

195

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

197

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

199

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

215

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

216

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

217

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

220

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

222

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

223

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

224

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

228

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

229

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

234

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

235

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

238

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

239

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

245

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

246

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

250

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

259

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

260

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

261

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

291

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

292

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

294

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

296

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

298

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

300

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

302

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

304

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

306

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

308

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

312

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

374

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

375

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

398

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

400

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

402

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

404

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

406

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

409

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

411

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

413

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

415

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

417

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

419

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

421

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

423

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

61

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

63

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

64

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

65

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

66

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

67

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

68

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

69

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

197

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

198

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

199

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

201

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

203

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

221

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

222

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

223

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

226

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

228

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

229

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

230

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

234

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

235

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

240

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

241

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

244

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

245

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

251

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

252

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

256

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

265

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

266

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

267

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

303

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

304

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

306

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

308

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

310

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

312

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

314

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

316

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

318

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

320

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

324

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

398

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

399

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

429

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

431

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

433

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

435

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

437

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

440

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

442

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

444

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

446

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

448

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

450

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

452

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

454

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

64

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

66

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

67

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

68

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

69

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

70

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

71

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

72

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

191

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

192

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

193

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

195

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

197

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

198

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

216

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

217

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

218

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

221

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

223

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

224

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

225

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

229

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

230

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

235

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

236

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

239

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

240

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

246

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

247

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

251

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

260

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

261

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

262

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

298

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

299

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

301

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

303

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

305

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

307

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

309

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

311

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

313

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

315

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

319

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

393

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

394

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

416

tmp = REG_SET_FIELD(tmp, CP_DEBUG, CPG_UTCL1_ERROR_HALT_DISABLE, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

426

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

428

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

430

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

432

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

434

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

437

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

439

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

441

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

443

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

445

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

447

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

449

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

451

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

60

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

62

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

63

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

64

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

65

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

66

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

67

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

68

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

196

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

197

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

198

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

200

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

202

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

203

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

221

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

222

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

223

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

226

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

228

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

229

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

230

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

234

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

235

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

240

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

241

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

244

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

245

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

251

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

252

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

256

tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

265

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

266

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

267

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

303

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

304

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

306

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

308

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

310

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

312

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

314

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

316

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

318

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

320

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

324

tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

386

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

387

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

414

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

416

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

418

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

420

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

422

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

425

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

427

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

429

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

431

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

433

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

435

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

437

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

439

tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

63

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

65

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

66

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

67

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

68

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

69

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

70

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

71

req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

394

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

396

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

398

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

400

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

402

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

404

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

425

tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

428

tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

431

tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

434

tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

702

data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

703

data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

704

data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

705

data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

707

data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0);

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

708

data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0);

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

709

data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0);

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

710

data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0);

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

725

data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0);

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

727

data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

741

data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

743

data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

80

blackout = REG_SET_FIELD(blackout,

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

95

tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

98

tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

986

srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

99

tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

992

srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

104

blackout = REG_SET_FIELD(blackout,

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

1172

srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

1178

srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

118

tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

121

tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

122

tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

284

tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

289

tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

308

tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

522

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

524

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

526

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

528

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

530

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

532

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

553

tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

555

tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

557

tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

559

tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

561

tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

563

tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

565

tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

621

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

622

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

623

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

624

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

625

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

629

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

630

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

631

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

632

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

633

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

634

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

635

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

637

tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

638

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

643

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

644

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

645

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

655

tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

656

tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

657

tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

685

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

686

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

687

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

741

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

742

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

743

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

747

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

862

data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

863

data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

864

data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

865

data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

867

data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

868

data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

869

data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

870

data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

885

data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

887

data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

901

data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

903

data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

1303

srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

1309

srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

186

blackout = REG_SET_FIELD(blackout,

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

200

tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

203

tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

204

tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

459

tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

464

tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

494

tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

737

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

739

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

741

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

743

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

745

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

747

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

749

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

770

tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

772

tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

774

tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

776

tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

778

tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

780

tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

782

tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

838

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

839

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

840

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

841

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

842

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

846

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

847

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

848

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

849

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

850

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

851

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

852

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

855

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

856

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

861

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

862

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

863

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

867

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

868

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

869

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

870

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

871

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

872

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

873

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

874

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

875

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

876

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

877

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

878

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

888

tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

889

tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

890

tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

918

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

919

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

920

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

921

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

922

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

923

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

924

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

925

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

926

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

927

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

975

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

976

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

977

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

981

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

712

req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

714

req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

715

req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

716

req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

717

req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

718

req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

719

req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

720

req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,

drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c

102

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,

drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c

107

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,

drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c

111

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,

drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c

120

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c

122

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c

129

hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,

drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c

131

hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,

drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c

58

hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,

drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c

60

hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,

drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c

66

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c

68

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c

70

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c

72

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c

74

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c

76

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c

78

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c

80

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c

88

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,

drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c

91

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,

drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c

95

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,

drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c

98

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,

drivers/gpu/drm/amd/amdgpu/hdp_v5_2.c

101

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,

drivers/gpu/drm/amd/amdgpu/hdp_v5_2.c

105

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,

drivers/gpu/drm/amd/amdgpu/hdp_v5_2.c

108

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,

drivers/gpu/drm/amd/amdgpu/hdp_v5_2.c

112

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,

drivers/gpu/drm/amd/amdgpu/hdp_v5_2.c

115

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,

drivers/gpu/drm/amd/amdgpu/hdp_v5_2.c

123

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/hdp_v5_2.c

125

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/hdp_v5_2.c

132

hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,

drivers/gpu/drm/amd/amdgpu/hdp_v5_2.c

134

hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,

drivers/gpu/drm/amd/amdgpu/hdp_v5_2.c

69

hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,

drivers/gpu/drm/amd/amdgpu/hdp_v5_2.c

71

hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,

drivers/gpu/drm/amd/amdgpu/hdp_v5_2.c

76

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/hdp_v5_2.c

78

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/hdp_v5_2.c

80

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/hdp_v5_2.c

82

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/hdp_v5_2.c

84

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/hdp_v5_2.c

86

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/hdp_v5_2.c

88

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/hdp_v5_2.c

90

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/hdp_v5_2.c

98

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,

drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c

108

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c

110

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c

117

hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,

drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c

52

hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,

drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c

60

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c

62

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c

64

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c

66

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c

68

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c

70

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c

72

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c

74

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c

82

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,

drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c

85

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,

drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c

89

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,

drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c

92

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,

drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c

96

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,

drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c

99

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,

drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c

101

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c

108

hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,

drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c

46

hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,

drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c

51

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c

53

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c

55

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c

57

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c

59

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c

61

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c

63

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c

65

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c

73

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,

drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c

76

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,

drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c

80

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,

drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c

83

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,

drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c

87

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,

drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c

90

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,

drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c

99

hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/iceland_ih.c

121

interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);

drivers/gpu/drm/amd/amdgpu/iceland_ih.c

123

interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);

drivers/gpu/drm/amd/amdgpu/iceland_ih.c

130

ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/iceland_ih.c

131

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);

drivers/gpu/drm/amd/amdgpu/iceland_ih.c

132

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);

drivers/gpu/drm/amd/amdgpu/iceland_ih.c

135

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/iceland_ih.c

149

ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, MC_VMID, 0);

drivers/gpu/drm/amd/amdgpu/iceland_ih.c

152

ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, RPTR_REARM, 1);

drivers/gpu/drm/amd/amdgpu/iceland_ih.c

212

wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);

drivers/gpu/drm/amd/amdgpu/iceland_ih.c

221

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);

drivers/gpu/drm/amd/amdgpu/iceland_ih.c

227

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);

drivers/gpu/drm/amd/amdgpu/iceland_ih.c

382

srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET,

drivers/gpu/drm/amd/amdgpu/iceland_ih.c

65

ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 1);

drivers/gpu/drm/amd/amdgpu/iceland_ih.c

66

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/iceland_ih.c

84

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/iceland_ih.c

85

ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 0);

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

101

ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2,

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

103

ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2,

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

105

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

137

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0));

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

143

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

152

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

163

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

168

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

219

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

221

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

223

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

225

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

229

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

231

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1);

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

232

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0);

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

233

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

243

ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

246

ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

250

ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

280

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled);

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

282

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

283

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

340

ih_chicken = REG_SET_FIELD(ih_chicken,

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

360

tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL,

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

365

tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

374

tmp = REG_SET_FIELD(tmp, IH_MSI_STORM_CTRL,

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

381

tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_INDEX, INDEX, 0);

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

385

tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, CLIENT_ID, 0xa);

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

386

tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, SOURCE_ID, 0x0);

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

387

tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA,

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

451

wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

466

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

472

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

684

data = REG_SET_FIELD(data, IH_CLK_CTRL,

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

686

data = REG_SET_FIELD(data, IH_CLK_CTRL,

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

688

data = REG_SET_FIELD(data, IH_CLK_CTRL,

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

690

data = REG_SET_FIELD(data, IH_CLK_CTRL,

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

692

data = REG_SET_FIELD(data, IH_CLK_CTRL,

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

716

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

723

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

725

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

727

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

730

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

732

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

734

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

737

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

741

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

743

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

745

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

748

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

750

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

752

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

755

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

101

ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2,

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

103

ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2,

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

105

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

137

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0));

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

140

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

191

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

193

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

195

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

197

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

201

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

203

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1);

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

204

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0);

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

205

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

215

ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

218

ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

222

ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

252

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled);

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

254

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

255

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

312

ih_chicken = REG_SET_FIELD(ih_chicken,

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

331

tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL,

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

336

tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

345

tmp = REG_SET_FIELD(tmp, IH_MSI_STORM_CTRL,

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

352

tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_INDEX, INDEX, 0);

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

356

tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, CLIENT_ID, 0xa);

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

357

tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, SOURCE_ID, 0x0);

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

358

tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA,

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

421

wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

434

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

440

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

659

data = REG_SET_FIELD(data, IH_CLK_CTRL,

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

661

data = REG_SET_FIELD(data, IH_CLK_CTRL,

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

663

data = REG_SET_FIELD(data, IH_CLK_CTRL,

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

665

data = REG_SET_FIELD(data, IH_CLK_CTRL,

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

667

data = REG_SET_FIELD(data, IH_CLK_CTRL,

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

693

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

700

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

702

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

704

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

707

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

709

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

711

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

714

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

718

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

720

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

722

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

725

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

727

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

729

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

732

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

101

ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2,

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

103

ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2,

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

105

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

137

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0));

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

140

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

191

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

193

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

195

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

197

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

201

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

203

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1);

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

204

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0);

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

205

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

215

ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

218

ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

222

ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

252

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled);

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

254

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

255

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

286

val = REG_SET_FIELD(val, IH_DOORBELL_RPTR, OFFSET, doorbell_index);

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

287

val = REG_SET_FIELD(val, IH_DOORBELL_RPTR, ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

335

ih_chicken = REG_SET_FIELD(ih_chicken,

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

354

tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL,

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

359

tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

368

tmp = REG_SET_FIELD(tmp, IH_MSI_STORM_CTRL,

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

380

tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_INDEX, INDEX, 0);

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

389

tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, CLIENT_ID, 0xa);

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

390

tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, SOURCE_ID, 0x0);

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

391

tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA,

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

406

tmp = REG_SET_FIELD(tmp, IH_RETRY_INT_CAM_CNTL, ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

407

tmp = REG_SET_FIELD(tmp, IH_RETRY_INT_CAM_CNTL, CAM_SIZE, 0xF);

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

468

wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

481

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

487

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

699

data = REG_SET_FIELD(data, IH_CLK_CTRL,

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

701

data = REG_SET_FIELD(data, IH_CLK_CTRL,

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

703

data = REG_SET_FIELD(data, IH_CLK_CTRL,

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

705

data = REG_SET_FIELD(data, IH_CLK_CTRL,

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

707

data = REG_SET_FIELD(data, IH_CLK_CTRL,

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

733

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

740

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

742

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

744

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

747

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

749

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

751

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

754

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

758

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

760

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

762

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

765

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

767

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

769

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

772

ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,

drivers/gpu/drm/amd/amdgpu/lsdma_v6_0.c

110

tmp = REG_SET_FIELD(tmp, LSDMA_MEM_POWER_CTRL, MEM_POWER_CTRL_EN, 0);

drivers/gpu/drm/amd/amdgpu/lsdma_v6_0.c

113

tmp = REG_SET_FIELD(tmp, LSDMA_MEM_POWER_CTRL, MEM_POWER_CTRL_EN, enable);

drivers/gpu/drm/amd/amdgpu/lsdma_v6_0.c

56

tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, BYTE_COUNT, size);

drivers/gpu/drm/amd/amdgpu/lsdma_v6_0.c

57

tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, SRC_LOCATION, 0);

drivers/gpu/drm/amd/amdgpu/lsdma_v6_0.c

58

tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, DST_LOCATION, 0);

drivers/gpu/drm/amd/amdgpu/lsdma_v6_0.c

59

tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, SRC_ADDR_INC, 0);

drivers/gpu/drm/amd/amdgpu/lsdma_v6_0.c

60

tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, DST_ADDR_INC, 0);

drivers/gpu/drm/amd/amdgpu/lsdma_v6_0.c

61

tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, OVERLAP_DISABLE, 0);

drivers/gpu/drm/amd/amdgpu/lsdma_v6_0.c

62

tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, CONSTANT_FILL, 0);

drivers/gpu/drm/amd/amdgpu/lsdma_v6_0.c

88

tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, BYTE_COUNT, size);

drivers/gpu/drm/amd/amdgpu/lsdma_v6_0.c

89

tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, SRC_LOCATION, 0);

drivers/gpu/drm/amd/amdgpu/lsdma_v6_0.c

90

tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, DST_LOCATION, 0);

drivers/gpu/drm/amd/amdgpu/lsdma_v6_0.c

91

tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, SRC_ADDR_INC, 0);

drivers/gpu/drm/amd/amdgpu/lsdma_v6_0.c

92

tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, DST_ADDR_INC, 0);

drivers/gpu/drm/amd/amdgpu/lsdma_v6_0.c

93

tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, OVERLAP_DISABLE, 0);

drivers/gpu/drm/amd/amdgpu/lsdma_v6_0.c

94

tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, CONSTANT_FILL, 1);

drivers/gpu/drm/amd/amdgpu/lsdma_v7_0.c

110

tmp = REG_SET_FIELD(tmp, LSDMA_MEM_POWER_CTRL, MEM_POWER_CTRL_EN, 0);

drivers/gpu/drm/amd/amdgpu/lsdma_v7_0.c

113

tmp = REG_SET_FIELD(tmp, LSDMA_MEM_POWER_CTRL, MEM_POWER_CTRL_EN, enable);

drivers/gpu/drm/amd/amdgpu/lsdma_v7_0.c

56

tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, BYTE_COUNT, size);

drivers/gpu/drm/amd/amdgpu/lsdma_v7_0.c

57

tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, SRC_LOCATION, 0);

drivers/gpu/drm/amd/amdgpu/lsdma_v7_0.c

58

tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, DST_LOCATION, 0);

drivers/gpu/drm/amd/amdgpu/lsdma_v7_0.c

59

tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, SRC_ADDR_INC, 0);

drivers/gpu/drm/amd/amdgpu/lsdma_v7_0.c

60

tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, DST_ADDR_INC, 0);

drivers/gpu/drm/amd/amdgpu/lsdma_v7_0.c

61

tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, OVERLAP_DISABLE, 0);

drivers/gpu/drm/amd/amdgpu/lsdma_v7_0.c

62

tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, CONSTANT_FILL, 0);

drivers/gpu/drm/amd/amdgpu/lsdma_v7_0.c

88

tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, BYTE_COUNT, size);

drivers/gpu/drm/amd/amdgpu/lsdma_v7_0.c

89

tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, SRC_LOCATION, 0);

drivers/gpu/drm/amd/amdgpu/lsdma_v7_0.c

90

tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, DST_LOCATION, 0);

drivers/gpu/drm/amd/amdgpu/lsdma_v7_0.c

91

tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, SRC_ADDR_INC, 0);

drivers/gpu/drm/amd/amdgpu/lsdma_v7_0.c

92

tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, DST_ADDR_INC, 0);

drivers/gpu/drm/amd/amdgpu/lsdma_v7_0.c

93

tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, OVERLAP_DISABLE, 0);

drivers/gpu/drm/amd/amdgpu/lsdma_v7_0.c

94

tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, CONSTANT_FILL, 1);

drivers/gpu/drm/amd/amdgpu/lsdma_v7_1.c

56

tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, COUNT, size);

drivers/gpu/drm/amd/amdgpu/lsdma_v7_1.c

57

tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, RAW_WAIT, 0);

drivers/gpu/drm/amd/amdgpu/lsdma_v7_1.c

58

tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, CONSTANT_FILL, 0);

drivers/gpu/drm/amd/amdgpu/lsdma_v7_1.c

84

tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, COUNT, size);

drivers/gpu/drm/amd/amdgpu/lsdma_v7_1.c

85

tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, RAW_WAIT, 0);

drivers/gpu/drm/amd/amdgpu/lsdma_v7_1.c

86

tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, CONSTANT_FILL, 1);

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

1008

data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0);

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

1009

data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0);

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

1010

data = REG_SET_FIELD(data, CP_MES_CNTL,

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

1012

data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

1013

data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET,

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

1015

data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1);

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

1077

data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0);

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

1078

data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1);

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

1083

data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1);

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

1138

tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

1157

tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

1178

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

1180

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

1182

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

1183

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

1184

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

1185

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

1186

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1);

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

1192

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

1194

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

1196

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

1198

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

1201

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

1210

tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE,

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

1233

data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0);

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

1238

data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

1248

data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0);

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

1540

data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

1542

data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

418

value = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid);

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

420

value = REG_SET_FIELD(value, CP_VMID_RESET, PIPE0_QUEUES, 1 << queue_id);

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

422

value = REG_SET_FIELD(value, CP_VMID_RESET, PIPE1_QUEUES, 1 << queue_id);

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

974

data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

975

data = REG_SET_FIELD(data, CP_MES_CNTL,

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

997

data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1);

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

998

data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE,

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

1116

data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

1118

data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 1);

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

1128

data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1);

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

1130

data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 1);

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

1147

data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0);

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

1148

data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0);

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

1149

data = REG_SET_FIELD(data, CP_MES_CNTL,

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

1151

data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

1152

data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 1);

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

1153

data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1);

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

1231

data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0);

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

1232

data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1);

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

1237

data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1);

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

1290

tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

1309

tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

1330

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

1332

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

1334

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

1335

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

1336

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

1337

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

1338

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1);

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

1344

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

1346

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

1348

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

1350

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

1353

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

1363

tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE,

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

1392

data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0);

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

1397

data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

1407

data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0);

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

1712

data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

1714

data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

391

tmp = REG_SET_FIELD(0, CP_GFX_INDEX_MUTEX, REQUEST, req);

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

392

tmp = REG_SET_FIELD(tmp, CP_GFX_INDEX_MUTEX, CLIENTID, 4);

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

400

tmp = REG_SET_FIELD(tmp, CP_GFX_INDEX_MUTEX,

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

435

value = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid);

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

437

value = REG_SET_FIELD(value, CP_VMID_RESET, PIPE0_QUEUES, 1 << queue_id);

drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

439

value = REG_SET_FIELD(value, CP_VMID_RESET, PIPE1_QUEUES, 1 << queue_id);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1066

data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1067

data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 1);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1087

data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1088

data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 1);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1099

data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1100

data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1101

data = REG_SET_FIELD(data, CP_MES_CNTL,

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1103

data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1104

data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 1);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1105

data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1185

data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1186

data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1191

data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1265

tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1284

tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1305

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1307

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1309

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1310

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1311

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1312

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1313

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1319

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1321

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1323

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1325

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1328

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1338

tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE,

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1368

data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1373

data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1383

data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0);

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1707

data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/mes_v12_1.c

1709

data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

132

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

144

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

145

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

146

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

148

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

150

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

152

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

166

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

167

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

169

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

171

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

172

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

173

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

177

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

178

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

183

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

184

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

187

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

188

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

194

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

195

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

204

tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

205

tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

206

tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

294

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

295

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

297

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

299

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

302

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

304

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

306

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

308

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

310

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

312

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

316

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

403

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

404

tmp = REG_SET_FIELD(tmp,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

413

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

433

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

435

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

437

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

439

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

441

tmp = REG_SET_FIELD(tmp,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

445

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

447

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

449

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

451

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

453

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

455

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

458

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

460

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

1342

reg_value = REG_SET_FIELD(reg_value, MMEA0_ERR_STATUS,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

150

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

162

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

163

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

164

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

166

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

168

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

170

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

208

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

209

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

211

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

213

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

214

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

215

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

219

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

220

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

225

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

226

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

229

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

230

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

237

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

239

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

242

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

244

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

255

tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

256

tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

258

tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_BLOCK_SIZE,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

260

tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

302

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

303

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

305

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

307

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

310

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

312

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

314

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

316

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

318

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

320

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

326

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

387

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

388

tmp = REG_SET_FIELD(tmp,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

397

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

417

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

419

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

421

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

423

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

425

tmp = REG_SET_FIELD(tmp,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

429

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

431

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

433

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

435

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

437

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

439

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

442

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

444

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

187

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

201

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

203

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

205

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

207

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

209

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

211

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

219

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

221

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

223

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

225

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

227

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

229

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

277

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

278

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

281

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

283

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

285

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

287

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

292

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

294

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

299

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

300

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

303

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

304

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

312

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

314

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

317

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

319

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

334

tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

335

tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

337

tmp = REG_SET_FIELD(tmp,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

340

tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

397

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

399

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

401

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

403

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

405

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

407

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

409

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

411

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

413

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

415

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

422

tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

487

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

488

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

495

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

497

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

520

tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

547

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

549

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

551

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

553

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

555

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

558

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

560

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

562

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

564

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

566

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

568

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

571

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

573

tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

125

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

127

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

128

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

129

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

130

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

131

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

132

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

133

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

235

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

247

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

248

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

249

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

251

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

253

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

271

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

272

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

273

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

276

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

278

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

279

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

280

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

284

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

285

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

290

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

291

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

294

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

295

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

301

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

302

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

306

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

315

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

316

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

317

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

356

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

357

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

359

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

361

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

364

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

366

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

368

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

370

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

372

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

374

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

378

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

440

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

441

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

447

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

469

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

471

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

473

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

475

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

477

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

480

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

482

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

484

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

486

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

488

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

490

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

493

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

495

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

171

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

183

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

184

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

185

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

187

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

189

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

201

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

202

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

203

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

206

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

208

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

209

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

210

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

214

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

215

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

220

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

221

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

224

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

225

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

231

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

232

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

236

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

245

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

246

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

247

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

280

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

281

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

283

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

285

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

288

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

290

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

292

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

294

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

296

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

298

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

302

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

378

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

379

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

385

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

402

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

404

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

406

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

408

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

410

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

413

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

415

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

417

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

419

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

421

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

423

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

426

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

428

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

64

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

66

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

67

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

68

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

69

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

70

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

71

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

72

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

197

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

209

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

210

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

211

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

213

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

215

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

216

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

234

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

235

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

236

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

239

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

241

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

242

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

243

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

247

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

248

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

253

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

254

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

257

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

258

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

264

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

265

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

269

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

278

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

279

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

280

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

319

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

320

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

322

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

324

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

327

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

329

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

331

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

333

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

335

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

337

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

341

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

403

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

404

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

410

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

432

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

434

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

436

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

438

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

440

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

443

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

445

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

447

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

449

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

451

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

453

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

456

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

458

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

81

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

83

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

84

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

85

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

86

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

87

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

88

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

89

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

202

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

214

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

215

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

216

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

218

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

220

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

221

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

233

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

234

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

235

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

238

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

240

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

241

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

242

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

246

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

247

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

252

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

253

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

256

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

257

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

263

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

264

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

268

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

277

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

278

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

279

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

312

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

313

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

315

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

317

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

320

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

322

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

324

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

326

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

328

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

330

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

334

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

396

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

397

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

403

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

420

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

422

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

424

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

426

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

428

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

431

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

433

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

435

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

437

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

439

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

441

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

444

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

446

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

88

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

90

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

91

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

92

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

93

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

94

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

95

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

96

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

196

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

208

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

209

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

210

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

212

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

214

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

215

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

233

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

234

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

235

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

238

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

240

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

241

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

242

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

246

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

247

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

252

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

253

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

256

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

257

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

263

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

264

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

268

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

277

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

278

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

279

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

318

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

319

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

321

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

323

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

326

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

328

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

330

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

332

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

334

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

336

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

340

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

402

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

403

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

409

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

431

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

433

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

435

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

437

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

439

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

442

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

444

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

446

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

448

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

450

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

452

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

455

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

457

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

81

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

83

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

84

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

85

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

86

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

87

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

88

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

89

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

201

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

203

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type ? : 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

204

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

205

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

206

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

207

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

208

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

209

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

319

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

331

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

332

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

333

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

335

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

337

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

338

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

350

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

351

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

352

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

355

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

357

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

358

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

359

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

363

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

364

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

369

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

370

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

373

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

374

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

380

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

381

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

385

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

394

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

395

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

396

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

430

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

431

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

433

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

435

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

438

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

440

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

442

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

444

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

446

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

448

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

452

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

507

tmp = REG_SET_FIELD(tmp, MMVM_L2_SAW_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

508

tmp = REG_SET_FIELD(tmp, MMVM_L2_SAW_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

517

tmp = REG_SET_FIELD(tmp, MMVM_L2_SAW_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

518

tmp = REG_SET_FIELD(tmp, MMVM_L2_SAW_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

563

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

564

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

570

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

587

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

589

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

591

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

593

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

595

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

598

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

600

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

602

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

604

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

606

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

608

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

611

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

613

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

191

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

203

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

204

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

205

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

207

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

209

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

210

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

228

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

229

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

230

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

233

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

235

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

236

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

237

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

241

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

242

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

247

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

248

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

251

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

252

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

258

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

259

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

263

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

272

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

273

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

274

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

313

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

314

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

316

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

318

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

321

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

323

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

325

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

327

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

329

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

331

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

335

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

397

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

398

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

404

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

427

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

429

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

431

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

433

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

435

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

438

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

440

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

442

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

444

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

446

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

448

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

451

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

453

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

73

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

76

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

77

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

78

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

79

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

80

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

81

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

82

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

320

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

322

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

340

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

341

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

342

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

344

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

346

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

347

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

370

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

371

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

372

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

375

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

377

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

379

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

381

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

386

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

388

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

394

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

395

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

398

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

399

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

407

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

409

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

412

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

414

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

420

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

435

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

437

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

439

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

442

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

497

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

498

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

500

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

502

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

505

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

507

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

509

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

511

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

513

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

515

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

519

tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

602

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

604

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

611

tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

641

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL_LO32,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

643

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL_LO32,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

645

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL_LO32,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

647

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL_LO32,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

649

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL_LO32,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

652

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL_LO32,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

654

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL_LO32,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

656

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL_LO32,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

658

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL_LO32,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

660

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL_LO32,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

662

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL_LO32,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

665

tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL_LO32,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

696

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

699

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

700

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

701

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

702

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

703

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

704

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE3, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

705

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

706

req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

166

tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2,

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

184

tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

186

tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

188

tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

190

tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

192

tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

194

tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

238

tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

240

tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

243

tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

245

tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

247

tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

249

tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

256

tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL2,

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

258

tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL2,

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

265

tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3, BANK_SELECT, 12);

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

266

tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3,

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

269

tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3, BANK_SELECT, 9);

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

270

tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3,

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

277

tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL4,

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

279

tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL4,

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

292

tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

293

tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

294

tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT0_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

342

tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

344

tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

347

tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

349

tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

352

tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

354

tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

356

tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

358

tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

360

tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

362

tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

366

tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

454

tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

456

tmp = REG_SET_FIELD(tmp,

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

466

tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

490

tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

493

tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

496

tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

499

tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

502

tmp = REG_SET_FIELD(tmp,

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

506

tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

509

tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

512

tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

515

tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

518

tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

521

tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

525

tmp = REG_SET_FIELD(tmp,

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

528

tmp = REG_SET_FIELD(tmp,

drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c

142

reg = REG_SET_FIELD(reg, BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0,

drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c

245

tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_MAILBOX_INT_CNTL, ACK_INT_EN,

drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c

333

tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_MAILBOX_INT_CNTL, VALID_INT_EN,

drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c

326

reg = REG_SET_FIELD(reg, MAILBOX_CONTROL, RCV_MSG_ACK, 1);

drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c

348

reg = REG_SET_FIELD(reg, MAILBOX_CONTROL,

drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c

359

reg = REG_SET_FIELD(reg, MAILBOX_MSGBUF_TRN_DW0,

drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c

506

tmp = REG_SET_FIELD(tmp, MAILBOX_INT_CNTL, ACK_INT_EN,

drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c

539

tmp = REG_SET_FIELD(tmp, MAILBOX_INT_CNTL, VALID_INT_EN,

drivers/gpu/drm/amd/amdgpu/navi10_ih.c

116

ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2,

drivers/gpu/drm/amd/amdgpu/navi10_ih.c

118

ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2,

drivers/gpu/drm/amd/amdgpu/navi10_ih.c

120

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,

drivers/gpu/drm/amd/amdgpu/navi10_ih.c

131

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,

drivers/gpu/drm/amd/amdgpu/navi10_ih.c

162

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0));

drivers/gpu/drm/amd/amdgpu/navi10_ih.c

163

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_GPU_TS_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/navi10_ih.c

166

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));

drivers/gpu/drm/amd/amdgpu/navi10_ih.c

217

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/navi10_ih.c

219

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/navi10_ih.c

221

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/navi10_ih.c

223

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);

drivers/gpu/drm/amd/amdgpu/navi10_ih.c

227

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/navi10_ih.c

229

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1);

drivers/gpu/drm/amd/amdgpu/navi10_ih.c

230

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0);

drivers/gpu/drm/amd/amdgpu/navi10_ih.c

231

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);

drivers/gpu/drm/amd/amdgpu/navi10_ih.c

241

ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,

drivers/gpu/drm/amd/amdgpu/navi10_ih.c

244

ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,

drivers/gpu/drm/amd/amdgpu/navi10_ih.c

248

ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,

drivers/gpu/drm/amd/amdgpu/navi10_ih.c

278

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled);

drivers/gpu/drm/amd/amdgpu/navi10_ih.c

280

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/navi10_ih.c

338

ih_chicken = REG_SET_FIELD(ih_chicken,

drivers/gpu/drm/amd/amdgpu/navi10_ih.c

344

ih_chicken = REG_SET_FIELD(ih_chicken,

drivers/gpu/drm/amd/amdgpu/navi10_ih.c

430

wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);

drivers/gpu/drm/amd/amdgpu/navi10_ih.c

442

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);

drivers/gpu/drm/amd/amdgpu/navi10_ih.c

448

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);

drivers/gpu/drm/amd/amdgpu/navi10_ih.c

654

data = REG_SET_FIELD(data, IH_CLK_CTRL,

drivers/gpu/drm/amd/amdgpu/navi10_ih.c

656

data = REG_SET_FIELD(data, IH_CLK_CTRL,

drivers/gpu/drm/amd/amdgpu/navi10_ih.c

658

data = REG_SET_FIELD(data, IH_CLK_CTRL,

drivers/gpu/drm/amd/amdgpu/navi10_ih.c

660

data = REG_SET_FIELD(data, IH_CLK_CTRL,

drivers/gpu/drm/amd/amdgpu/navi10_ih.c

662

data = REG_SET_FIELD(data, IH_CLK_CTRL,

drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c

168

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c

172

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c

176

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c

180

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c

184

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c

189

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c

216

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c

220

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c

224

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c

228

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c

232

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c

237

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c

264

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c

268

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c

272

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c

276

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c

280

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c

285

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c

325

tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,

drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c

327

REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,

drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c

329

REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,

drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c

353

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c

357

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c

361

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c

365

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c

369

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c

374

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c

402

interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL,

drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c

406

interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL,

drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c

678

bif_doorbell_int_cntl = REG_SET_FIELD(bif_doorbell_int_cntl,

drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c

712

bif_doorbell_int_cntl = REG_SET_FIELD(bif_doorbell_int_cntl,

drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c

120

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c

123

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c

127

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c

143

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c

146

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c

149

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c

168

tmp = REG_SET_FIELD(tmp, BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL,

drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c

170

REG_SET_FIELD(tmp, BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL,

drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c

172

REG_SET_FIELD(tmp, BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL,

drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c

192

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c

195

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c

199

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c

218

interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL,

drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c

222

interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL,

drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c

336

data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);

drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c

337

data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);

drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c

113

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c

117

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c

121

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c

125

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c

129

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c

134

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c

164

tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,

drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c

166

REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,

drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c

168

REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,

drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c

187

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c

191

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c

195

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c

199

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c

203

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c

208

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c

228

interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL,

drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c

232

interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL,

drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c

570

bif_doorbell_int_cntl = REG_SET_FIELD(bif_doorbell_int_cntl,

drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c

604

bif_doorbell_int_cntl = REG_SET_FIELD(bif_doorbell_int_cntl,

drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c

72

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c

76

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c

80

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c

84

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c

88

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c

93

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c

100

doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);

drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c

118

tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_EN, 1) |

drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c

119

REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_MODE, 1) |

drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c

120

REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_SIZE, 0);

drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c

138

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index);

drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c

139

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c

142

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0);

drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c

157

interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);

drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c

159

interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);

drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c

267

data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);

drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c

268

data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);

drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c

274

data = REG_SET_FIELD(data, PCIE_CI_CNTL, CI_SLV_ORDERING_DIS, 1);

drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c

97

doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);

drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c

98

doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, doorbell_size);

drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.c

101

tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,

drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.c

103

REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,

drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.c

105

REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,

drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.c

136

interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL,

drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.c

140

interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL,

drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.c

153

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.c

157

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.c

161

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.c

165

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.c

169

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.c

173

ih_doorbell_range1 = REG_SET_FIELD(ih_doorbell_range1,

drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.c

177

ih_doorbell_range1 = REG_SET_FIELD(ih_doorbell_range1,

drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.c

181

ih_doorbell_range1 = REG_SET_FIELD(ih_doorbell_range1,

drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.c

207

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.c

211

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.c

215

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.c

219

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.c

223

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.c

227

doorbell_range1 = REG_SET_FIELD(doorbell_range1,

drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.c

231

doorbell_range1 = REG_SET_FIELD(doorbell_range1,

drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.c

235

doorbell_range1 = REG_SET_FIELD(doorbell_range1,

drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.c

254

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.c

258

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.c

262

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.c

266

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.c

270

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.c

274

doorbell_range1 = REG_SET_FIELD(doorbell_range1,

drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.c

278

doorbell_range1 = REG_SET_FIELD(doorbell_range1,

drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.c

282

doorbell_range1 = REG_SET_FIELD(doorbell_range1,

drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c

122

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index);

drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c

123

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 2);

drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c

125

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0);

drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c

232

interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);

drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c

234

interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);

drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c

76

doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);

drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c

77

doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, doorbell_size);

drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c

79

doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);

drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c

92

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c

95

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c

98

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c

100

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c

104

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c

123

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c

126

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c

129

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c

143

reg = REG_SET_FIELD(reg, RCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN,

drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c

155

tmp = REG_SET_FIELD(tmp, BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL,

drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c

157

REG_SET_FIELD(tmp, BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL,

drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c

159

REG_SET_FIELD(tmp, BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL,

drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c

180

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c

183

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c

187

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c

209

interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX1_INTERRUPT_CNTL,

drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c

213

interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX1_INTERRUPT_CNTL,

drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c

269

data = REG_SET_FIELD(data, BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3,

drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c

271

data = REG_SET_FIELD(data, BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3,

drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c

72

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c

75

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c

79

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c

97

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c

115

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c

118

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c

122

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c

137

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c

140

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c

143

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c

156

reg = REG_SET_FIELD(reg, RCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN,

drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c

168

tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,

drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c

170

REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,

drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c

172

REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,

drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c

194

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c

197

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c

201

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c

223

interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL,

drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c

227

interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL,

drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c

376

data = REG_SET_FIELD(data, BIF1_PCIE_MST_CTRL_3,

drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c

378

data = REG_SET_FIELD(data, BIF1_PCIE_MST_CTRL_3,

drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c

386

data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL,

drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c

388

data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL,

drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c

171

doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);

drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c

172

doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, doorbell_size);

drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c

174

doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);

drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c

196

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c

199

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c

202

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c

220

tmp = REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_EN, 1) |

drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c

221

REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_MODE, 1) |

drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c

222

REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_SIZE, 0);

drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c

239

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index);

drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c

240

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 8);

drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c

242

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0);

drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c

300

interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);

drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c

302

interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);

drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c

377

bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,

drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c

434

bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,

drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c

467

bif_intr_cntl = REG_SET_FIELD(bif_intr_cntl,

drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c

512

bif_intr_cntl = REG_SET_FIELD(bif_intr_cntl,

drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c

636

int_eoi = REG_SET_FIELD(int_eoi,

drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c

100

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c

113

reg = REG_SET_FIELD(reg, RCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN,

drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c

125

tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,

drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c

127

REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,

drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c

129

REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,

drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c

152

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c

155

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c

159

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c

181

interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX1_INTERRUPT_CNTL,

drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c

185

interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX1_INTERRUPT_CNTL,

drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c

241

data = REG_SET_FIELD(data, BIF0_PCIE_MST_CTRL_3,

drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c

243

data = REG_SET_FIELD(data, BIF0_PCIE_MST_CTRL_3,

drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c

72

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c

75

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c

79

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c

94

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c

97

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c

105

doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,

drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c

108

doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,

drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c

111

doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,

drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c

122

doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,

drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c

125

doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,

drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c

128

doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,

drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c

139

doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,

drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c

142

doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,

drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c

145

doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,

drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c

156

doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,

drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c

159

doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,

drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c

162

doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,

drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c

185

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c

189

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c

194

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c

199

doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,

drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c

202

doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,

drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c

205

doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,

drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c

208

doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,

drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c

211

doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,

drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c

220

doorbell_range = REG_SET_FIELD(doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c

223

doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,

drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c

249

tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,

drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c

251

REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,

drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c

253

REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,

drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c

271

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c

275

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c

280

ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl,

drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c

283

ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl,

drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c

286

ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl,

drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c

289

ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl,

drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c

292

ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl,

drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c

296

ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,

drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c

299

ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl,

drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c

335

REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);

drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c

338

REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);

drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c

533

bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,

drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c

579

bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,

drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c

88

REG_SET_FIELD(doorbell_range, DOORBELL0_CTRL_ENTRY_0,

drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c

91

REG_SET_FIELD(doorbell_range, DOORBELL0_CTRL_ENTRY_0,

drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c

94

REG_SET_FIELD(doorbell_ctrl, S2A_DOORBELL_ENTRY_1_CTRL,

drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c

97

REG_SET_FIELD(doorbell_ctrl, S2A_DOORBELL_ENTRY_1_CTRL,

drivers/gpu/drm/amd/amdgpu/nv.c

321

grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);

drivers/gpu/drm/amd/amdgpu/nv.c

322

grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);

drivers/gpu/drm/amd/amdgpu/nv.c

323

grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);

drivers/gpu/drm/amd/amdgpu/nv.c

324

grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);

drivers/gpu/drm/amd/amdgpu/psp_v3_1.c

165

tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b);

drivers/gpu/drm/amd/amdgpu/psp_v3_1.c

166

tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);

drivers/gpu/drm/amd/amdgpu/psp_v3_1.c

167

tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);

drivers/gpu/drm/amd/amdgpu/psp_v3_1.c

178

tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b);

drivers/gpu/drm/amd/amdgpu/psp_v3_1.c

179

tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

1004

sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

1009

sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

1020

sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

1025

sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

279

ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

281

ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

344

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

347

ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

385

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

387

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

428

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

430

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

431

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

448

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

457

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

461

ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

463

ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

960

tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

967

tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

1342

sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

1347

sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

1358

sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

1363

sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

455

ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

457

ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

520

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

523

ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

580

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

582

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

591

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

593

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

622

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

624

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

668

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

670

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

671

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

689

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

697

doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL,

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

699

doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

701

doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

716

wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

720

wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

727

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

731

ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

733

ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

1011

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

1057

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

1070

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

1072

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

1073

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

1112

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

1126

doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE,

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

1128

doorbell_offset = REG_SET_FIELD(doorbell_offset,

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

1146

wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

1152

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

1156

ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

1158

ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

1197

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

1211

doorbell = REG_SET_FIELD(doorbell, SDMA0_PAGE_DOORBELL, ENABLE,

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

1213

doorbell_offset = REG_SET_FIELD(doorbell_offset,

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

1232

wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

1238

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, RB_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

1242

ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

1244

ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_SWAP_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

1414

temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

1420

temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

2079

sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

2169

sdma_edc_config = REG_SET_FIELD(sdma_edc_config, SDMA0_EDC_CONFIG, ECC_INT_ENABLE,

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

605

temp = REG_SET_FIELD(temp, SDMA0_ULV_CNTL, HYSTERESIS, 0x0);

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

928

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, enable ? 1 : 0);

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

931

ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, enable ? 1 : 0);

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

962

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

966

ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL,

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

1002

temp = REG_SET_FIELD(temp, SDMA_CNTL, UTC_L1_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

1007

temp = REG_SET_FIELD(temp, SDMA_CNTL, CTXEMPTY_INT_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

1014

temp = REG_SET_FIELD(temp, SDMA_F32_CNTL, HALT, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

169

val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG, NUM_BANKS, 4);

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

170

val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG,

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

175

val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG_READ, NUM_BANKS,

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

1763

sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, TRAP_ENABLE,

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

177

val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG_READ,

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

1862

sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, DRAM_ECC_INT_ENABLE,

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

502

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

505

ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

508

sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, UTC_L1_ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

515

doorbell = REG_SET_FIELD(doorbell, SDMA_GFX_DOORBELL, ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

516

doorbell_offset = REG_SET_FIELD(doorbell_offset,

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

555

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

559

ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL,

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

606

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA_CNTL,

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

652

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA_F32_CNTL, HALT, enable ? 0 : 1);

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

666

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_SIZE, rb_bufsz);

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

668

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

669

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

707

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

743

doorbell = REG_SET_FIELD(doorbell, SDMA_GFX_DOORBELL, ENABLE,

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

745

doorbell_offset = REG_SET_FIELD(doorbell_offset,

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

763

wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

769

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

773

ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

775

ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

834

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

849

doorbell = REG_SET_FIELD(doorbell, SDMA_PAGE_DOORBELL, ENABLE,

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

851

doorbell_offset = REG_SET_FIELD(doorbell_offset,

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

870

wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

876

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL, RB_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

880

ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, IB_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

882

ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, IB_SWAP_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1334

grbm_soft_reset = REG_SET_FIELD(0,

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1583

freeze = REG_SET_FIELD(freeze, SDMA0_FREEZE, FREEZE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1604

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1608

cntl = REG_SET_FIELD(cntl, SDMA0_CNTL, UTC_L1_ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1625

freeze = REG_SET_FIELD(freeze, SDMA0_FREEZE, FREEZE, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

1694

sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

569

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

572

ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

629

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

672

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

706

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

708

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

709

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

734

wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

746

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

771

doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

772

doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

775

doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

793

temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

796

temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

801

temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

802

temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

816

temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

821

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

825

ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

827

ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

991

m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_RLC0_DOORBELL, ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1494

freeze = REG_SET_FIELD(freeze, SDMA0_FREEZE, FREEZE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1516

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1520

cntl = REG_SET_FIELD(cntl, SDMA0_CNTL, UTC_L1_ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1538

freeze = REG_SET_FIELD(freeze, SDMA0_FREEZE, FREEZE, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

1603

sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

419

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

422

ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

488

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

519

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

555

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

557

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

558

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

584

wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

596

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

616

doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

617

doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

620

doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

640

temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

643

temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

648

temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

649

temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

663

temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

668

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

672

ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

674

ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

770

grbm_soft_reset = REG_SET_FIELD(0,

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

891

m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_RLC0_DOORBELL, ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

1622

sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

402

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

405

ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

438

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

468

f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

500

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SIZE, rb_bufsz);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

502

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SWAP_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

503

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

506

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_PRIV, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

534

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

535

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

536

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, F32_WPTR_POLL_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

556

doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

557

doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_QUEUE0_DOORBELL_OFFSET,

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

560

doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

579

temp = REG_SET_FIELD(temp, SDMA0_WATCHDOG_CNTL, QUEUE_HANG_COUNT,

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

585

temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

586

temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

601

temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

602

temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, TH1_RESET, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

607

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

611

ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

613

ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_SWAP_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

886

m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_QUEUE0_DOORBELL, ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

1554

sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

404

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

407

ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

459

mcu_cntl = REG_SET_FIELD(mcu_cntl, SDMA0_MCU_CNTL, HALT, enable ? 0 : 1);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

490

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SIZE, rb_bufsz);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

492

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SWAP_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

493

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

496

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_PRIV, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

524

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

526

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

528

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

530

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, MCU_WPTR_POLL_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

550

doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

551

doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_QUEUE0_DOORBELL_OFFSET,

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

554

doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

573

temp = REG_SET_FIELD(temp, SDMA0_WATCHDOG_CNTL, QUEUE_HANG_COUNT,

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

579

temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

580

temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

594

temp = REG_SET_FIELD(temp, SDMA0_MCU_CNTL, HALT, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

595

temp = REG_SET_FIELD(temp, SDMA0_MCU_CNTL, RESET, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

600

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

604

ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

606

ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_SWAP_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

718

tmp = REG_SET_FIELD(tmp, SDMA0_IC_CNTL, GPA, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

727

tmp = REG_SET_FIELD(tmp, SDMA0_IC_OP_CNTL, PRIME_ICACHE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

904

m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_QUEUE0_DOORBELL, ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

1518

sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_SDMA_CNTL, TRAP_ENABLE,

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

374

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_SDMA_QUEUE0_RB_CNTL, RB_ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

377

ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_SDMA_QUEUE0_IB_CNTL, IB_ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

441

mcu_cntl = REG_SET_FIELD(mcu_cntl, SDMA0_SDMA_MCU_CNTL, HALT, enable ? 0 : 1);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

472

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_SDMA_QUEUE0_RB_CNTL, RB_SIZE, rb_bufsz);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

474

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_SDMA_QUEUE0_RB_CNTL, RB_SWAP_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

475

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_SDMA_QUEUE0_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

478

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_SDMA_QUEUE0_RB_CNTL, RB_PRIV, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

506

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_SDMA_QUEUE0_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

508

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_SDMA_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

510

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_SDMA_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

512

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_SDMA_QUEUE0_RB_CNTL, MCU_WPTR_POLL_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

532

doorbell = REG_SET_FIELD(doorbell, SDMA0_SDMA_QUEUE0_DOORBELL, ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

533

doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_SDMA_QUEUE0_DOORBELL_OFFSET,

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

536

doorbell = REG_SET_FIELD(doorbell, SDMA0_SDMA_QUEUE0_DOORBELL, ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

555

temp = REG_SET_FIELD(temp, SDMA0_SDMA_WATCHDOG_CNTL, QUEUE_HANG_COUNT,

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

561

temp = REG_SET_FIELD(temp, SDMA0_SDMA_UTCL1_CNTL, RESP_MODE, 3);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

562

temp = REG_SET_FIELD(temp, SDMA0_SDMA_UTCL1_CNTL, REDO_DELAY, 9);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

576

temp = REG_SET_FIELD(temp, SDMA0_SDMA_MCU_CNTL, HALT, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

577

temp = REG_SET_FIELD(temp, SDMA0_SDMA_MCU_CNTL, RESET, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

582

rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_SDMA_QUEUE0_RB_CNTL, RB_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

586

ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_SDMA_QUEUE0_IB_CNTL, IB_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

588

ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_SDMA_QUEUE0_IB_CNTL, IB_SWAP_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

707

tmp = REG_SET_FIELD(tmp, SDMA0_SDMA_IC_CNTL, GPA, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

716

tmp = REG_SET_FIELD(tmp, SDMA0_SDMA_IC_OP_CNTL, PRIME_ICACHE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

897

m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_SDMA_QUEUE0_DOORBELL, ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/si.c

1603

perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);

drivers/gpu/drm/amd/amdgpu/si.c

1604

perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);

drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c

119

reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_SLAVE_DISABLE, 1);

drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c

120

reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_RESTART_EN, 1);

drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c

121

reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_10BITADDR_MASTER, 0);

drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c

122

reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_10BITADDR_SLAVE, 0);

drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c

128

reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_MAX_SPEED_MODE,

drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c

130

reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_MASTER_MODE, 1);

drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c

312

reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, DAT,

drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c

320

reg = REG_SET_FIELD(reg,

drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c

325

reg = REG_SET_FIELD(reg,

drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c

330

reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, CMD, 0);

drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c

391

reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, DAT, 0);

drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c

393

reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, CMD, 1);

drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c

399

reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD,

drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c

403

reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD,

drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c

450

reg = REG_SET_FIELD(reg, CKSVII2C_IC_ENABLE, ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c

454

reg = REG_SET_FIELD(reg, CKSVII2C_IC_ENABLE, ABORT, 1);

drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c

53

reg = REG_SET_FIELD(reg, SMUIO_PWRMGT, i2c_clk_gate_en, en ? 1 : 0);

drivers/gpu/drm/amd/amdgpu/soc15.c

367

grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);

drivers/gpu/drm/amd/amdgpu/soc15.c

368

grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);

drivers/gpu/drm/amd/amdgpu/soc15.c

369

grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);

drivers/gpu/drm/amd/amdgpu/soc15.c

370

grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);

drivers/gpu/drm/amd/amdgpu/soc15.c

746

perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);

drivers/gpu/drm/amd/amdgpu/soc15.c

747

perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);

drivers/gpu/drm/amd/amdgpu/soc15.c

793

perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,

drivers/gpu/drm/amd/amdgpu/soc15.c

795

perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,

drivers/gpu/drm/amd/amdgpu/soc21.c

273

grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);

drivers/gpu/drm/amd/amdgpu/soc21.c

274

grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);

drivers/gpu/drm/amd/amdgpu/soc21.c

275

grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);

drivers/gpu/drm/amd/amdgpu/soc21.c

276

grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);

drivers/gpu/drm/amd/amdgpu/soc24.c

105

grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);

drivers/gpu/drm/amd/amdgpu/soc24.c

106

grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);

drivers/gpu/drm/amd/amdgpu/soc24.c

107

grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);

drivers/gpu/drm/amd/amdgpu/soc24.c

108

grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);

drivers/gpu/drm/amd/amdgpu/soc_v1_0.c

160

grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);

drivers/gpu/drm/amd/amdgpu/soc_v1_0.c

161

grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);

drivers/gpu/drm/amd/amdgpu/soc_v1_0.c

162

grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);

drivers/gpu/drm/amd/amdgpu/soc_v1_0.c

163

grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);

drivers/gpu/drm/amd/amdgpu/tonga_ih.c

117

interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);

drivers/gpu/drm/amd/amdgpu/tonga_ih.c

119

interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);

drivers/gpu/drm/amd/amdgpu/tonga_ih.c

126

ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);

drivers/gpu/drm/amd/amdgpu/tonga_ih.c

127

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);

drivers/gpu/drm/amd/amdgpu/tonga_ih.c

129

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/tonga_ih.c

130

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);

drivers/gpu/drm/amd/amdgpu/tonga_ih.c

133

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 1);

drivers/gpu/drm/amd/amdgpu/tonga_ih.c

147

ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,

drivers/gpu/drm/amd/amdgpu/tonga_ih.c

149

ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,

drivers/gpu/drm/amd/amdgpu/tonga_ih.c

152

ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,

drivers/gpu/drm/amd/amdgpu/tonga_ih.c

214

wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);

drivers/gpu/drm/amd/amdgpu/tonga_ih.c

225

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);

drivers/gpu/drm/amd/amdgpu/tonga_ih.c

231

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);

drivers/gpu/drm/amd/amdgpu/tonga_ih.c

400

srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET,

drivers/gpu/drm/amd/amdgpu/tonga_ih.c

64

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/tonga_ih.c

65

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1);

drivers/gpu/drm/amd/amdgpu/tonga_ih.c

81

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/tonga_ih.c

82

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0);

drivers/gpu/drm/amd/amdgpu/umc_v12_0.c

456

odecc_cnt_sel = REG_SET_FIELD(odecc_cnt_sel, UMCCH0_OdEccCntSel,

drivers/gpu/drm/amd/amdgpu/umc_v6_1.c

121

ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel,

drivers/gpu/drm/amd/amdgpu/umc_v6_1.c

134

ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel,

drivers/gpu/drm/amd/amdgpu/umc_v6_1.c

198

ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel,

drivers/gpu/drm/amd/amdgpu/umc_v6_1.c

208

ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel,

drivers/gpu/drm/amd/amdgpu/umc_v6_1.c

414

ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel,

drivers/gpu/drm/amd/amdgpu/umc_v6_1.c

417

ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel,

drivers/gpu/drm/amd/amdgpu/umc_v6_1.c

424

ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel,

drivers/gpu/drm/amd/amdgpu/umc_v6_1.c

52

rsmu_umc_val = REG_SET_FIELD(rsmu_umc_val,

drivers/gpu/drm/amd/amdgpu/umc_v6_1.c

67

rsmu_umc_val = REG_SET_FIELD(rsmu_umc_val,

drivers/gpu/drm/amd/amdgpu/umc_v6_7.c

282

ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel,

drivers/gpu/drm/amd/amdgpu/umc_v6_7.c

292

ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel,

drivers/gpu/drm/amd/amdgpu/umc_v6_7.c

380

ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel,

drivers/gpu/drm/amd/amdgpu/umc_v6_7.c

393

ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel,

drivers/gpu/drm/amd/amdgpu/umc_v8_10.c

311

ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_GeccErrCntSel,

drivers/gpu/drm/amd/amdgpu/umc_v8_14.c

136

ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_GeccErrCntSel,

drivers/gpu/drm/amd/amdgpu/umc_v8_7.c

194

ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel,

drivers/gpu/drm/amd/amdgpu/umc_v8_7.c

207

ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel,

drivers/gpu/drm/amd/amdgpu/umc_v8_7.c

253

ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_GeccErrCntSel,

drivers/gpu/drm/amd/amdgpu/umc_v8_7.c

263

ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_GeccErrCntSel,

drivers/gpu/drm/amd/amdgpu/umc_v8_7.c

403

ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_GeccErrCntSel,

drivers/gpu/drm/amd/amdgpu/umc_v8_7.c

406

ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_GeccErrCntSel,

drivers/gpu/drm/amd/amdgpu/umc_v8_7.c

413

ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_GeccErrCntSel,

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

130

data = REG_SET_FIELD(data, UVD_UMSCH_FORCE, IC_FORCE_GPUVM, 1);

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

131

data = REG_SET_FIELD(data, UVD_UMSCH_FORCE, DC_FORCE_GPUVM, 1);

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

135

data = REG_SET_FIELD(data, VCN_MES_IC_OP_CNTL, PRIME_ICACHE, 0);

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

136

data = REG_SET_FIELD(data, VCN_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1);

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

140

data = REG_SET_FIELD(data, VCN_MES_IC_OP_CNTL, PRIME_ICACHE, 1);

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

155

data = REG_SET_FIELD(data, VCN_MES_CNTL, MES_INVALIDATE_ICACHE, 0);

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

156

data = REG_SET_FIELD(data, VCN_MES_CNTL, MES_PIPE0_RESET, 0);

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

157

data = REG_SET_FIELD(data, VCN_MES_CNTL, MES_HALT, 0);

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

158

data = REG_SET_FIELD(data, VCN_MES_CNTL, MES_PIPE0_ACTIVE, 1);

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

190

data = REG_SET_FIELD(data, VCN_AGDB_CTRL0, OFFSET,

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

192

data = REG_SET_FIELD(data, VCN_AGDB_CTRL0, EN, 1);

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

196

data = REG_SET_FIELD(data, VCN_AGDB_CTRL1, OFFSET,

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

198

data = REG_SET_FIELD(data, VCN_AGDB_CTRL1, EN, 1);

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

202

data = REG_SET_FIELD(data, VCN_AGDB_CTRL2, OFFSET,

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

204

data = REG_SET_FIELD(data, VCN_AGDB_CTRL2, EN, 1);

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

208

data = REG_SET_FIELD(data, VCN_AGDB_CTRL3, OFFSET,

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

210

data = REG_SET_FIELD(data, VCN_AGDB_CTRL3, EN, 1);

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

221

data = REG_SET_FIELD(data, VCN_UMSCH_RB_DB_CTRL, OFFSET, ring->doorbell_index);

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

222

data = REG_SET_FIELD(data, VCN_UMSCH_RB_DB_CTRL, EN, 1);

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

251

data = REG_SET_FIELD(data, VCN_RB_ENABLE, UMSCH_RB_EN, 0);

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

255

data = REG_SET_FIELD(data, VCN_UMSCH_RB_DB_CTRL, EN, 0);

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

73

data = REG_SET_FIELD(data, UMSCH_MES_RESET_CTRL, MES_CORE_SOFT_RESET, 0);

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

77

data = REG_SET_FIELD(data, VCN_MES_CNTL, MES_INVALIDATE_ICACHE, 1);

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

78

data = REG_SET_FIELD(data, VCN_MES_CNTL, MES_PIPE0_RESET, 1);

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

79

data = REG_SET_FIELD(data, VCN_MES_CNTL, MES_PIPE0_ACTIVE, 0);

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

80

data = REG_SET_FIELD(data, VCN_MES_CNTL, MES_HALT, 1);

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

84

data = REG_SET_FIELD(data, VCN_MES_IC_BASE_CNTL, VMID, 0);

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

85

data = REG_SET_FIELD(data, VCN_MES_IC_BASE_CNTL, EXE_DISABLE, 0);

drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

86

data = REG_SET_FIELD(data, VCN_MES_IC_BASE_CNTL, CACHE_POLICY, 0);

drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c

421

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);

drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c

422

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);

drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c

423

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);

drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c

424

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);

drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c

425

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);

drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c

426

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);

drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

1177

srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_UVD, 1);

drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

839

tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);

drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

840

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);

drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

841

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);

drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

842

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);

drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

843

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);

drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

844

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);

drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

1086

tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);

drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

1087

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);

drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

1088

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);

drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

1089

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);

drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

1090

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);

drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

1091

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);

drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

919

tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, size);

drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

920

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

655

srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE0, 1);

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

656

srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE1, 1);

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

660

srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE0, 1);

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

661

srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE1, 1);

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

1128

tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

1129

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

1130

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

1131

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

1132

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

964

tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

965

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

966

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

967

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

968

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

1132

tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

1133

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

1134

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

1135

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

1136

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

2078

tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, tmp);

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

2079

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

2080

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

2081

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

2082

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

953

tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

954

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

955

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

956

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

957

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

1108

tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

1109

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

1110

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

1111

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

1112

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

1298

tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

1299

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

1300

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

1301

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

1302

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

1521

tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

1522

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

1523

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

1524

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);

drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

1525

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

1139

tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

1140

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

1141

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

1142

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

1143

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

1330

tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

1331

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

1332

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

1333

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

1334

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

1520

tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, tmp);

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

1521

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

1522

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

1523

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

1524

tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);

drivers/gpu/drm/amd/amdgpu/vega10_ih.c

106

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0));

drivers/gpu/drm/amd/amdgpu/vega10_ih.c

107

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_GPU_TS_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/vega10_ih.c

110

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));

drivers/gpu/drm/amd/amdgpu/vega10_ih.c

162

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/vega10_ih.c

164

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/vega10_ih.c

166

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/vega10_ih.c

168

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);

drivers/gpu/drm/amd/amdgpu/vega10_ih.c

172

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/vega10_ih.c

174

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1);

drivers/gpu/drm/amd/amdgpu/vega10_ih.c

175

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0);

drivers/gpu/drm/amd/amdgpu/vega10_ih.c

176

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);

drivers/gpu/drm/amd/amdgpu/vega10_ih.c

186

ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,

drivers/gpu/drm/amd/amdgpu/vega10_ih.c

189

ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,

drivers/gpu/drm/amd/amdgpu/vega10_ih.c

193

ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,

drivers/gpu/drm/amd/amdgpu/vega10_ih.c

223

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled);

drivers/gpu/drm/amd/amdgpu/vega10_ih.c

225

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/vega10_ih.c

278

ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN,

drivers/gpu/drm/amd/amdgpu/vega10_ih.c

360

wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);

drivers/gpu/drm/amd/amdgpu/vega10_ih.c

372

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);

drivers/gpu/drm/amd/amdgpu/vega10_ih.c

378

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);

drivers/gpu/drm/amd/amdgpu/vega10_ih.c

589

data = REG_SET_FIELD(data, IH_CLK_CTRL,

drivers/gpu/drm/amd/amdgpu/vega10_ih.c

592

data = REG_SET_FIELD(data, IH_CLK_CTRL,

drivers/gpu/drm/amd/amdgpu/vega10_ih.c

594

data = REG_SET_FIELD(data, IH_CLK_CTRL,

drivers/gpu/drm/amd/amdgpu/vega10_ih.c

596

data = REG_SET_FIELD(data, IH_CLK_CTRL,

drivers/gpu/drm/amd/amdgpu/vega10_ih.c

598

data = REG_SET_FIELD(data, IH_CLK_CTRL,

drivers/gpu/drm/amd/amdgpu/vega10_ih.c

600

data = REG_SET_FIELD(data, IH_CLK_CTRL,

drivers/gpu/drm/amd/amdgpu/vega20_ih.c

114

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0));

drivers/gpu/drm/amd/amdgpu/vega20_ih.c

115

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_GPU_TS_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/vega20_ih.c

121

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);

drivers/gpu/drm/amd/amdgpu/vega20_ih.c

130

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);

drivers/gpu/drm/amd/amdgpu/vega20_ih.c

141

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);

drivers/gpu/drm/amd/amdgpu/vega20_ih.c

146

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));

drivers/gpu/drm/amd/amdgpu/vega20_ih.c

198

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/vega20_ih.c

200

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/vega20_ih.c

202

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/vega20_ih.c

204

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);

drivers/gpu/drm/amd/amdgpu/vega20_ih.c

208

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

drivers/gpu/drm/amd/amdgpu/vega20_ih.c

210

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1);

drivers/gpu/drm/amd/amdgpu/vega20_ih.c

211

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0);

drivers/gpu/drm/amd/amdgpu/vega20_ih.c

212

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);

drivers/gpu/drm/amd/amdgpu/vega20_ih.c

222

ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,

drivers/gpu/drm/amd/amdgpu/vega20_ih.c

225

ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,

drivers/gpu/drm/amd/amdgpu/vega20_ih.c

229

ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,

drivers/gpu/drm/amd/amdgpu/vega20_ih.c

259

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled);

drivers/gpu/drm/amd/amdgpu/vega20_ih.c

261

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/vega20_ih.c

290

val = REG_SET_FIELD(val, IH_DOORBELL_RPTR, OFFSET, doorbell_index);

drivers/gpu/drm/amd/amdgpu/vega20_ih.c

291

val = REG_SET_FIELD(val, IH_DOORBELL_RPTR, ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/vega20_ih.c

326

ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN,

drivers/gpu/drm/amd/amdgpu/vega20_ih.c

340

ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN,

drivers/gpu/drm/amd/amdgpu/vega20_ih.c

442

wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);

drivers/gpu/drm/amd/amdgpu/vega20_ih.c

456

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);

drivers/gpu/drm/amd/amdgpu/vega20_ih.c

462

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);

drivers/gpu/drm/amd/amdgpu/vega20_ih.c

685

data = REG_SET_FIELD(data, IH_CLK_CTRL,

drivers/gpu/drm/amd/amdgpu/vega20_ih.c

687

data = REG_SET_FIELD(data, IH_CLK_CTRL,

drivers/gpu/drm/amd/amdgpu/vega20_ih.c

689

data = REG_SET_FIELD(data, IH_CLK_CTRL,

drivers/gpu/drm/amd/amdgpu/vega20_ih.c

691

data = REG_SET_FIELD(data, IH_CLK_CTRL,

drivers/gpu/drm/amd/amdgpu/vega20_ih.c

693

data = REG_SET_FIELD(data, IH_CLK_CTRL,

drivers/gpu/drm/amd/amdgpu/vega20_ih.c

695

data = REG_SET_FIELD(data, IH_CLK_CTRL,

drivers/gpu/drm/amd/amdgpu/vega20_ih.c

697

data = REG_SET_FIELD(data, IH_CLK_CTRL,

drivers/gpu/drm/amd/amdgpu/vi.c

1289

tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 1);

drivers/gpu/drm/amd/amdgpu/vi.c

1291

tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 0);

drivers/gpu/drm/amd/amdgpu/vi.c

1367

perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);

drivers/gpu/drm/amd/amdgpu/vi.c

1368

perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);

drivers/gpu/drm/amd/amdgpu/vi.c

582

srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, PIPEID, pipe);

drivers/gpu/drm/amd/amdgpu/vi.c

583

srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, MEID, me);

drivers/gpu/drm/amd/amdgpu/vi.c

584

srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, vmid);

drivers/gpu/drm/amd/amdgpu/vi.c

585

srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, QUEUEID, queue);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

108

f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, TH1_CHECKSUM_CLR, 0);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

109

f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, TH0_CHECKSUM_CLR, 0);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

146

reg_data = REG_SET_FIELD(reg_data, VPEC_PG_CNTL, PG_EN, 0);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

168

reg_data = REG_SET_FIELD(reg_data, VPEC_PG_CNTL, PG_EN, 1);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

173

f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, HALT, 0);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

174

f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, TH1_RESET, 0);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

193

rb_cntl = REG_SET_FIELD(rb_cntl, VPEC_QUEUE0_RB_CNTL, RB_SIZE, rb_bufsz);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

194

rb_cntl = REG_SET_FIELD(rb_cntl, VPEC_QUEUE0_RB_CNTL, RB_PRIV, 1);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

195

rb_cntl = REG_SET_FIELD(rb_cntl, VPEC_QUEUE0_RB_CNTL, RB_VMID, 0);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

210

rb_cntl = REG_SET_FIELD(rb_cntl, VPEC_QUEUE0_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

225

doorbell_offset = REG_SET_FIELD(doorbell_offset, VPEC_QUEUE0_DOORBELL_OFFSET, OFFSET, ring->doorbell_index + i*4);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

229

doorbell = REG_SET_FIELD(doorbell, VPEC_QUEUE0_DOORBELL, ENABLE, ring->use_doorbell ? 1 : 0);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

234

rb_cntl = REG_SET_FIELD(rb_cntl, VPEC_QUEUE0_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

235

rb_cntl = REG_SET_FIELD(rb_cntl, VPEC_QUEUE0_RB_CNTL, RB_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

239

ib_cntl = REG_SET_FIELD(ib_cntl, VPEC_QUEUE0_IB_CNTL, IB_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

259

queue_reset = REG_SET_FIELD(queue_reset, VPEC_QUEUE_RESET_REQ, QUEUE0_RESET, 1);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

284

vpe_cntl = REG_SET_FIELD(vpe_cntl, VPEC_CNTL, TRAP_ENABLE,

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

70

ret = REG_SET_FIELD(ret, VPEC_CNTL, UMSCH_INT_ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

74

reg_data = REG_SET_FIELD(reg_data, VPEC_CNTL2, IB_FIFO_WATERMARK, 1);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

84

f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, HALT, 0);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

85

f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, TH1_RESET, 0);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

96

f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, HALT, 1);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

97

f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, TH1_RESET, 1);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

98

f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, TH1_CHECKSUM_CLR, 1);

drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c

99

f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, TH0_CHECKSUM_CLR, 1);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

110

vpe_colla_cntl = REG_SET_FIELD(vpe_colla_cntl, VPEC_COLLABORATE_CNTL,

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

115

vpe_colla_cfg = REG_SET_FIELD(vpe_colla_cfg, VPEC_COLLABORATE_CFG, MASTER_ID, 0);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

116

vpe_colla_cfg = REG_SET_FIELD(vpe_colla_cfg, VPEC_COLLABORATE_CFG, MASTER_EN, enable ? 1 : 0);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

117

vpe_colla_cfg = REG_SET_FIELD(vpe_colla_cfg, VPEC_COLLABORATE_CFG, SLAVE0_ID, 1);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

118

vpe_colla_cfg = REG_SET_FIELD(vpe_colla_cfg, VPEC_COLLABORATE_CFG, SLAVE0_EN, enable ? 1 : 0);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

140

ret = REG_SET_FIELD(ret, VPEC_CNTL, UMSCH_INT_ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

163

f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, HALT, 0);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

164

f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, TH1_RESET, 0);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

219

rb_cntl = REG_SET_FIELD(rb_cntl, VPEC_QUEUE0_RB_CNTL, RB_SIZE, rb_bufsz);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

220

rb_cntl = REG_SET_FIELD(rb_cntl, VPEC_QUEUE0_RB_CNTL, RB_PRIV, 1);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

221

rb_cntl = REG_SET_FIELD(rb_cntl, VPEC_QUEUE0_RB_CNTL, RB_VMID, 0);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

236

rb_cntl = REG_SET_FIELD(rb_cntl, VPEC_QUEUE0_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

251

doorbell_offset = REG_SET_FIELD(doorbell_offset, VPEC_QUEUE0_DOORBELL_OFFSET, OFFSET, ring->doorbell_index + i*4);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

255

doorbell = REG_SET_FIELD(doorbell, VPEC_QUEUE0_DOORBELL, ENABLE, ring->use_doorbell ? 1 : 0);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

260

rb_cntl = REG_SET_FIELD(rb_cntl, VPEC_QUEUE0_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

261

rb_cntl = REG_SET_FIELD(rb_cntl, VPEC_QUEUE0_RB_CNTL, RB_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

265

ib_cntl = REG_SET_FIELD(ib_cntl, VPEC_QUEUE0_IB_CNTL, IB_ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

288

queue_reset = REG_SET_FIELD(queue_reset, VPEC_QUEUE_RESET_REQ, QUEUE0_RESET, 1);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

322

vpe_cntl = REG_SET_FIELD(vpe_cntl, VPEC_CNTL, TRAP_ENABLE,

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

80

f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, HALT, halt ? 1 : 0);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

81

f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, TH1_RESET, halt ? 1 : 0);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

842

data = REG_SET_FIELD(data, DIDT_SQ_EDC_CTRL, EDC_EN, en);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

843

data = REG_SET_FIELD(data, DIDT_SQ_EDC_CTRL, EDC_SW_RST, ~en);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

849

data = REG_SET_FIELD(data, DIDT_DB_EDC_CTRL, EDC_EN, en);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

850

data = REG_SET_FIELD(data, DIDT_DB_EDC_CTRL, EDC_SW_RST, ~en);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

856

data = REG_SET_FIELD(data, DIDT_TD_EDC_CTRL, EDC_EN, en);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

857

data = REG_SET_FIELD(data, DIDT_TD_EDC_CTRL, EDC_SW_RST, ~en);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

863

data = REG_SET_FIELD(data, DIDT_TCP_EDC_CTRL, EDC_EN, en);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

864

data = REG_SET_FIELD(data, DIDT_TCP_EDC_CTRL, EDC_SW_RST, ~en);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

870

data = REG_SET_FIELD(data, DIDT_DBR_EDC_CTRL, EDC_EN, en);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c

871

data = REG_SET_FIELD(data, DIDT_DBR_EDC_CTRL, EDC_SW_RST, ~en);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

141

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

144

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

161

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

165

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

274

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

322

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

391

val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

392

val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

393

val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, high);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

394

val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, low);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

415

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c

421

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c

191

val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c

192

val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c

193

val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, high);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c

194

val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, low);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c

163

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c

206

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c

95

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c

98

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),

drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1117

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2_ARCT),

drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1120

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2_ARCT),

drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1190

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0_ARCT),

drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

1212

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL_ARCT),

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1091

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1094

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1119

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1148

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1272

val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1);

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1273

val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1);

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1280

val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1292

val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1293

val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1294

val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1295

val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1296

val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1297

val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1308

val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1309

val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1313

val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1368

data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1045

REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2),

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1048

REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2),

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1076

REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL0),

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1127

REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_TACH_CTRL),

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1158

val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1159

val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1166

val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1178

val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1179

val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1180

val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1181

val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1182

val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1183

val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1194

val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1195

val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1199

val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1261

data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1299

data = REG_SET_FIELD(data, THM_THERMAL_INT_CTRL,

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1312

data = REG_SET_FIELD(data, THM_THERMAL_INT_CTRL,

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1836

data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1886

val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1893

val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1894

val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1898

val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

816

val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

817

val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

825

val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

829

val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

841

val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

842

val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

843

val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

844

val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

845

val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

846

val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

858

val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

859

val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

863

val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

867

val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

868

val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

872

val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

921

data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

936

data = REG_SET_FIELD(data, THM_THERMAL_INT_CTRL,

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

949

data = REG_SET_FIELD(data, THM_THERMAL_INT_CTRL,

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c

768

val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c

772

val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c

781

val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c

782

val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c

786

val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c

790

val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c

791

val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c

795

val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c

1175

data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c

1225

val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c

1232

val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c

1233

val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c

1237

val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);

drivers/gpu/drm/amd/ras/rascore/ras_nbio_v7_9.c

66

bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,

drivers/gpu/drm/amd/ras/rascore/ras_nbio_v7_9.c

90

bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,