RFPGA0_XCD_RFINTERFACESW
RFPGA0_XCD_RFINTERFACESW, 0xb68, 0xb6c,
rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;
rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;
RFPGA0_XCD_RFINTERFACESW,
rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;
rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;
rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;
rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;
RFPGA0_XCD_RFINTERFACESW, ROFDM0_TRXPATHENABLE,
rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22204000);
RFPGA0_XCD_RFINTERFACESW, ROFDM0_TRXPATHENABLE,
rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22208000);
RFPGA0_XCD_RFINTERFACESW, ROFDM0_TRXPATHENABLE,
rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22204000);
RFPGA0_XCD_RFINTERFACESW, ROFDM0_TRXPATHENABLE,
rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22208000);
RFPGA0_XCD_RFINTERFACESW, 0xb68, 0xb6c,
rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22208200);
rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;
rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;
reg_874 = (rtl_get_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
RFPGA0_XCD_RFINTERFACESW, 0xb68, 0xb6c,
rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;
rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;