RFPGA0_XAB_RFINTERFACESW
rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BIT(8) | BIT(9), 0);
rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD,
rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x0f600700);
rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD,
RFPGA0_XAB_RFINTERFACESW, RFPGA0_XA_RFINTERFACEOE,
RFPGA0_XAB_RFINTERFACESW, RFPGA0_XA_RFINTERFACEOE,
rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x07000f60);
rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x07000f60);
rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD,
rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x0f600700);
rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD,
RFPGA0_XAB_RFINTERFACESW, RFPGA0_XA_RFINTERFACEOE,
RFPGA0_XAB_RFINTERFACESW, RFPGA0_XA_RFINTERFACEOE,
rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BIT(10), 0x01);
rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BIT(26), 0x01);
rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BIT(8) | BIT(9), 0);
rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;