drivers/gpu/drm/i915/display/i9xx_wm.c

185

val = enable ? REG_MASKED_FIELD_ENABLE(FW_BLC_SELF_EN) :

drivers/gpu/drm/i915/display/i9xx_wm.c

196

val = enable ? REG_MASKED_FIELD_ENABLE(INSTPM_SELF_EN) :

drivers/gpu/drm/i915/display/intel_display_irq.c

1635

REG_MASKED_FIELD_ENABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE));

drivers/gpu/drm/i915/gt/gen6_ppgtt.c

70

REG_MASKED_FIELD_ENABLE(GFX_PPGTT_ENABLE));

drivers/gpu/drm/i915/gt/intel_engine_cs.c

1236

engine->tlb_inv.request = REG_MASKED_FIELD_ENABLE(val);

drivers/gpu/drm/i915/gt/intel_engine_cs.c

1631

intel_uncore_write_fw(uncore, mode, REG_MASKED_FIELD_ENABLE(STOP_RING));

drivers/gpu/drm/i915/gt/intel_engine_cs.c

1639

REG_MASKED_FIELD_ENABLE(GEN12_GFX_PREFETCH_DISABLE));

drivers/gpu/drm/i915/gt/intel_engine_cs.c

2555

REG_MASKED_FIELD_ENABLE(GEN12_RCU_MODE_CCS_ENABLE));

drivers/gpu/drm/i915/gt/intel_execlists_submission.c

2937

mode = REG_MASKED_FIELD_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE);

drivers/gpu/drm/i915/gt/intel_execlists_submission.c

2939

mode = REG_MASKED_FIELD_ENABLE(GFX_RUN_LIST_ENABLE);

drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c

919

REG_MASKED_FIELD_ENABLE(ARB_MODE_SWIZZLE_SNB));

drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c

923

REG_MASKED_FIELD_ENABLE(ARB_MODE_SWIZZLE_IVB));

drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c

927

REG_MASKED_FIELD_ENABLE(ARB_MODE_SWIZZLE_BDW));

drivers/gpu/drm/i915/gt/intel_lrc.c

1347

*cs++ = REG_MASKED_FIELD_ENABLE(INSTRUCTION_STATE_CACHE_INVALIDATE);

drivers/gpu/drm/i915/gt/intel_lrc.c

1745

REG_MASKED_FIELD_ENABLE(FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX),

drivers/gpu/drm/i915/gt/intel_lrc.c

1751

REG_MASKED_FIELD_ENABLE(_3D_CHICKEN_SF_PROVOKING_VERTEX_FIX),

drivers/gpu/drm/i915/gt/intel_lrc.c

849

ctl = REG_MASKED_FIELD_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH);

drivers/gpu/drm/i915/gt/intel_lrc.c

858

ctl |= REG_MASKED_FIELD_ENABLE(GEN12_CTX_CTRL_RUNALONE_MODE);

drivers/gpu/drm/i915/gt/intel_rc6.c

381

REG_MASKED_FIELD_ENABLE(VLV_COUNT_RANGE_HIGH |

drivers/gpu/drm/i915/gt/intel_rc6.c

406

REG_MASKED_FIELD_ENABLE(VLV_COUNT_RANGE_HIGH |

drivers/gpu/drm/i915/gt/intel_rc6.c

766

REG_MASKED_FIELD_ENABLE(VLV_COUNT_RANGE_HIGH));

drivers/gpu/drm/i915/gt/intel_rc6.c

776

REG_MASKED_FIELD_ENABLE(VLV_COUNT_RANGE_HIGH));

drivers/gpu/drm/i915/gt/intel_reset.c

591

intel_uncore_write_fw(uncore, reg, REG_MASKED_FIELD_ENABLE(request));

drivers/gpu/drm/i915/gt/intel_ring_submission.c

1055

REG_MASKED_FIELD_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));

drivers/gpu/drm/i915/gt/intel_ring_submission.c

131

REG_MASKED_FIELD_ENABLE(INSTPM_TLB_INVALIDATE | INSTPM_SYNC_FLUSH));

drivers/gpu/drm/i915/gt/intel_ring_submission.c

174

REG_MASKED_FIELD_ENABLE(GFX_PPGTT_ENABLE));

drivers/gpu/drm/i915/gt/intel_ring_submission.c

721

*cs++ = REG_MASKED_FIELD_ENABLE(INSTPM_TLB_INVALIDATE);

drivers/gpu/drm/i915/gt/intel_ring_submission.c

770

*cs++ = REG_MASKED_FIELD_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE);

drivers/gpu/drm/i915/gt/intel_workarounds.c

1134

REG_MASKED_FIELD_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE),

drivers/gpu/drm/i915/gt/intel_workarounds.c

2275

REG_MASKED_FIELD_ENABLE(DIS_ATOMIC_CHAINING_TYPED_WRITES),

drivers/gpu/drm/i915/gt/intel_workarounds.c

2666

0, REG_MASKED_FIELD_ENABLE(VS_TIMER_DISPATCH),

drivers/gpu/drm/i915/gt/intel_workarounds.c

2682

0, REG_MASKED_FIELD_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE),

drivers/gpu/drm/i915/gt/intel_workarounds.c

2882

REG_MASKED_FIELD_ENABLE(ENABLE_PREFETCH_INTO_IC),

drivers/gpu/drm/i915/gt/intel_workarounds.c

303

wa_add(wal, reg, 0, REG_MASKED_FIELD_ENABLE(val), val, true);

drivers/gpu/drm/i915/gt/intel_workarounds.c

309

wa_mcr_add(wal, reg, 0, REG_MASKED_FIELD_ENABLE(val), val, true);

drivers/gpu/drm/i915/gt/intel_workarounds.c

669

REG_MASKED_FIELD_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE),

drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c

4417

REG_MASKED_FIELD_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE));

drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c

1068

REG_MASKED_FIELD_ENABLE(dma_flags | START_DMA));

drivers/gpu/drm/i915/gvt/handlers.c

2049

(*(u32 *)p_data) &= ~REG_MASKED_FIELD_ENABLE(1);

drivers/gpu/drm/i915/gvt/handlers.c

2052

(*(u32 *)p_data) &= ~REG_MASKED_FIELD_ENABLE(2);

drivers/gpu/drm/i915/gvt/handlers.c

2154

(*(u32 *)p_data) &= ~REG_MASKED_FIELD_ENABLE(0x18);

drivers/gpu/drm/i915/gvt/handlers.c

2536

~REG_MASKED_FIELD_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,

drivers/gpu/drm/i915/gvt/mmio_context.c

479

REG_MASKED_FIELD_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);

drivers/gpu/drm/i915/gvt/reg.h

94

(((_val) & REG_MASKED_FIELD_ENABLE(_b)) == REG_MASKED_FIELD_ENABLE(_b))

drivers/gpu/drm/i915/i915_perf.c

2639

REG_MASKED_FIELD_ENABLE(GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE) :

drivers/gpu/drm/i915/i915_perf.c

2829

REG_MASKED_FIELD_ENABLE(GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS |

drivers/gpu/drm/i915/i915_perf.c

2852

return REG_MASKED_FIELD_ENABLE(GEN12_OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS);

drivers/gpu/drm/i915/i915_perf.c

2873

REG_MASKED_FIELD_ENABLE(STALL_DOP_GATING_DISABLE));

drivers/gpu/drm/i915/i915_perf.c

2875

REG_MASKED_FIELD_ENABLE(GEN12_DISABLE_DOP_GATING));

drivers/gpu/drm/i915/i915_perf.c

2880

REG_MASKED_FIELD_ENABLE(GEN12_OAG_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS |

drivers/gpu/drm/i915/i915_perf.c

4478

val = val & ~REG_MASKED_FIELD_ENABLE(GEN8_ST_PO_DISABLE);

drivers/gpu/drm/i915/i915_perf.c

4486

val = val & ~REG_MASKED_FIELD_ENABLE(HSW_WAIT_FOR_RC6_EXIT_ENABLE);

drivers/gpu/drm/i915/intel_clock_gating.c

221

REG_MASKED_FIELD_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));

drivers/gpu/drm/i915/intel_clock_gating.c

268

REG_MASKED_FIELD_ENABLE(DOP_CLOCK_GATING_DISABLE));

drivers/gpu/drm/i915/intel_clock_gating.c

272

REG_MASKED_FIELD_ENABLE(DOP_CLOCK_GATING_DISABLE));

drivers/gpu/drm/i915/intel_clock_gating.c

274

REG_MASKED_FIELD_ENABLE(DOP_CLOCK_GATING_DISABLE));

drivers/gpu/drm/i915/intel_clock_gating.c

307

REG_MASKED_FIELD_ENABLE(DOP_CLOCK_GATING_DISABLE));

drivers/gpu/drm/i915/intel_clock_gating.c

342

REG_MASKED_FIELD_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));

drivers/gpu/drm/i915/intel_clock_gating.c

379

REG_MASKED_FIELD_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));

drivers/gpu/drm/i915/intel_clock_gating.c

391

REG_MASKED_FIELD_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));

drivers/gpu/drm/i915/intel_clock_gating.c

404

REG_MASKED_FIELD_ENABLE(ECO_GATING_CX_ONLY));

drivers/gpu/drm/i915/intel_clock_gating.c

411

intel_uncore_write(&i915->uncore, INSTPM, REG_MASKED_FIELD_ENABLE(INSTPM_AGPBUSY_INT_EN));

drivers/gpu/drm/i915/intel_clock_gating.c

415

REG_MASKED_FIELD_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));

drivers/gpu/drm/i915/intel_clock_gating.c

418

REG_MASKED_FIELD_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));

drivers/gpu/drm/i915/intel_clock_gating.c

426

intel_uncore_write(&i915->uncore, MI_STATE, REG_MASKED_FIELD_ENABLE(MI_AGPBUSY_INT_EN) |

drivers/gpu/drm/i915/intel_clock_gating.c

430

REG_MASKED_FIELD_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));

drivers/gpu/drm/i915/intel_clock_gating.c

440

REG_MASKED_FIELD_ENABLE(SCPD_FBC_IGNORE_3D));

drivers/gpu/drm/i915/intel_clock_gating.c

446

REG_MASKED_FIELD_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |

drivers/gpu/drm/i915/intel_clock_gating.c

447

REG_MASKED_FIELD_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));

drivers/gpu/drm/i915/intel_uncore.c

135

#define fw_set(d, val) writel(REG_MASKED_FIELD_ENABLE((val)), (d)->reg_set)

drivers/gpu/drm/i915/pxp/intel_pxp.c

69

u32 val = enable ? REG_MASKED_FIELD_ENABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES) :

drivers/gpu/drm/xe/xe_eu_stall.c

459

write_ptr_reg = REG_MASKED_FIELD_ENABLE(XEHPC_EUSTALL_REPORT_OVERFLOW_DROP);

drivers/gpu/drm/xe/xe_eu_stall.c

698

REG_MASKED_FIELD_ENABLE(DISABLE_DOP_GATING));

drivers/gpu/drm/xe/xe_lrc.c

1243

*cmd++ = REG_MASKED_FIELD_ENABLE(INSTRUCTION_STATE_CACHE_INVALIDATE);

drivers/gpu/drm/xe/xe_lrc.c

1565

REG_MASKED_FIELD_ENABLE(CTX_CTRL_RUN_ALONE));

drivers/gpu/drm/xe/xe_lrc.c

1570

REG_MASKED_FIELD_ENABLE(CTX_CTRL_PXP_ENABLE));

drivers/gpu/drm/xe/xe_lrc.c

1613

state_cache_perf_fix[2] = REG_MASKED_FIELD_ENABLE(DISABLE_STATE_CACHE_PERF_FIX);

drivers/gpu/drm/xe/xe_lrc.c

651

regs[CTX_CONTEXT_CONTROL] = REG_MASKED_FIELD_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |

drivers/gpu/drm/xe/xe_lrc.c

656

REG_MASKED_FIELD_ENABLE(CTX_CTRL_INDIRECT_RING_STATE_ENABLE);

drivers/gpu/drm/xe/xe_oa.c

1092

return REG_MASKED_FIELD_ENABLE(OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS);

drivers/gpu/drm/xe/xe_oa.c

1098

return REG_MASKED_FIELD_ENABLE(OAG_OA_DEBUG_BUF_SIZE_SELECT);

drivers/gpu/drm/xe/xe_oa.c

1115

REG_MASKED_FIELD_ENABLE(STALL_DOP_GATING_DISABLE));

drivers/gpu/drm/xe/xe_oa.c

1117

REG_MASKED_FIELD_ENABLE(DISABLE_DOP_GATING));

drivers/gpu/drm/xe/xe_oa.c

1132

REG_MASKED_FIELD_ENABLE(oa_debug) |

drivers/gpu/drm/xe/xe_oa.c

781

REG_MASKED_FIELD_ENABLE(CTX_CTRL_OAC_CONTEXT_ENABLE) :

drivers/gpu/drm/xe/xe_oa.c

806

REG_MASKED_FIELD_ENABLE(CTX_CTRL_OAC_CONTEXT_ENABLE | CTX_CTRL_RUN_ALONE) :

drivers/gpu/drm/xe/xe_oa.c

838

return REG_MASKED_FIELD_ENABLE(OAG_OA_DEBUG_DISABLE_MMIO_TRG);

drivers/gpu/drm/xe/xe_pxp.c

317

u32 val = enable ? REG_MASKED_FIELD_ENABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES) :

drivers/gpu/drm/xe/xe_uc_fw.c

894

REG_MASKED_FIELD_ENABLE(dma_flags | START_DMA));