AZX_ML_BASE
val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
hlink->ml_addr = bus->mlcap + AZX_ML_BASE +
hlink->ml_addr = bus->mlcap + AZX_ML_BASE + (AZX_ML_INTERVAL * index);