REG_FPGA0_IQK
val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0);
rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0);
rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x808000);
rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0);
rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0);
rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x808000);
rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0);
rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0);
rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x808000);
rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0);
rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0);
rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x000000);
rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x808000);
rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0);
rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0);
rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x808000);
rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0);
rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0);
rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x808000);
rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0);
rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0);
rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x808000);
val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x0);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0);