drivers/accel/ivpu/ivpu_hw_btrs.c

17

#define BTRS_MTL_IRQ_MASK ((REG_FLD(VPU_HW_BTRS_MTL_INTERRUPT_STAT, ATS_ERR)) | \

drivers/accel/ivpu/ivpu_hw_btrs.c

18

(REG_FLD(VPU_HW_BTRS_MTL_INTERRUPT_STAT, UFI_ERR)))

drivers/accel/ivpu/ivpu_hw_btrs.c

20

#define BTRS_LNL_IRQ_MASK ((REG_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, ATS_ERR)) | \

drivers/accel/ivpu/ivpu_hw_btrs.c

21

(REG_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, CFI0_ERR)) | \

drivers/accel/ivpu/ivpu_hw_btrs.c

22

(REG_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, CFI1_ERR)) | \

drivers/accel/ivpu/ivpu_hw_btrs.c

23

(REG_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, IMR0_ERR)) | \

drivers/accel/ivpu/ivpu_hw_btrs.c

24

(REG_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, IMR1_ERR)) | \

drivers/accel/ivpu/ivpu_hw_btrs.c

25

(REG_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, SURV_ERR)))

drivers/accel/ivpu/ivpu_hw_btrs.c

27

#define BTRS_MTL_ALL_IRQ_MASK (BTRS_MTL_IRQ_MASK | (REG_FLD(VPU_HW_BTRS_MTL_INTERRUPT_STAT, \

drivers/accel/ivpu/ivpu_hw_ip.c

1191

u32 val = REG_FLD(VPU_37XX_CPU_SS_DOORBELL_0, SET);

drivers/accel/ivpu/ivpu_hw_ip.c

1199

u32 val = REG_FLD(VPU_40XX_CPU_SS_DOORBELL_0, SET);

drivers/accel/ivpu/ivpu_hw_ip.c

23

#define ICB_0_IRQ_MASK_37XX ((REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, HOST_IPC_FIFO_INT)) | \

drivers/accel/ivpu/ivpu_hw_ip.c

24

(REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_0_INT)) | \

drivers/accel/ivpu/ivpu_hw_ip.c

25

(REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_1_INT)) | \

drivers/accel/ivpu/ivpu_hw_ip.c

26

(REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_2_INT)) | \

drivers/accel/ivpu/ivpu_hw_ip.c

27

(REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, NOC_FIREWALL_INT)) | \

drivers/accel/ivpu/ivpu_hw_ip.c

28

(REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_0_INT)) | \

drivers/accel/ivpu/ivpu_hw_ip.c

29

(REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_1_INT)))

drivers/accel/ivpu/ivpu_hw_ip.c

31

#define ICB_1_IRQ_MASK_37XX ((REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_1, CPU_INT_REDIRECT_2_INT)) | \

drivers/accel/ivpu/ivpu_hw_ip.c

32

(REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_1, CPU_INT_REDIRECT_3_INT)) | \

drivers/accel/ivpu/ivpu_hw_ip.c

33

(REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_1, CPU_INT_REDIRECT_4_INT)))

drivers/accel/ivpu/ivpu_hw_ip.c

37

#define ICB_0_IRQ_MASK_40XX ((REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, HOST_IPC_FIFO_INT)) | \

drivers/accel/ivpu/ivpu_hw_ip.c

38

(REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_0_INT)) | \

drivers/accel/ivpu/ivpu_hw_ip.c

39

(REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_1_INT)) | \

drivers/accel/ivpu/ivpu_hw_ip.c

40

(REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_2_INT)) | \

drivers/accel/ivpu/ivpu_hw_ip.c

41

(REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, NOC_FIREWALL_INT)) | \

drivers/accel/ivpu/ivpu_hw_ip.c

42

(REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_0_INT)) | \

drivers/accel/ivpu/ivpu_hw_ip.c

43

(REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_1_INT)))

drivers/accel/ivpu/ivpu_hw_ip.c

45

#define ICB_1_IRQ_MASK_40XX ((REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_1, CPU_INT_REDIRECT_2_INT)) | \

drivers/accel/ivpu/ivpu_hw_ip.c

46

(REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_1, CPU_INT_REDIRECT_3_INT)) | \

drivers/accel/ivpu/ivpu_hw_ip.c

47

(REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_1, CPU_INT_REDIRECT_4_INT)))

drivers/accel/ivpu/ivpu_hw_ip.c

51

#define ITF_FIREWALL_VIOLATION_MASK_37XX ((REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, CSS_ROM_CMX)) | \

drivers/accel/ivpu/ivpu_hw_ip.c

52

(REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, CSS_DBG)) | \

drivers/accel/ivpu/ivpu_hw_ip.c

53

(REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, CSS_CTRL)) | \

drivers/accel/ivpu/ivpu_hw_ip.c

54

(REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, DEC400)) | \

drivers/accel/ivpu/ivpu_hw_ip.c

55

(REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, MSS_NCE)) | \

drivers/accel/ivpu/ivpu_hw_ip.c

56

(REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, MSS_MBI)) | \

drivers/accel/ivpu/ivpu_hw_ip.c

57

(REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, MSS_MBI_CMX)))

drivers/accel/ivpu/ivpu_hw_ip.c

59

#define ITF_FIREWALL_VIOLATION_MASK_40XX ((REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, CSS_ROM_CMX)) | \

drivers/accel/ivpu/ivpu_hw_ip.c

60

(REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, CSS_DBG)) | \

drivers/accel/ivpu/ivpu_hw_ip.c

61

(REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, CSS_CTRL)) | \

drivers/accel/ivpu/ivpu_hw_ip.c

62

(REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, DEC400)) | \

drivers/accel/ivpu/ivpu_hw_ip.c

63

(REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, MSS_NCE)) | \

drivers/accel/ivpu/ivpu_hw_ip.c

64

(REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, MSS_MBI)) | \

drivers/accel/ivpu/ivpu_hw_ip.c

65

(REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, MSS_MBI_CMX)))

drivers/accel/ivpu/ivpu_mmu.c

226

#define IVPU_MMU_GERROR_ERR_MASK ((REG_FLD(IVPU_MMU_REG_GERROR, CMDQ)) | \

drivers/accel/ivpu/ivpu_mmu.c

227

(REG_FLD(IVPU_MMU_REG_GERROR, EVTQ_ABT)) | \

drivers/accel/ivpu/ivpu_mmu.c

228

(REG_FLD(IVPU_MMU_REG_GERROR, PRIQ_ABT)) | \

drivers/accel/ivpu/ivpu_mmu.c

229

(REG_FLD(IVPU_MMU_REG_GERROR, MSI_CMDQ_ABT)) | \

drivers/accel/ivpu/ivpu_mmu.c

230

(REG_FLD(IVPU_MMU_REG_GERROR, MSI_EVTQ_ABT)) | \

drivers/accel/ivpu/ivpu_mmu.c

231

(REG_FLD(IVPU_MMU_REG_GERROR, MSI_PRIQ_ABT)) | \

drivers/accel/ivpu/ivpu_mmu.c

232

(REG_FLD(IVPU_MMU_REG_GERROR, MSI_ABT)))