drivers/gpu/drm/i915/display/intel_cx0_phy.c

2026

return !REG_FIELD_GET8(C10_PLL15_HDMIDIV_MASK, pll_state->pll[15]);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2054

multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, pll_state->pll[3]) << 8 |

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2057

tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, pll_state->pll[15]);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2058

hdmi_div = REG_FIELD_GET8(C10_PLL15_HDMIDIV_MASK, pll_state->pll[15]);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2320

multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, hw_state->pll[3]) << 8 |

drivers/gpu/drm/i915/display/intel_cx0_phy.c

2322

tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, hw_state->pll[15]);

drivers/gpu/drm/i915/display/intel_lt_phy.c

1183

u8 mode = REG_FIELD_GET8(LT_PHY_VDR_MODE_ENCODING_MASK, ltpll->config[0]);

drivers/gpu/drm/i915/display/intel_lt_phy.c

1193

u8 mode = REG_FIELD_GET8(LT_PHY_VDR_MODE_ENCODING_MASK, ltpll->config[0]);

drivers/gpu/drm/i915/display/intel_lt_phy.c

1277

rate = REG_FIELD_GET8(LT_PHY_VDR_RATE_ENCODING_MASK, val);

drivers/gpu/drm/i915/display/intel_lt_phy.c

1721

mode = REG_FIELD_GET8(LT_PHY_VDR_MODE_ENCODING_MASK,

drivers/gpu/drm/i915/display/intel_lt_phy.c

1730

rate = REG_FIELD_GET8(LT_PHY_VDR_RATE_ENCODING_MASK,

drivers/gpu/drm/i915/display/intel_psr.c

551

pr_dsc_mode = REG_FIELD_GET8(DP_PANEL_REPLAY_DSC_DECODE_CAPABILITY_IN_PR_MASK, val);