drivers/net/ethernet/chelsio/cxgb/cxgb2.c

563

reg_block_dump(ap, buf, A_PL_ENABLE, A_PL_CAUSE);

drivers/net/ethernet/chelsio/cxgb/espi.c

110

u32 enable, pl_intr = readl(espi->adapter->regs + A_PL_ENABLE);

drivers/net/ethernet/chelsio/cxgb/espi.c

121

writel(pl_intr | F_PL_INTR_ESPI, espi->adapter->regs + A_PL_ENABLE);

drivers/net/ethernet/chelsio/cxgb/espi.c

133

u32 pl_intr = readl(espi->adapter->regs + A_PL_ENABLE);

drivers/net/ethernet/chelsio/cxgb/espi.c

136

writel(pl_intr & ~F_PL_INTR_ESPI, espi->adapter->regs + A_PL_ENABLE);

drivers/net/ethernet/chelsio/cxgb/pm3393.c

145

pl_intr = readl(cmac->adapter->regs + A_PL_ENABLE);

drivers/net/ethernet/chelsio/cxgb/pm3393.c

147

writel(pl_intr, cmac->adapter->regs + A_PL_ENABLE);

drivers/net/ethernet/chelsio/cxgb/sge.c

1646

adapter->regs + A_PL_ENABLE);

drivers/net/ethernet/chelsio/cxgb/sge.c

902

u32 val = readl(sge->adapter->regs + A_PL_ENABLE);

drivers/net/ethernet/chelsio/cxgb/sge.c

904

writel(val & ~SGE_PL_INTR_MASK, sge->adapter->regs + A_PL_ENABLE);

drivers/net/ethernet/chelsio/cxgb/sge.c

914

u32 val = readl(sge->adapter->regs + A_PL_ENABLE);

drivers/net/ethernet/chelsio/cxgb/sge.c

919

writel(val | SGE_PL_INTR_MASK, sge->adapter->regs + A_PL_ENABLE);

drivers/net/ethernet/chelsio/cxgb/subr.c

779

u32 pl_intr = readl(adapter->regs + A_PL_ENABLE);

drivers/net/ethernet/chelsio/cxgb/subr.c

787

writel(pl_intr, adapter->regs + A_PL_ENABLE);

drivers/net/ethernet/chelsio/cxgb/subr.c

809

writel(0, adapter->regs + A_PL_ENABLE);

drivers/net/ethernet/chelsio/cxgb/subr.c

876

adapter->regs + A_PL_ENABLE);

drivers/net/ethernet/chelsio/cxgb/tp.c

101

tp->adapter->regs + A_PL_ENABLE);

drivers/net/ethernet/chelsio/cxgb/tp.c

107

tp->adapter->regs + A_PL_ENABLE);

drivers/net/ethernet/chelsio/cxgb/tp.c

73

u32 tp_intr = readl(tp->adapter->regs + A_PL_ENABLE);

drivers/net/ethernet/chelsio/cxgb/tp.c

81

tp->adapter->regs + A_PL_ENABLE);

drivers/net/ethernet/chelsio/cxgb/tp.c

88

tp->adapter->regs + A_PL_ENABLE);

drivers/net/ethernet/chelsio/cxgb/tp.c

94

u32 tp_intr = readl(tp->adapter->regs + A_PL_ENABLE);