drivers/gpu/drm/i915/gt/intel_engine_cs.c

68

{ .graphics_ver = 1, .base = RENDER_RING_BASE }

drivers/gpu/drm/i915/gt/intel_engine_regs.h

35

#define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))

drivers/gpu/drm/i915/gt/intel_engine_regs.h

36

#define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))

drivers/gpu/drm/i915/gt/intel_engine_regs.h

37

#define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE))

drivers/gpu/drm/i915/gt/intel_gt.c

254

intel_uncore_write(uncore, IPEIR(RENDER_RING_BASE), 0);

drivers/gpu/drm/i915/gt/intel_gt.c

441

RING_TAIL(RENDER_RING_BASE));

drivers/gpu/drm/i915/gt/intel_rc6.c

463

if (!((intel_uncore_read(uncore, PWRCTX_MAXCNT(RENDER_RING_BASE)) & IDLE_TIME_MASK) > 1 &&

drivers/gpu/drm/i915/gt/intel_workarounds.c

2329

RING_PSMI_CTL(RENDER_RING_BASE),

drivers/gpu/drm/i915/gt/intel_workarounds.c

2581

RING_MODE_GEN7(RENDER_RING_BASE),

drivers/gpu/drm/i915/gt/intel_workarounds.c

2607

RING_MI_MODE(RENDER_RING_BASE),

drivers/gpu/drm/i915/gt/intel_workarounds.c

2663

wa_add(wal, RING_MI_MODE(RENDER_RING_BASE),

drivers/gpu/drm/i915/gt/intel_workarounds.c

2679

wa_add(wal, ECOSKPD(RENDER_RING_BASE),

drivers/gpu/drm/i915/gt/intel_workarounds.c

368

wa_masked_en(wal, RING_MI_MODE(RENDER_RING_BASE), ASYNC_FLIP_PERF_DISABLE);

drivers/gpu/drm/i915/gvt/handlers.c

2188

MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \

drivers/gpu/drm/i915/gvt/handlers.c

2245

MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2814

MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40, F_CMD_ACCESS,

drivers/gpu/drm/i915/gvt/mmio_context.c

100

{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */

drivers/gpu/drm/i915/gvt/mmio_context.c

101

{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */

drivers/gpu/drm/i915/gvt/mmio_context.c

102

{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */

drivers/gpu/drm/i915/gvt/mmio_context.c

103

{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */

drivers/gpu/drm/i915/gvt/mmio_context.c

104

{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */

drivers/gpu/drm/i915/gvt/mmio_context.c

105

{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */

drivers/gpu/drm/i915/gvt/mmio_context.c

106

{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */

drivers/gpu/drm/i915/gvt/mmio_context.c

107

{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */

drivers/gpu/drm/i915/gvt/mmio_context.c

108

{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */

drivers/gpu/drm/i915/gvt/mmio_context.c

109

{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */

drivers/gpu/drm/i915/gvt/mmio_context.c

62

{RCS0, RING_MODE_GEN7(RENDER_RING_BASE), 0xffff, false}, /* 0x229c */

drivers/gpu/drm/i915/gvt/mmio_context.c

66

{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */

drivers/gpu/drm/i915/gvt/mmio_context.c

67

{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */

drivers/gpu/drm/i915/gvt/mmio_context.c

68

{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */

drivers/gpu/drm/i915/gvt/mmio_context.c

69

{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */

drivers/gpu/drm/i915/gvt/mmio_context.c

70

{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */

drivers/gpu/drm/i915/gvt/mmio_context.c

71

{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */

drivers/gpu/drm/i915/gvt/mmio_context.c

72

{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */

drivers/gpu/drm/i915/gvt/mmio_context.c

73

{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */

drivers/gpu/drm/i915/gvt/mmio_context.c

74

{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */

drivers/gpu/drm/i915/gvt/mmio_context.c

75

{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */

drivers/gpu/drm/i915/gvt/mmio_context.c

76

{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */

drivers/gpu/drm/i915/gvt/mmio_context.c

77

{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */

drivers/gpu/drm/i915/gvt/mmio_context.c

94

{RCS0, RING_MODE_GEN7(RENDER_RING_BASE), 0xffff, false}, /* 0x229c */

drivers/gpu/drm/i915/gvt/mmio_context.c

98

{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */

drivers/gpu/drm/i915/gvt/mmio_context.c

99

{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */

drivers/gpu/drm/i915/i915_cmd_parser.c

620

REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE),

drivers/gpu/drm/i915/i915_cmd_parser.c

621

REG64_IDX(MI_PREDICATE_SRC0, RENDER_RING_BASE),

drivers/gpu/drm/i915/i915_cmd_parser.c

622

REG64_IDX(MI_PREDICATE_SRC1, RENDER_RING_BASE),

drivers/gpu/drm/i915/i915_cmd_parser.c

652

REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 0),

drivers/gpu/drm/i915/i915_cmd_parser.c

653

REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 1),

drivers/gpu/drm/i915/i915_cmd_parser.c

654

REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 2),

drivers/gpu/drm/i915/i915_cmd_parser.c

655

REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 3),

drivers/gpu/drm/i915/i915_cmd_parser.c

656

REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 4),

drivers/gpu/drm/i915/i915_cmd_parser.c

657

REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 5),

drivers/gpu/drm/i915/i915_cmd_parser.c

658

REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 6),

drivers/gpu/drm/i915/i915_cmd_parser.c

659

REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 7),

drivers/gpu/drm/i915/i915_cmd_parser.c

660

REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 8),

drivers/gpu/drm/i915/i915_cmd_parser.c

661

REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 9),

drivers/gpu/drm/i915/i915_cmd_parser.c

662

REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 10),

drivers/gpu/drm/i915/i915_cmd_parser.c

663

REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 11),

drivers/gpu/drm/i915/i915_cmd_parser.c

664

REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 12),

drivers/gpu/drm/i915/i915_cmd_parser.c

665

REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 13),

drivers/gpu/drm/i915/i915_cmd_parser.c

666

REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 14),

drivers/gpu/drm/i915/i915_cmd_parser.c

667

REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 15),

drivers/gpu/drm/i915/i915_cmd_parser.c

678

REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE),

drivers/gpu/drm/i915/i915_cmd_parser.c

685

REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE),

drivers/gpu/drm/i915/i915_ioctl.c

32

.offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),

drivers/gpu/drm/i915/i915_ioctl.c

33

.offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),

drivers/gpu/drm/i915/i915_perf.c

1960

MI_PREDICATE_RESULT_1(RENDER_RING_BASE);

drivers/gpu/drm/i915/i915_perf.c

2766

GEN8_R_PWR_CLK_STATE(RENDER_RING_BASE),

drivers/gpu/drm/i915/intel_clock_gating.c

454

intel_uncore_write(&i915->uncore, RING_PSMI_CTL(RENDER_RING_BASE),

drivers/gpu/drm/i915/intel_clock_gating.c

594

intel_uncore_write(&i915->uncore, RING_PSMI_CTL(RENDER_RING_BASE),

drivers/gpu/drm/i915/intel_clock_gating.c

665

intel_uncore_write(&i915->uncore, ECOSKPD(RENDER_RING_BASE),

drivers/gpu/drm/i915/intel_clock_gating.c

669

intel_uncore_write(&i915->uncore, ECOSKPD(RENDER_RING_BASE),

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

1260

MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40);

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

53

MMIO_F(prefix(RENDER_RING_BASE), s); \

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

616

MMIO_D(ECOSKPD(RENDER_RING_BASE));

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

91

MMIO_D(CCID(RENDER_RING_BASE));

drivers/gpu/drm/i915/intel_uncore.c

1761

__raw_uncore_write32(uncore, RING_MI_MODE(RENDER_RING_BASE), 0);

drivers/gpu/drm/xe/xe_hw_engine.c

63

.mmio_base = RENDER_RING_BASE,

drivers/gpu/drm/xe/xe_reg_whitelist.c

75

XE_RTP_ACTIONS(WHITELIST(CSBE_DEBUG_STATUS(RENDER_RING_BASE), 0))

drivers/gpu/drm/xe/xe_wa.c

316

XE_RTP_ACTIONS(SET(FF_THREAD_MODE(RENDER_RING_BASE),

drivers/gpu/drm/xe/xe_wa.c

337

XE_RTP_ACTIONS(SET(CS_DEBUG_MODE1(RENDER_RING_BASE),

drivers/gpu/drm/xe/xe_wa.c

346

XE_RTP_ACTIONS(SET(FF_SLICE_CS_CHICKEN1(RENDER_RING_BASE),

drivers/gpu/drm/xe/xe_wa.c

354

XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE),

drivers/gpu/drm/xe/xe_wa.c

363

XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE),

drivers/gpu/drm/xe/xe_wa.c

372

XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE),

drivers/gpu/drm/xe/xe_wa.c

462

XE_RTP_ACTIONS(SET(RING_HWSTAM(RENDER_RING_BASE), ~0))

drivers/gpu/drm/xe/xe_wa.c

699

XE_RTP_ACTIONS(FIELD_SET(CS_CHICKEN1(RENDER_RING_BASE),