Symbol: REG_WRITE
arch/x86/mm/mmio-mod.c
170
case REG_WRITE:
arch/x86/mm/pf_in.c
140
CHECK_OP_TYPE(opcode, reg_wop, REG_WRITE);
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c
109
REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Status_BUSY);
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c
112
REG_WRITE(MP1_SMN_C2PMSG_83, param);
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c
115
REG_WRITE(MP1_SMN_C2PMSG_67, msg_id);
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
115
REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Status_BUSY);
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
118
REG_WRITE(MP1_SMN_C2PMSG_83, param);
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
121
REG_WRITE(MP1_SMN_C2PMSG_67, msg_id);
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c
84
REG_WRITE(DAL_RESP_REG, 0);
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c
87
REG_WRITE(DAL_ARG_REG, param_in);
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c
90
REG_WRITE(DAL_MSG_REG, msg_id);
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr_smu_msg.c
84
REG_WRITE(DAL_RESP_REG, 0);
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr_smu_msg.c
87
REG_WRITE(DAL_ARG_REG, param_in);
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr_smu_msg.c
90
REG_WRITE(DAL_MSG_REG, msg_id);
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c
114
REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Status_BUSY);
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c
117
REG_WRITE(MP1_SMN_C2PMSG_83, param);
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c
120
REG_WRITE(MP1_SMN_C2PMSG_67, msg_id);
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
119
REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Status_BUSY);
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
122
REG_WRITE(MP1_SMN_C2PMSG_83, param);
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
125
REG_WRITE(MP1_SMN_C2PMSG_67, msg_id);
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
135
REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Result_OK);
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c
135
REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Status_BUSY);
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c
138
REG_WRITE(MP1_SMN_C2PMSG_83, param);
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c
141
REG_WRITE(MP1_SMN_C2PMSG_67, msg_id);
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c
154
REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Result_OK);
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c
150
REG_WRITE(MP1_SMN_C2PMSG_38, VBIOSSMC_Status_BUSY);
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c
153
REG_WRITE(MP1_SMN_C2PMSG_37, param);
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c
134
REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Status_BUSY);
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c
137
REG_WRITE(MP1_SMN_C2PMSG_83, param);
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c
140
REG_WRITE(MP1_SMN_C2PMSG_67, msg_id);
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c
138
REG_WRITE(DAL_RESP_REG, 0);
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c
141
REG_WRITE(DAL_ARG_REG, param_in);
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c
144
REG_WRITE(DAL_MSG_REG, msg_id);
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c
78
REG_WRITE(DAL_RESP_REG, 0);
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c
81
REG_WRITE(DAL_ARG_REG, param_in);
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c
84
REG_WRITE(DAL_MSG_REG, msg_id);
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
153
REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Status_BUSY);
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
156
REG_WRITE(MP1_SMN_C2PMSG_83, param);
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
159
REG_WRITE(MP1_SMN_C2PMSG_67, msg_id);
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
169
REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Result_OK);
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c
123
REG_WRITE(DAL_RESP_REG, 0);
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c
126
REG_WRITE(DAL_ARG_REG, param_in);
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c
129
REG_WRITE(DAL_MSG_REG, msg_id);
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c
63
REG_WRITE(DAL_RESP_REG, 0);
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c
66
REG_WRITE(DAL_ARG_REG, param_in);
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c
69
REG_WRITE(DAL_MSG_REG, msg_id);
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c
140
REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x00120264);
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c
141
REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x001186a0);
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c
142
REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0x0e01003c);
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c
145
REG_WRITE(REFCLK_CNTL, 0);
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c
154
REG_WRITE(REFCLK_CNTL, 0);
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c
169
REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c
170
REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c
172
REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0xFFFFFFFF);
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c
173
REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0xFFFFFFFF);
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
584
REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], modulo);
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
585
REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], phase);
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
606
REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], 0);
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
607
REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], 0);
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
626
REG_WRITE(DCCG_AUDIO_DTBCLK_DTO_MODULO, modulo);
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
627
REG_WRITE(DCCG_AUDIO_DTBCLK_DTO_PHASE, phase);
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
635
REG_WRITE(DCCG_AUDIO_DTBCLK_DTO_PHASE, 0);
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
636
REG_WRITE(DCCG_AUDIO_DTBCLK_DTO_MODULO, 0);
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c
221
REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], modulo);
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c
222
REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], phase);
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c
245
REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], 0);
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c
246
REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], 0);
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c
220
REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], modulo);
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c
221
REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], phase);
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c
243
REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], 0);
drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c
244
REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], 0);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1126
REG_WRITE(DENTIST_DISPCLK_CNTL, dentist_dispclk_value);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1404
REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], modulo);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1405
REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], phase);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1450
REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], 0);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
1451
REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], 0);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2320
REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], modulo);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2321
REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], phase);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2346
REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], 0);
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
2347
REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], 0);
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
116
REG_WRITE(DENTIST_DISPCLK_CNTL, dentist_dispclk_value);
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
661
REG_WRITE(DP_DTO_PHASE[params->otg_inst], dto_phase_hz);
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
662
REG_WRITE(DP_DTO_MODULO[params->otg_inst], dto_modulo_hz);
drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
115
REG_WRITE(MASTER_COMM_DATA_REG1, frame_ramp);
drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
131
REG_WRITE(BIOS_SCRATCH_2, s2);
drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
142
REG_WRITE(DC_ABM1_HG_SAMPLE_RATE, 0x103);
drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
143
REG_WRITE(DC_ABM1_HG_SAMPLE_RATE, 0x101);
drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
144
REG_WRITE(DC_ABM1_LS_SAMPLE_RATE, 0x103);
drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
145
REG_WRITE(DC_ABM1_LS_SAMPLE_RATE, 0x101);
drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
146
REG_WRITE(BL1_PWM_BL_UPDATE_SAMPLE_RATE, 0x101);
drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
70
REG_WRITE(MASTER_COMM_DATA_REG1, rampingBoundary);
drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
854
REG_WRITE(AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS,
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
141
REG_WRITE(AUX_CONTROL, value);
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
155
REG_WRITE(AUX_CONTROL, value);
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
1298
REG_WRITE(MODULO[inst],
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
1313
REG_WRITE(PHASE[inst], pixel_clk);
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
1314
REG_WRITE(MODULO[inst], ref_clk);
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
1343
REG_WRITE(PHASE[inst], e->target_pixel_rate_khz * e->mult_factor);
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
1344
REG_WRITE(MODULO[inst], dp_dto_ref_khz * e->div_factor);
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
1347
REG_WRITE(PHASE[inst], pll_settings->actual_pix_clk_100hz * 100);
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
1348
REG_WRITE(MODULO[inst], dp_dto_ref_khz * 1000);
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
989
REG_WRITE(PHASE[inst], e->target_pixel_rate_khz * e->mult_factor);
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
990
REG_WRITE(MODULO[inst], dp_dto_ref_khz * e->div_factor);
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
993
REG_WRITE(PHASE[inst], pll_settings->actual_pix_clk_100hz * 100);
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
994
REG_WRITE(MODULO[inst], dp_dto_ref_khz * 1000);
drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
118
REG_WRITE(DMCU_IRAM_RD_CTRL, psr_state_offset);
drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
344
REG_WRITE(DMCU_IRAM_RD_CTRL, dmcu_version_offset);
drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
366
REG_WRITE(MASTER_COMM_DATA_REG1, fractional_pwm);
drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
416
REG_WRITE(MASTER_COMM_DATA_REG1, 0xFFFF);
drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
419
REG_WRITE(MASTER_COMM_DATA_REG2, abm_gain_stepsize);
drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
421
REG_WRITE(MASTER_COMM_DATA_REG3, tx_interrupt_mask);
drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
493
REG_WRITE(DMCU_IRAM_WR_CTRL, start_offset);
drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
496
REG_WRITE(DMCU_IRAM_WR_DATA, src[count]);
drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
535
REG_WRITE(DMCU_IRAM_RD_CTRL, psr_state_offset);
drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
842
REG_WRITE(MASTER_COMM_DATA_REG1, header);
drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
843
REG_WRITE(MASTER_COMM_DATA_REG2, data1);
drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
844
REG_WRITE(MASTER_COMM_DATA_REG3, data2);
drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
93
REG_WRITE(DMCU_IRAM_WR_CTRL, start_offset);
drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
96
REG_WRITE(DMCU_IRAM_WR_DATA, src[count]);
drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
298
REG_WRITE(DP_DPHY_TRAINING_PATTERN_SEL, index);
drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
342
REG_WRITE(DP_DPHY_INTERNAL_CTRL, value);
drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
333
REG_WRITE(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, 0);
drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
335
REG_WRITE(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, 0);
drivers/gpu/drm/amd/display/dc/dce/dce_opp.c
337
REG_WRITE(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, 0);
drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c
102
REG_WRITE(BL_PWM_CNTL,
drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c
104
REG_WRITE(BL_PWM_CNTL2,
drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c
106
REG_WRITE(BL_PWM_PERIOD_CNTL,
drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c
125
REG_WRITE(BL_PWM_CNTL, 0x8000FA00);
drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c
126
REG_WRITE(BL_PWM_PERIOD_CNTL, 0x000C0FA0);
drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c
133
REG_WRITE(BIOS_SCRATCH_2, value);
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
120
REG_WRITE(AFMT_GENERIC_0, *content++);
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
121
REG_WRITE(AFMT_GENERIC_1, *content++);
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
122
REG_WRITE(AFMT_GENERIC_2, *content++);
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
123
REG_WRITE(AFMT_GENERIC_3, *content++);
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
124
REG_WRITE(AFMT_GENERIC_4, *content++);
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
125
REG_WRITE(AFMT_GENERIC_5, *content++);
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
126
REG_WRITE(AFMT_GENERIC_6, *content++);
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
127
REG_WRITE(AFMT_GENERIC_7, *content);
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
447
REG_WRITE(DP_MSA_MISC, misc1); /* MSA_MISC1 */
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
740
REG_WRITE(AFMT_AVI_INFO0, content[0]);
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
742
REG_WRITE(AFMT_AVI_INFO1, content[1]);
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
744
REG_WRITE(AFMT_AVI_INFO2, content[2]);
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
746
REG_WRITE(AFMT_AVI_INFO3, content[3]);
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
1460
REG_WRITE(REGAMMA_LUT_INDEX, 0);
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
1465
REG_WRITE(REGAMMA_LUT_DATA, rgb->red_reg);
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
1466
REG_WRITE(REGAMMA_LUT_DATA, rgb->green_reg);
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
1467
REG_WRITE(REGAMMA_LUT_DATA, rgb->blue_reg);
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
1468
REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_red_reg);
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
1469
REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_green_reg);
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
1470
REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_blue_reg);
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
158
REG_WRITE(SCL_SCALER_ENABLE, 0);
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
161
REG_WRITE(SCL_TAP_CONTROL, 0);
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
162
REG_WRITE(SCL_AUTOMATIC_MODE_CONTROL, 0);
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
163
REG_WRITE(SCL_F_SHARP_CONTROL, 0);
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
171
REG_WRITE(SCL_SCALER_ENABLE, 1);
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
262
REG_WRITE(DCFE_MEM_PWR_CTRL, power_ctl);
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
361
REG_WRITE(SCL_AUTOMATIC_MODE_CONTROL, 0);
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
390
REG_WRITE(SCL_AUTOMATIC_MODE_CONTROL, 0);
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
426
REG_WRITE(SCL_F_SHARP_CONTROL, 0);
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
508
REG_WRITE(SCL_UPDATE, 0x00010000);
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
511
REG_WRITE(SCL_F_SHARP_CONTROL, 0);
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
535
REG_WRITE(SCL_VERT_FILTER_CONTROL, 0);
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
549
REG_WRITE(SCL_HORZ_FILTER_CONTROL, 0);
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
573
REG_WRITE(SCL_UPDATE, 0);
drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c
82
REG_WRITE(DC_ABM1_HG_SAMPLE_RATE, 0x3);
drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c
83
REG_WRITE(DC_ABM1_HG_SAMPLE_RATE, 0x1);
drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c
84
REG_WRITE(DC_ABM1_LS_SAMPLE_RATE, 0x3);
drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c
85
REG_WRITE(DC_ABM1_LS_SAMPLE_RATE, 0x1);
drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c
86
REG_WRITE(BL1_PWM_BL_UPDATE_SAMPLE_RATE, 0x1);
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_vpg.c
103
REG_WRITE(VPG_GENERIC_PACKET_DATA, *content++);
drivers/gpu/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c
110
REG_WRITE(BL_PWM_CNTL,
drivers/gpu/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c
112
REG_WRITE(BL_PWM_CNTL2,
drivers/gpu/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c
114
REG_WRITE(BL_PWM_PERIOD_CNTL,
drivers/gpu/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c
123
REG_WRITE(BL_PWM_CNTL, 0xC000FA00);
drivers/gpu/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c
124
REG_WRITE(BL_PWM_PERIOD_CNTL, 0x000C0FA0);
drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_dio.c
24
REG_WRITE(DIO_MEM_PWR_CTRL, 0);
drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
216
REG_WRITE(DP_DPHY_TRAINING_PATTERN_SEL, index);
drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c
253
REG_WRITE(DP_DPHY_INTERNAL_CTRL, value);
drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
110
REG_WRITE(AFMT_GENERIC_0, *content++);
drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
111
REG_WRITE(AFMT_GENERIC_1, *content++);
drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
112
REG_WRITE(AFMT_GENERIC_2, *content++);
drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
113
REG_WRITE(AFMT_GENERIC_3, *content++);
drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
114
REG_WRITE(AFMT_GENERIC_4, *content++);
drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
115
REG_WRITE(AFMT_GENERIC_5, *content++);
drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
116
REG_WRITE(AFMT_GENERIC_6, *content++);
drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
117
REG_WRITE(AFMT_GENERIC_7, *content);
drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
413
REG_WRITE(DP_MSA_MISC, misc1); /* MSA_MISC1 */
drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
838
REG_WRITE(AFMT_GENERIC_0, *content++);
drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
839
REG_WRITE(AFMT_GENERIC_1, *content++);
drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
840
REG_WRITE(AFMT_GENERIC_2, *content++);
drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
841
REG_WRITE(AFMT_GENERIC_3, *content++);
drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
842
REG_WRITE(AFMT_GENERIC_4, *content++);
drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
843
REG_WRITE(AFMT_GENERIC_5, *content++);
drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
844
REG_WRITE(AFMT_GENERIC_6, *content++);
drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
845
REG_WRITE(AFMT_GENERIC_7, *content);
drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
260
REG_WRITE(AFMT_GENERIC_0, *content++);
drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
261
REG_WRITE(AFMT_GENERIC_1, *content++);
drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
262
REG_WRITE(AFMT_GENERIC_2, *content++);
drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
263
REG_WRITE(AFMT_GENERIC_3, *content++);
drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
264
REG_WRITE(AFMT_GENERIC_4, *content++);
drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
265
REG_WRITE(AFMT_GENERIC_5, *content++);
drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
266
REG_WRITE(AFMT_GENERIC_6, *content++);
drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
267
REG_WRITE(AFMT_GENERIC_7, *content++);
drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
654
REG_WRITE(DP_MSA_MISC, misc1); /* MSA_MISC1 */
drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
185
REG_WRITE(DCHUBBUB_TEST_DEBUG_INDEX, hubbub1->debug_test_index_pstate);
drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
272
REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A, prog_wm_value);
drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
297
REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B, prog_wm_value);
drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
322
REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C, prog_wm_value);
drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
347
REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D, prog_wm_value);
drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
650
REG_WRITE(DCHUBBUB_TEST_DEBUG_INDEX, 0x6);
drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
689
REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, prog_wm_value);
drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
408
REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
409
REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
410
REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
413
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
414
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
415
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
418
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
419
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
420
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
423
REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
424
REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
425
REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
428
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
429
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
430
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
433
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
434
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
435
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
438
REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
439
REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
440
REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
1007
REG_WRITE(DCHUBBUB_TEST_DEBUG_INDEX, hubbub2->debug_test_index_pstate);
drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
833
REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
834
REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
835
REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
838
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
839
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
840
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
843
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
844
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
845
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
848
REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
849
REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
850
REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
853
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
854
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
855
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
858
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
859
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
860
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
863
REG_WRITE(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
864
REG_WRITE(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
865
REG_WRITE(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
868
REG_WRITE(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
869
REG_WRITE(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
870
REG_WRITE(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
873
REG_WRITE(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
874
REG_WRITE(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c
875
REG_WRITE(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
344
REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
345
REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
346
REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
349
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
350
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
351
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
354
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
355
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
356
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
359
REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
360
REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
361
REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
364
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
365
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
366
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
369
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
370
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
371
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
374
REG_WRITE(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
375
REG_WRITE(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
376
REG_WRITE(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
379
REG_WRITE(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
380
REG_WRITE(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
381
REG_WRITE(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
384
REG_WRITE(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
385
REG_WRITE(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
386
REG_WRITE(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
389
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
390
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
391
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
394
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
395
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c
396
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
503
REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
506
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
509
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
512
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_MALL_B, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
515
REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
518
REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_META_TRIP_B, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
521
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
522
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_A, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
523
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_B, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
524
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_A, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
525
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_B, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
526
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_A, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
527
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_B, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
530
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
531
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_A, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
532
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_B, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
533
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_A, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
534
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_B, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
535
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_A, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
536
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_B, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
539
REG_WRITE(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
542
REG_WRITE(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
544
REG_WRITE(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_B, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
547
REG_WRITE(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B, reg);
drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c
549
REG_WRITE(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_B, reg);
drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
138
REG_WRITE(HUBPREQ_DEBUG_DB, value);
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
178
REG_WRITE(HUBPREQ_DEBUG_DB, 1 << 8);
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
678
REG_WRITE(DMDATA_ADDRESS_LOW, attr->address.low_part);
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
716
REG_WRITE(DMDATA_SW_DATA, dmdata_sw_data[i]);
drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
811
REG_WRITE(HUBPREQ_DEBUG, 1 << 26);
drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c
402
REG_WRITE(DMDATA_ADDRESS_LOW, attr->address.low_part);
drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c
621
REG_WRITE(HUBPREQ_DEBUG, 1 << 26);
drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c
186
REG_WRITE(HUBPREQ_DEBUG_DB, 1 << 8);
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
256
REG_WRITE(HUBPREQ_DEBUG_DB, 1 << 8);
drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
49
REG_WRITE(HUBP_3DLUT_ADDRESS_LOW, address.lut3d.addr.low_part);
drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.c
83
REG_WRITE(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst], value);
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
870
REG_WRITE(D1VGA_CONTROL, 0);
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
871
REG_WRITE(D2VGA_CONTROL, 0);
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
872
REG_WRITE(D3VGA_CONTROL, 0);
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
873
REG_WRITE(D4VGA_CONTROL, 0);
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
3138
REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF);
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
3139
REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF);
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
369
REG_WRITE(D1VGA_CONTROL, 0);
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
370
REG_WRITE(D2VGA_CONTROL, 0);
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
371
REG_WRITE(D3VGA_CONTROL, 0);
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
372
REG_WRITE(D4VGA_CONTROL, 0);
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
373
REG_WRITE(D5VGA_CONTROL, 0);
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
374
REG_WRITE(D6VGA_CONTROL, 0);
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1312
REG_WRITE(MPC_OUT_CSC_COEF_FORMAT, 0);
drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c
1353
REG_WRITE(MPC_OUT_CSC_COEF_FORMAT, 0);
drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c
269
REG_WRITE(DPG_CONTROL, 0);
drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c
270
REG_WRITE(DPG_COLOUR_R_CR, 0);
drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c
271
REG_WRITE(DPG_COLOUR_G_Y, 0);
drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c
272
REG_WRITE(DPG_COLOUR_B_CB, 0);
drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c
273
REG_WRITE(DPG_RAMP_CONTROL, 0);
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1080
REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0);
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1204
REG_WRITE(OTG_TEST_PATTERN_COLOR, 0);
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1207
REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0);
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1218
REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0);
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1219
REG_WRITE(OTG_TEST_PATTERN_COLOR, 0);
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1220
REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0);
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
1476
REG_WRITE(OTG_CRC_CNTL, 0);
drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
743
REG_WRITE(OTG_TRIGA_CNTL, 0);
drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c
171
REG_WRITE(OTG_H_TIMING_CNTL, 0);
drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
283
REG_WRITE(OTG_CRC_CNTL, 0);
drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
436
REG_WRITE(OTG_V_COUNT_STOP_CONTROL, max_otg_v_total);
drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
437
REG_WRITE(OTG_V_COUNT_STOP_CONTROL2, 0);
drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
476
REG_WRITE(OTG_V_COUNT_STOP_CONTROL, vcount_stop);
drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
477
REG_WRITE(OTG_V_COUNT_STOP_CONTROL2, vcount_stop_timer);
drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
496
REG_WRITE(OTG_V_COUNT_STOP_CONTROL, max_otg_v_total);
drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
497
REG_WRITE(OTG_V_COUNT_STOP_CONTROL2, 0);
drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
521
REG_WRITE(OTG_V_COUNT_STOP_CONTROL, vcount_stop);
drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
522
REG_WRITE(OTG_V_COUNT_STOP_CONTROL2, vcount_stop_timer);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
139
REG_WRITE(DMCUB_INBOX1_RPTR, 0);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
140
REG_WRITE(DMCUB_INBOX1_WPTR, 0);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
141
REG_WRITE(DMCUB_OUTBOX1_RPTR, 0);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
142
REG_WRITE(DMCUB_OUTBOX1_WPTR, 0);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
143
REG_WRITE(DMCUB_SCRATCH0, 0);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
149
REG_WRITE(DMCUB_SCRATCH15, dmub->psp_version & 0x001100FF);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
169
REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
170
REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
171
REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
178
REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
179
REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
180
REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
206
REG_WRITE(DMCUB_REGION3_CW2_OFFSET, offset.u.low_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
207
REG_WRITE(DMCUB_REGION3_CW2_OFFSET_HIGH, offset.u.high_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
208
REG_WRITE(DMCUB_REGION3_CW2_BASE_ADDRESS, cw2->region.base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
213
REG_WRITE(DMCUB_REGION3_CW2_OFFSET, 0);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
214
REG_WRITE(DMCUB_REGION3_CW2_OFFSET_HIGH, 0);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
215
REG_WRITE(DMCUB_REGION3_CW2_BASE_ADDRESS, 0);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
216
REG_WRITE(DMCUB_REGION3_CW2_TOP_ADDRESS, 0);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
221
REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
222
REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
223
REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
233
REG_WRITE(DMCUB_REGION3_CW4_OFFSET, offset.u.low_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
234
REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
235
REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
240
REG_WRITE(DMCUB_REGION4_OFFSET, offset.u.low_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
241
REG_WRITE(DMCUB_REGION4_OFFSET_HIGH, offset.u.high_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
250
REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
251
REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
252
REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
257
REG_WRITE(DMCUB_REGION5_OFFSET, offset.u.low_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
258
REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
266
REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
267
REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
268
REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
279
REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, inbox1->base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
281
REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, 0x80000000);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
283
REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
298
REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
306
REG_WRITE(DMCUB_OUTBOX1_BASE_ADDRESS, outbox1->base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
308
REG_WRITE(DMCUB_OUTBOX1_BASE_ADDRESS, 0x80002000);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
310
REG_WRITE(DMCUB_OUTBOX1_SIZE, outbox1->top - outbox1->base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
328
REG_WRITE(DMCUB_OUTBOX1_RPTR, rptr_offset);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
334
REG_WRITE(DMCUB_OUTBOX0_BASE_ADDRESS, outbox0->base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
336
REG_WRITE(DMCUB_OUTBOX0_SIZE, outbox0->top - outbox0->base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
346
REG_WRITE(DMCUB_OUTBOX0_RPTR, rptr_offset);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
370
REG_WRITE(DMCUB_GPINT_DATAIN1, reg.all);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
401
REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
409
REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c
102
REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c
103
REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c
104
REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c
111
REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c
112
REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c
113
REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c
137
REG_WRITE(DMCUB_REGION3_CW2_OFFSET, offset.u.low_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c
138
REG_WRITE(DMCUB_REGION3_CW2_OFFSET_HIGH, offset.u.high_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c
139
REG_WRITE(DMCUB_REGION3_CW2_BASE_ADDRESS, cw2->region.base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c
144
REG_WRITE(DMCUB_REGION3_CW2_OFFSET, 0);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c
145
REG_WRITE(DMCUB_REGION3_CW2_OFFSET_HIGH, 0);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c
146
REG_WRITE(DMCUB_REGION3_CW2_BASE_ADDRESS, 0);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c
147
REG_WRITE(DMCUB_REGION3_CW2_TOP_ADDRESS, 0);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c
152
REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c
153
REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c
154
REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c
163
REG_WRITE(DMCUB_REGION3_CW4_OFFSET, offset.u.low_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c
164
REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c
165
REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c
170
REG_WRITE(DMCUB_REGION4_OFFSET, offset.u.low_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c
171
REG_WRITE(DMCUB_REGION4_OFFSET_HIGH, offset.u.high_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c
180
REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c
181
REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c
182
REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c
187
REG_WRITE(DMCUB_REGION5_OFFSET, offset.u.low_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c
188
REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c
196
REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c
197
REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c
198
REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
136
REG_WRITE(DMCUB_INBOX1_RPTR, 0);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
137
REG_WRITE(DMCUB_INBOX1_WPTR, 0);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
138
REG_WRITE(DMCUB_OUTBOX1_RPTR, 0);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
139
REG_WRITE(DMCUB_OUTBOX1_WPTR, 0);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
140
REG_WRITE(DMCUB_OUTBOX0_RPTR, 0);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
141
REG_WRITE(DMCUB_OUTBOX0_WPTR, 0);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
142
REG_WRITE(DMCUB_SCRATCH0, 0);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
152
REG_WRITE(DMCUB_SCRATCH15, dmub->psp_version & 0x001100FF);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
170
REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
171
REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
172
REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
179
REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
180
REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
181
REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
202
REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
203
REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
204
REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
211
REG_WRITE(DMCUB_REGION3_CW4_OFFSET, offset.u.low_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
212
REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
213
REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
220
REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
221
REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
222
REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
227
REG_WRITE(DMCUB_REGION5_OFFSET, offset.u.low_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
228
REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
236
REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
237
REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
238
REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
247
REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, inbox1->base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
248
REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
263
REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
269
REG_WRITE(DMCUB_OUTBOX1_BASE_ADDRESS, outbox1->base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
270
REG_WRITE(DMCUB_OUTBOX1_SIZE, outbox1->top - outbox1->base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
288
REG_WRITE(DMCUB_OUTBOX1_RPTR, rptr_offset);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
319
REG_WRITE(DMCUB_GPINT_DATAIN1, reg.all);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
344
REG_WRITE(DMCUB_GPINT_DATAOUT, 0);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
385
REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
393
REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
399
REG_WRITE(DMCUB_OUTBOX0_BASE_ADDRESS, outbox0->base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
401
REG_WRITE(DMCUB_OUTBOX0_SIZE, outbox0->top - outbox0->base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
411
REG_WRITE(DMCUB_OUTBOX0_RPTR, rptr_offset);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
144
REG_WRITE(DMCUB_INBOX1_RPTR, 0);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
145
REG_WRITE(DMCUB_INBOX1_WPTR, 0);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
146
REG_WRITE(DMCUB_OUTBOX1_RPTR, 0);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
147
REG_WRITE(DMCUB_OUTBOX1_WPTR, 0);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
148
REG_WRITE(DMCUB_OUTBOX0_RPTR, 0);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
149
REG_WRITE(DMCUB_OUTBOX0_WPTR, 0);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
150
REG_WRITE(DMCUB_SCRATCH0, 0);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
160
REG_WRITE(DMCUB_SCRATCH15, dmub->psp_version & 0x001100FF);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
180
REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
181
REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
182
REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
189
REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
190
REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
191
REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
212
REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
213
REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
214
REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
221
REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
222
REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
223
REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
244
REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
245
REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
246
REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
253
REG_WRITE(DMCUB_REGION3_CW4_OFFSET, offset.u.low_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
254
REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
255
REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
262
REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
263
REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
264
REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
269
REG_WRITE(DMCUB_REGION5_OFFSET, offset.u.low_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
270
REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
278
REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
279
REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
280
REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
289
REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, inbox1->base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
290
REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
305
REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
311
REG_WRITE(DMCUB_OUTBOX1_BASE_ADDRESS, outbox1->base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
312
REG_WRITE(DMCUB_OUTBOX1_SIZE, outbox1->top - outbox1->base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
330
REG_WRITE(DMCUB_OUTBOX1_RPTR, rptr_offset);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
356
REG_WRITE(DMCUB_GPINT_DATAIN1, reg.all);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
381
REG_WRITE(DMCUB_GPINT_DATAOUT, 0);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
404
REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
412
REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
418
REG_WRITE(DMCUB_OUTBOX0_BASE_ADDRESS, outbox0->base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
420
REG_WRITE(DMCUB_OUTBOX0_SIZE, outbox0->top - outbox0->base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
430
REG_WRITE(DMCUB_OUTBOX0_RPTR, rptr_offset);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
515
REG_WRITE(DMCUB_REGION3_TMR_AXI_SPACE, 0x4);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
520
REG_WRITE(DMCUB_INBOX0_WPTR, data.inbox0_cmd_common.all);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
525
REG_WRITE(DMCUB_SCRATCH17, 0);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
540
REG_WRITE(DMCUB_SCRATCH9, addr->grph.addr.low_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
541
REG_WRITE(DMCUB_SCRATCH11, addr->grph.meta_addr.low_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
543
REG_WRITE(DMCUB_SCRATCH12, addr->grph.addr.low_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
544
REG_WRITE(DMCUB_SCRATCH13, addr->grph.meta_addr.low_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
546
REG_WRITE(DMCUB_SCRATCH15, !index);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
550
REG_WRITE(DMCUB_SCRATCH18, addr->grph.addr.low_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
551
REG_WRITE(DMCUB_SCRATCH19, addr->grph.meta_addr.low_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
553
REG_WRITE(DMCUB_SCRATCH20, addr->grph.addr.low_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
554
REG_WRITE(DMCUB_SCRATCH22, addr->grph.meta_addr.low_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
556
REG_WRITE(DMCUB_SCRATCH23, !index);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
135
REG_WRITE(DMCUB_INBOX1_RPTR, 0);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
136
REG_WRITE(DMCUB_INBOX1_WPTR, 0);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
137
REG_WRITE(DMCUB_OUTBOX1_RPTR, 0);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
138
REG_WRITE(DMCUB_OUTBOX1_WPTR, 0);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
139
REG_WRITE(DMCUB_OUTBOX0_RPTR, 0);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
140
REG_WRITE(DMCUB_OUTBOX0_WPTR, 0);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
141
REG_WRITE(DMCUB_SCRATCH0, 0);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
150
REG_WRITE(DMCUB_SCRATCH15, dmub->psp_version & 0x001100FF);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
173
REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
174
REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
175
REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
182
REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
183
REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
184
REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
201
REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
202
REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
203
REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
208
REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
209
REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
210
REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
229
REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
230
REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
231
REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
238
REG_WRITE(DMCUB_REGION3_CW4_OFFSET, offset.u.low_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
239
REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
240
REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
247
REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
248
REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
249
REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
254
REG_WRITE(DMCUB_REGION5_OFFSET, offset.u.low_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
255
REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
263
REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
264
REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
265
REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
272
REG_WRITE(DMCUB_REGION6_OFFSET, offset.u.low_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
273
REG_WRITE(DMCUB_REGION6_OFFSET_HIGH, offset.u.high_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
283
REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, inbox1->base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
284
REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
299
REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
305
REG_WRITE(DMCUB_OUTBOX1_BASE_ADDRESS, outbox1->base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
306
REG_WRITE(DMCUB_OUTBOX1_SIZE, outbox1->top - outbox1->base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
324
REG_WRITE(DMCUB_OUTBOX1_RPTR, rptr_offset);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
350
REG_WRITE(DMCUB_GPINT_DATAIN1, reg.all);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
375
REG_WRITE(DMCUB_GPINT_DATAOUT, 0);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
426
REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
434
REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
440
REG_WRITE(DMCUB_OUTBOX0_BASE_ADDRESS, outbox0->base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
442
REG_WRITE(DMCUB_OUTBOX0_SIZE, outbox0->top - outbox0->base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
452
REG_WRITE(DMCUB_OUTBOX0_RPTR, rptr_offset);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
576
REG_WRITE(DMCUB_REGION3_TMR_AXI_SPACE, 0x4);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
588
REG_WRITE(DMCUB_INBOX0_WPTR, data.inbox0_cmd_common.all);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
593
REG_WRITE(DMCUB_SCRATCH17, 0);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
118
REG_WRITE(DMCUB_INBOX1_RPTR, 0);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
119
REG_WRITE(DMCUB_INBOX1_WPTR, 0);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
120
REG_WRITE(DMCUB_OUTBOX1_RPTR, 0);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
121
REG_WRITE(DMCUB_OUTBOX1_WPTR, 0);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
122
REG_WRITE(DMCUB_OUTBOX0_RPTR, 0);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
123
REG_WRITE(DMCUB_OUTBOX0_WPTR, 0);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
124
REG_WRITE(DMCUB_SCRATCH0, 0);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
134
REG_WRITE(DMCUB_SCRATCH15, dmub->psp_version & 0x001100FF);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
154
REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
155
REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
156
REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
163
REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
164
REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
165
REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
187
REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
188
REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
189
REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
196
REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
197
REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
198
REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
220
REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
221
REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
222
REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
229
REG_WRITE(DMCUB_REGION3_CW4_OFFSET, offset.u.low_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
230
REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
231
REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
238
REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
239
REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
240
REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
245
REG_WRITE(DMCUB_REGION5_OFFSET, offset.u.low_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
246
REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
254
REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
255
REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
256
REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
263
REG_WRITE(DMCUB_REGION6_OFFSET, offset.u.low_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
264
REG_WRITE(DMCUB_REGION6_OFFSET_HIGH, offset.u.high_part);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
274
REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, inbox1->base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
275
REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
290
REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
296
REG_WRITE(DMCUB_OUTBOX1_BASE_ADDRESS, outbox1->base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
297
REG_WRITE(DMCUB_OUTBOX1_SIZE, outbox1->top - outbox1->base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
315
REG_WRITE(DMCUB_OUTBOX1_RPTR, rptr_offset);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
341
REG_WRITE(DMCUB_GPINT_DATAIN1, reg.all);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
366
REG_WRITE(DMCUB_GPINT_DATAOUT, 0);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
391
REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
399
REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
405
REG_WRITE(DMCUB_OUTBOX0_BASE_ADDRESS, outbox0->base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
407
REG_WRITE(DMCUB_OUTBOX0_SIZE, outbox0->top - outbox0->base);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
417
REG_WRITE(DMCUB_OUTBOX0_RPTR, rptr_offset);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
508
REG_WRITE(DMCUB_REGION3_TMR_AXI_SPACE, 0x4);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
513
REG_WRITE(DMCUB_INBOX0_WPTR, data.inbox0_cmd_common.all);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
518
REG_WRITE(DMCUB_SCRATCH17, 0);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
542
REG_WRITE(DMCUB_REG_INBOX0_MSG0, dwords[msg_index + 1]);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
545
REG_WRITE(DMCUB_REG_INBOX0_MSG1, dwords[msg_index + 1]);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
548
REG_WRITE(DMCUB_REG_INBOX0_MSG2, dwords[msg_index + 1]);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
551
REG_WRITE(DMCUB_REG_INBOX0_MSG3, dwords[msg_index + 1]);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
554
REG_WRITE(DMCUB_REG_INBOX0_MSG4, dwords[msg_index + 1]);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
557
REG_WRITE(DMCUB_REG_INBOX0_MSG5, dwords[msg_index + 1]);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
560
REG_WRITE(DMCUB_REG_INBOX0_MSG6, dwords[msg_index + 1]);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
563
REG_WRITE(DMCUB_REG_INBOX0_MSG7, dwords[msg_index + 1]);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
566
REG_WRITE(DMCUB_REG_INBOX0_MSG8, dwords[msg_index + 1]);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
569
REG_WRITE(DMCUB_REG_INBOX0_MSG9, dwords[msg_index + 1]);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
572
REG_WRITE(DMCUB_REG_INBOX0_MSG10, dwords[msg_index + 1]);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
575
REG_WRITE(DMCUB_REG_INBOX0_MSG11, dwords[msg_index + 1]);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
578
REG_WRITE(DMCUB_REG_INBOX0_MSG12, dwords[msg_index + 1]);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
581
REG_WRITE(DMCUB_REG_INBOX0_MSG13, dwords[msg_index + 1]);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
584
REG_WRITE(DMCUB_REG_INBOX0_MSG14, dwords[msg_index + 1]);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
592
REG_WRITE(DMCUB_REG_INBOX0_RDY, dwords[0]);
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
656
REG_WRITE(DMCUB_REG_OUTBOX0_RSP, *rsp);
drivers/gpu/drm/gma500/cdv_device.c
126
REG_WRITE(BLC_PWM_CTL, (blc_pwm_ctl |
drivers/gpu/drm/gma500/cdv_device.c
298
REG_WRITE(DSPCLK_GATE_D, regs->cdv.saveDSPCLK_GATE_D);
drivers/gpu/drm/gma500/cdv_device.c
299
REG_WRITE(RAMCLK_GATE_D, regs->cdv.saveRAMCLK_GATE_D);
drivers/gpu/drm/gma500/cdv_device.c
302
REG_WRITE(DPIO_CFG, 0);
drivers/gpu/drm/gma500/cdv_device.c
303
REG_WRITE(DPIO_CFG, DPIO_MODE_SELECT_0 | DPIO_CMN_RESET_N);
drivers/gpu/drm/gma500/cdv_device.c
307
REG_WRITE(DPLL_A, temp | DPLL_SYNCLOCK_ENABLE);
drivers/gpu/drm/gma500/cdv_device.c
313
REG_WRITE(DPLL_B, temp | DPLL_SYNCLOCK_ENABLE);
drivers/gpu/drm/gma500/cdv_device.c
319
REG_WRITE(DSPFW1, regs->cdv.saveDSPFW[0]);
drivers/gpu/drm/gma500/cdv_device.c
320
REG_WRITE(DSPFW2, regs->cdv.saveDSPFW[1]);
drivers/gpu/drm/gma500/cdv_device.c
321
REG_WRITE(DSPFW3, regs->cdv.saveDSPFW[2]);
drivers/gpu/drm/gma500/cdv_device.c
322
REG_WRITE(DSPFW4, regs->cdv.saveDSPFW[3]);
drivers/gpu/drm/gma500/cdv_device.c
323
REG_WRITE(DSPFW5, regs->cdv.saveDSPFW[4]);
drivers/gpu/drm/gma500/cdv_device.c
324
REG_WRITE(DSPFW6, regs->cdv.saveDSPFW[5]);
drivers/gpu/drm/gma500/cdv_device.c
326
REG_WRITE(DSPARB, regs->cdv.saveDSPARB);
drivers/gpu/drm/gma500/cdv_device.c
327
REG_WRITE(ADPA, regs->cdv.saveADPA);
drivers/gpu/drm/gma500/cdv_device.c
329
REG_WRITE(BLC_PWM_CTL2, regs->saveBLC_PWM_CTL2);
drivers/gpu/drm/gma500/cdv_device.c
330
REG_WRITE(LVDS, regs->cdv.saveLVDS);
drivers/gpu/drm/gma500/cdv_device.c
331
REG_WRITE(PFIT_CONTROL, regs->cdv.savePFIT_CONTROL);
drivers/gpu/drm/gma500/cdv_device.c
332
REG_WRITE(PFIT_PGM_RATIOS, regs->cdv.savePFIT_PGM_RATIOS);
drivers/gpu/drm/gma500/cdv_device.c
333
REG_WRITE(BLC_PWM_CTL, regs->saveBLC_PWM_CTL);
drivers/gpu/drm/gma500/cdv_device.c
334
REG_WRITE(PP_ON_DELAYS, regs->cdv.savePP_ON_DELAYS);
drivers/gpu/drm/gma500/cdv_device.c
335
REG_WRITE(PP_OFF_DELAYS, regs->cdv.savePP_OFF_DELAYS);
drivers/gpu/drm/gma500/cdv_device.c
336
REG_WRITE(PP_CYCLE, regs->cdv.savePP_CYCLE);
drivers/gpu/drm/gma500/cdv_device.c
337
REG_WRITE(PP_CONTROL, regs->cdv.savePP_CONTROL);
drivers/gpu/drm/gma500/cdv_device.c
339
REG_WRITE(VGACNTRL, regs->cdv.saveVGACNTRL);
drivers/gpu/drm/gma500/cdv_device.c
341
REG_WRITE(PSB_INT_ENABLE_R, regs->cdv.saveIER);
drivers/gpu/drm/gma500/cdv_device.c
342
REG_WRITE(PSB_INT_MASK_R, regs->cdv.saveIMR);
drivers/gpu/drm/gma500/cdv_device.c
36
REG_WRITE(vga_reg, VGA_DISP_DISABLE);
drivers/gpu/drm/gma500/cdv_device.c
420
REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT));
drivers/gpu/drm/gma500/cdv_device.c
430
REG_WRITE(PORT_HOTPLUG_EN, hotplug);
drivers/gpu/drm/gma500/cdv_device.c
432
REG_WRITE(PORT_HOTPLUG_EN, 0);
drivers/gpu/drm/gma500/cdv_device.c
433
REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT));
drivers/gpu/drm/gma500/cdv_intel_crt.c
113
REG_WRITE(dpll_md_reg,
drivers/gpu/drm/gma500/cdv_intel_crt.c
128
REG_WRITE(adpa_reg, adpa);
drivers/gpu/drm/gma500/cdv_intel_crt.c
162
REG_WRITE(PORT_HOTPLUG_EN, hotplug_en);
drivers/gpu/drm/gma500/cdv_intel_crt.c
178
REG_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
drivers/gpu/drm/gma500/cdv_intel_crt.c
181
REG_WRITE(PORT_HOTPLUG_EN, orig);
drivers/gpu/drm/gma500/cdv_intel_crt.c
68
REG_WRITE(reg, temp);
drivers/gpu/drm/gma500/cdv_intel_display.c
141
REG_WRITE(SB_ADDR, reg);
drivers/gpu/drm/gma500/cdv_intel_display.c
142
REG_WRITE(SB_PCKT,
drivers/gpu/drm/gma500/cdv_intel_display.c
176
REG_WRITE(SB_ADDR, reg);
drivers/gpu/drm/gma500/cdv_intel_display.c
177
REG_WRITE(SB_DATA, val);
drivers/gpu/drm/gma500/cdv_intel_display.c
178
REG_WRITE(SB_PCKT,
drivers/gpu/drm/gma500/cdv_intel_display.c
203
REG_WRITE(DPIO_CFG, 0);
drivers/gpu/drm/gma500/cdv_intel_display.c
205
REG_WRITE(DPIO_CFG, DPIO_MODE_SELECT_0 | DPIO_CMN_RESET_N);
drivers/gpu/drm/gma500/cdv_intel_display.c
228
REG_WRITE(dpll_reg, DPLL_SYNCLOCK_ENABLE | DPLL_VGA_MODE_DIS);
drivers/gpu/drm/gma500/cdv_intel_display.c
476
REG_WRITE(FW_BLC_SELF, (REG_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN));
drivers/gpu/drm/gma500/cdv_intel_display.c
484
REG_WRITE(OV_OVADD, 0/*dev_priv->ovl_offset*/);
drivers/gpu/drm/gma500/cdv_intel_display.c
506
REG_WRITE(DSPFW1, fw);
drivers/gpu/drm/gma500/cdv_intel_display.c
513
REG_WRITE(DSPFW2, fw);
drivers/gpu/drm/gma500/cdv_intel_display.c
515
REG_WRITE(DSPFW3, 0x36000000);
drivers/gpu/drm/gma500/cdv_intel_display.c
522
REG_WRITE(DSPFW5, 0x00040330);
drivers/gpu/drm/gma500/cdv_intel_display.c
528
REG_WRITE(DSPFW5, fw);
drivers/gpu/drm/gma500/cdv_intel_display.c
531
REG_WRITE(DSPFW6, 0x10);
drivers/gpu/drm/gma500/cdv_intel_display.c
536
REG_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
drivers/gpu/drm/gma500/cdv_intel_display.c
543
REG_WRITE(DSPFW1, 0x3f880808);
drivers/gpu/drm/gma500/cdv_intel_display.c
544
REG_WRITE(DSPFW2, 0x0b020202);
drivers/gpu/drm/gma500/cdv_intel_display.c
545
REG_WRITE(DSPFW3, 0x24000000);
drivers/gpu/drm/gma500/cdv_intel_display.c
546
REG_WRITE(DSPFW4, 0x08030202);
drivers/gpu/drm/gma500/cdv_intel_display.c
547
REG_WRITE(DSPFW5, 0x01010101);
drivers/gpu/drm/gma500/cdv_intel_display.c
548
REG_WRITE(DSPFW6, 0x1d0);
drivers/gpu/drm/gma500/cdv_intel_display.c
671
REG_WRITE(PIPE_GMCH_DATA_M(pipe), 0);
drivers/gpu/drm/gma500/cdv_intel_display.c
672
REG_WRITE(PIPE_GMCH_DATA_N(pipe), 0);
drivers/gpu/drm/gma500/cdv_intel_display.c
673
REG_WRITE(PIPE_DP_LINK_M(pipe), 0);
drivers/gpu/drm/gma500/cdv_intel_display.c
674
REG_WRITE(PIPE_DP_LINK_N(pipe), 0);
drivers/gpu/drm/gma500/cdv_intel_display.c
723
REG_WRITE(map->dpll, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE);
drivers/gpu/drm/gma500/cdv_intel_display.c
755
REG_WRITE(LVDS, lvds);
drivers/gpu/drm/gma500/cdv_intel_display.c
763
REG_WRITE(PFIT_CONTROL, 0);
drivers/gpu/drm/gma500/cdv_intel_display.c
768
REG_WRITE(map->dpll,
drivers/gpu/drm/gma500/cdv_intel_display.c
781
REG_WRITE(map->dpll_md, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) | ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
drivers/gpu/drm/gma500/cdv_intel_display.c
784
REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) |
drivers/gpu/drm/gma500/cdv_intel_display.c
786
REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) |
drivers/gpu/drm/gma500/cdv_intel_display.c
788
REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) |
drivers/gpu/drm/gma500/cdv_intel_display.c
790
REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) |
drivers/gpu/drm/gma500/cdv_intel_display.c
792
REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) |
drivers/gpu/drm/gma500/cdv_intel_display.c
794
REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) |
drivers/gpu/drm/gma500/cdv_intel_display.c
799
REG_WRITE(map->size,
drivers/gpu/drm/gma500/cdv_intel_display.c
801
REG_WRITE(map->pos, 0);
drivers/gpu/drm/gma500/cdv_intel_display.c
802
REG_WRITE(map->src,
drivers/gpu/drm/gma500/cdv_intel_display.c
804
REG_WRITE(map->conf, pipeconf);
drivers/gpu/drm/gma500/cdv_intel_display.c
809
REG_WRITE(map->cntr, dspcntr);
drivers/gpu/drm/gma500/cdv_intel_dp.c
1025
REG_WRITE(PIPE_GMCH_DATA_M(pipe),
drivers/gpu/drm/gma500/cdv_intel_dp.c
1028
REG_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
drivers/gpu/drm/gma500/cdv_intel_dp.c
1029
REG_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
drivers/gpu/drm/gma500/cdv_intel_dp.c
1030
REG_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
drivers/gpu/drm/gma500/cdv_intel_dp.c
1085
REG_WRITE(intel_dp->output_reg, (intel_dp->DP | DP_PORT_EN));
drivers/gpu/drm/gma500/cdv_intel_dp.c
1099
REG_WRITE(PFIT_CONTROL, pfit_control);
drivers/gpu/drm/gma500/cdv_intel_dp.c
1360
REG_WRITE(intel_dp->output_reg, dp_reg_value);
drivers/gpu/drm/gma500/cdv_intel_dp.c
1481
REG_WRITE(intel_dp->output_reg, reg);
drivers/gpu/drm/gma500/cdv_intel_dp.c
1633
REG_WRITE(intel_dp->output_reg, reg);
drivers/gpu/drm/gma500/cdv_intel_dp.c
1654
REG_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
drivers/gpu/drm/gma500/cdv_intel_dp.c
1660
REG_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
drivers/gpu/drm/gma500/cdv_intel_dp.c
1940
REG_WRITE(DSPCLK_GATE_D, reg_value);
drivers/gpu/drm/gma500/cdv_intel_dp.c
2022
REG_WRITE(PP_CONTROL, pp_on);
drivers/gpu/drm/gma500/cdv_intel_dp.c
2026
REG_WRITE(BLC_PWM_CTL2, pwm_ctrl);
drivers/gpu/drm/gma500/cdv_intel_dp.c
392
REG_WRITE(PP_CONTROL, pp);
drivers/gpu/drm/gma500/cdv_intel_dp.c
406
REG_WRITE(PP_CONTROL, pp);
drivers/gpu/drm/gma500/cdv_intel_dp.c
426
REG_WRITE(PP_CONTROL, pp);
drivers/gpu/drm/gma500/cdv_intel_dp.c
459
REG_WRITE(PP_CONTROL, pp);
drivers/gpu/drm/gma500/cdv_intel_dp.c
487
REG_WRITE(PP_CONTROL, pp);
drivers/gpu/drm/gma500/cdv_intel_dp.c
503
REG_WRITE(PP_CONTROL, pp);
drivers/gpu/drm/gma500/cdv_intel_dp.c
604
REG_WRITE(ch_data + i,
drivers/gpu/drm/gma500/cdv_intel_dp.c
608
REG_WRITE(ch_ctl,
drivers/gpu/drm/gma500/cdv_intel_dp.c
625
REG_WRITE(ch_ctl,
drivers/gpu/drm/gma500/cdv_intel_hdmi.c
102
REG_WRITE(hdmi_priv->hdmi_reg, hdmib & ~HDMIB_PORT_EN);
drivers/gpu/drm/gma500/cdv_intel_hdmi.c
104
REG_WRITE(hdmi_priv->hdmi_reg, hdmib | HDMIB_PORT_EN);
drivers/gpu/drm/gma500/cdv_intel_hdmi.c
123
REG_WRITE(hdmi_priv->hdmi_reg, hdmi_priv->save_HDMIB);
drivers/gpu/drm/gma500/cdv_intel_hdmi.c
88
REG_WRITE(hdmi_priv->hdmi_reg, hdmib);
drivers/gpu/drm/gma500/cdv_intel_lvds.c
118
REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) |
drivers/gpu/drm/gma500/cdv_intel_lvds.c
129
REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) &
drivers/gpu/drm/gma500/cdv_intel_lvds.c
294
REG_WRITE(PFIT_CONTROL, pfit_control);
drivers/gpu/drm/gma500/cdv_intel_lvds.c
644
REG_WRITE(BLC_PWM_CTL2, pwm);
drivers/gpu/drm/gma500/cdv_intel_lvds.c
93
REG_WRITE(BLC_PWM_CTL,
drivers/gpu/drm/gma500/gma_display.c
115
REG_WRITE(map->cntr, dspcntr);
drivers/gpu/drm/gma500/gma_display.c
124
REG_WRITE(map->base, offset + start);
drivers/gpu/drm/gma500/gma_display.c
127
REG_WRITE(map->base, offset);
drivers/gpu/drm/gma500/gma_display.c
129
REG_WRITE(map->surf, start);
drivers/gpu/drm/gma500/gma_display.c
164
REG_WRITE(palreg + 4 * i,
drivers/gpu/drm/gma500/gma_display.c
225
REG_WRITE(map->dpll, temp);
drivers/gpu/drm/gma500/gma_display.c
229
REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE);
drivers/gpu/drm/gma500/gma_display.c
233
REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE);
drivers/gpu/drm/gma500/gma_display.c
242
REG_WRITE(map->cntr,
drivers/gpu/drm/gma500/gma_display.c
245
REG_WRITE(map->base, REG_READ(map->base));
drivers/gpu/drm/gma500/gma_display.c
253
REG_WRITE(map->conf, temp | PIPEACONF_ENABLE);
drivers/gpu/drm/gma500/gma_display.c
258
REG_WRITE(map->status, temp);
drivers/gpu/drm/gma500/gma_display.c
280
REG_WRITE(VGACNTRL, VGA_DISP_DISABLE);
drivers/gpu/drm/gma500/gma_display.c
291
REG_WRITE(map->cntr,
drivers/gpu/drm/gma500/gma_display.c
294
REG_WRITE(map->base, REG_READ(map->base));
drivers/gpu/drm/gma500/gma_display.c
301
REG_WRITE(map->conf, temp & ~PIPEACONF_ENABLE);
drivers/gpu/drm/gma500/gma_display.c
313
REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE);
drivers/gpu/drm/gma500/gma_display.c
326
REG_WRITE(DSPARB, 0x3F3E);
drivers/gpu/drm/gma500/gma_display.c
351
REG_WRITE(control, temp);
drivers/gpu/drm/gma500/gma_display.c
352
REG_WRITE(base, 0);
drivers/gpu/drm/gma500/gma_display.c
423
REG_WRITE(control, temp);
drivers/gpu/drm/gma500/gma_display.c
424
REG_WRITE(base, addr);
drivers/gpu/drm/gma500/gma_display.c
467
REG_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
drivers/gpu/drm/gma500/gma_display.c
468
REG_WRITE((pipe == 0) ? CURABASE : CURBBASE, addr);
drivers/gpu/drm/gma500/gma_display.c
634
REG_WRITE(map->dpll,
drivers/gpu/drm/gma500/gma_display.c
640
REG_WRITE(map->fp0, crtc_state->saveFP0);
drivers/gpu/drm/gma500/gma_display.c
643
REG_WRITE(map->fp1, crtc_state->saveFP1);
drivers/gpu/drm/gma500/gma_display.c
646
REG_WRITE(map->dpll, crtc_state->saveDPLL);
drivers/gpu/drm/gma500/gma_display.c
650
REG_WRITE(map->htotal, crtc_state->saveHTOTAL);
drivers/gpu/drm/gma500/gma_display.c
651
REG_WRITE(map->hblank, crtc_state->saveHBLANK);
drivers/gpu/drm/gma500/gma_display.c
652
REG_WRITE(map->hsync, crtc_state->saveHSYNC);
drivers/gpu/drm/gma500/gma_display.c
653
REG_WRITE(map->vtotal, crtc_state->saveVTOTAL);
drivers/gpu/drm/gma500/gma_display.c
654
REG_WRITE(map->vblank, crtc_state->saveVBLANK);
drivers/gpu/drm/gma500/gma_display.c
655
REG_WRITE(map->vsync, crtc_state->saveVSYNC);
drivers/gpu/drm/gma500/gma_display.c
656
REG_WRITE(map->stride, crtc_state->saveDSPSTRIDE);
drivers/gpu/drm/gma500/gma_display.c
658
REG_WRITE(map->size, crtc_state->saveDSPSIZE);
drivers/gpu/drm/gma500/gma_display.c
659
REG_WRITE(map->pos, crtc_state->saveDSPPOS);
drivers/gpu/drm/gma500/gma_display.c
661
REG_WRITE(map->src, crtc_state->savePIPESRC);
drivers/gpu/drm/gma500/gma_display.c
662
REG_WRITE(map->base, crtc_state->saveDSPBASE);
drivers/gpu/drm/gma500/gma_display.c
663
REG_WRITE(map->conf, crtc_state->savePIPECONF);
drivers/gpu/drm/gma500/gma_display.c
667
REG_WRITE(map->cntr, crtc_state->saveDSPCNTR);
drivers/gpu/drm/gma500/gma_display.c
668
REG_WRITE(map->base, crtc_state->saveDSPBASE);
drivers/gpu/drm/gma500/gma_display.c
674
REG_WRITE(palette_reg + (i << 2), crtc_state->savePalette[i]);
drivers/gpu/drm/gma500/gma_display.c
91
REG_WRITE(map->stride, fb->pitches[0]);
drivers/gpu/drm/gma500/intel_i2c.c
59
REG_WRITE(chan->reg, reserved | clock_bits);
drivers/gpu/drm/gma500/intel_i2c.c
81
REG_WRITE(chan->reg, reserved | data_bits);
drivers/gpu/drm/gma500/oaktrail_crtc.c
332
REG_WRITE(DSPARB, 0x3f80);
drivers/gpu/drm/gma500/oaktrail_crtc.c
333
REG_WRITE(DSPFW1, 0x3f8f0404);
drivers/gpu/drm/gma500/oaktrail_crtc.c
334
REG_WRITE(DSPFW2, 0x04040f04);
drivers/gpu/drm/gma500/oaktrail_crtc.c
335
REG_WRITE(DSPFW3, 0x0);
drivers/gpu/drm/gma500/oaktrail_crtc.c
336
REG_WRITE(DSPFW4, 0x04040404);
drivers/gpu/drm/gma500/oaktrail_crtc.c
337
REG_WRITE(DSPFW5, 0x04040404);
drivers/gpu/drm/gma500/oaktrail_crtc.c
338
REG_WRITE(DSPFW6, 0x78);
drivers/gpu/drm/gma500/oaktrail_crtc.c
339
REG_WRITE(DSPCHICKENBIT, REG_READ(DSPCHICKENBIT) | 0xc040);
drivers/gpu/drm/gma500/oaktrail_crtc.c
428
REG_WRITE(PFIT_CONTROL, 0);
drivers/gpu/drm/gma500/oaktrail_crtc.c
619
REG_WRITE(map->stride, fb->pitches[0]);
drivers/gpu/drm/gma500/oaktrail_crtc.c
643
REG_WRITE(map->cntr, dspcntr);
drivers/gpu/drm/gma500/oaktrail_crtc.c
645
REG_WRITE(map->base, offset);
drivers/gpu/drm/gma500/oaktrail_crtc.c
647
REG_WRITE(map->surf, start);
drivers/gpu/drm/gma500/oaktrail_device.c
100
REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2)));
drivers/gpu/drm/gma500/oaktrail_device.c
101
REG_WRITE(BLC_PWM_CTL, value | (value << 16));
drivers/gpu/drm/gma500/oaktrail_device.c
69
REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2)));
drivers/gpu/drm/gma500/oaktrail_device.c
70
REG_WRITE(BLC_PWM_CTL, (max_pwm_blc << 16) | blc_pwm_ctl);
drivers/gpu/drm/gma500/oaktrail_hdmi.c
293
REG_WRITE(VGACNTRL, VGA_DISP_DISABLE);
drivers/gpu/drm/gma500/oaktrail_hdmi.c
298
REG_WRITE(DPLL_CTRL, dpll | (DPLL_PWRDN | DPLL_RESET));
drivers/gpu/drm/gma500/oaktrail_hdmi.c
299
REG_WRITE(DPLL_DIV_CTRL, 0x00000000);
drivers/gpu/drm/gma500/oaktrail_hdmi.c
300
REG_WRITE(DPLL_STATUS, 0x1);
drivers/gpu/drm/gma500/oaktrail_hdmi.c
315
REG_WRITE(DPLL_CTRL, 0x00000008);
drivers/gpu/drm/gma500/oaktrail_hdmi.c
316
REG_WRITE(DPLL_DIV_CTRL, ((clock.nf << 6) | clock.nr));
drivers/gpu/drm/gma500/oaktrail_hdmi.c
317
REG_WRITE(DPLL_ADJUST, ((clock.nf >> 14) - 1));
drivers/gpu/drm/gma500/oaktrail_hdmi.c
318
REG_WRITE(DPLL_CTRL, (dpll | (clock.np << DPLL_PDIV_SHIFT) | DPLL_ENSTAT | DPLL_DITHEN));
drivers/gpu/drm/gma500/oaktrail_hdmi.c
319
REG_WRITE(DPLL_UPDATE, 0x80000000);
drivers/gpu/drm/gma500/oaktrail_hdmi.c
320
REG_WRITE(DPLL_CLK_ENABLE, 0x80050102);
drivers/gpu/drm/gma500/oaktrail_hdmi.c
331
REG_WRITE(htot_reg, temp);
drivers/gpu/drm/gma500/oaktrail_hdmi.c
332
REG_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16));
drivers/gpu/drm/gma500/oaktrail_hdmi.c
333
REG_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16));
drivers/gpu/drm/gma500/oaktrail_hdmi.c
334
REG_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) | ((adjusted_mode->crtc_vtotal - 1) << 16));
drivers/gpu/drm/gma500/oaktrail_hdmi.c
335
REG_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) | ((adjusted_mode->crtc_vblank_end - 1) << 16));
drivers/gpu/drm/gma500/oaktrail_hdmi.c
336
REG_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16));
drivers/gpu/drm/gma500/oaktrail_hdmi.c
337
REG_WRITE(pipesrc_reg, ((mode->crtc_hdisplay - 1) << 16) | (mode->crtc_vdisplay - 1));
drivers/gpu/drm/gma500/oaktrail_hdmi.c
339
REG_WRITE(PCH_HTOTAL_B, (adjusted_mode->crtc_hdisplay - 1) | ((adjusted_mode->crtc_htotal - 1) << 16));
drivers/gpu/drm/gma500/oaktrail_hdmi.c
340
REG_WRITE(PCH_HBLANK_B, (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16));
drivers/gpu/drm/gma500/oaktrail_hdmi.c
341
REG_WRITE(PCH_HSYNC_B, (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16));
drivers/gpu/drm/gma500/oaktrail_hdmi.c
342
REG_WRITE(PCH_VTOTAL_B, (adjusted_mode->crtc_vdisplay - 1) | ((adjusted_mode->crtc_vtotal - 1) << 16));
drivers/gpu/drm/gma500/oaktrail_hdmi.c
343
REG_WRITE(PCH_VBLANK_B, (adjusted_mode->crtc_vblank_start - 1) | ((adjusted_mode->crtc_vblank_end - 1) << 16));
drivers/gpu/drm/gma500/oaktrail_hdmi.c
344
REG_WRITE(PCH_VSYNC_B, (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16));
drivers/gpu/drm/gma500/oaktrail_hdmi.c
345
REG_WRITE(PCH_PIPEBSRC, ((mode->crtc_hdisplay - 1) << 16) | (mode->crtc_vdisplay - 1));
drivers/gpu/drm/gma500/oaktrail_hdmi.c
350
REG_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1));
drivers/gpu/drm/gma500/oaktrail_hdmi.c
351
REG_WRITE(dsppos_reg, 0);
drivers/gpu/drm/gma500/oaktrail_hdmi.c
369
REG_WRITE(pipeconf_reg, pipeconf);
drivers/gpu/drm/gma500/oaktrail_hdmi.c
372
REG_WRITE(PCH_PIPEBCONF, pipeconf);
drivers/gpu/drm/gma500/oaktrail_hdmi.c
376
REG_WRITE(dspcntr_reg, dspcntr);
drivers/gpu/drm/gma500/oaktrail_hdmi.c
393
REG_WRITE(VGACNTRL, 0x80000000);
drivers/gpu/drm/gma500/oaktrail_hdmi.c
398
REG_WRITE(DSPBCNTR, temp & ~DISPLAY_PLANE_ENABLE);
drivers/gpu/drm/gma500/oaktrail_hdmi.c
401
REG_WRITE(DSPBSURF, REG_READ(DSPBSURF));
drivers/gpu/drm/gma500/oaktrail_hdmi.c
408
REG_WRITE(PIPEBCONF, temp & ~PIPEACONF_ENABLE);
drivers/gpu/drm/gma500/oaktrail_hdmi.c
415
REG_WRITE(PCH_PIPEBCONF, temp & ~PIPEACONF_ENABLE);
drivers/gpu/drm/gma500/oaktrail_hdmi.c
425
REG_WRITE(DPLL_CTRL, temp | (DPLL_PWRDN | DPLL_RESET));
drivers/gpu/drm/gma500/oaktrail_hdmi.c
426
REG_WRITE(DPLL_STATUS, 0x1);
drivers/gpu/drm/gma500/oaktrail_hdmi.c
439
REG_WRITE(DPLL_CTRL, temp & ~(DPLL_PWRDN | DPLL_RESET));
drivers/gpu/drm/gma500/oaktrail_hdmi.c
441
REG_WRITE(DPLL_CLK_ENABLE, temp | DPLL_EN_DISP | DPLL_SEL_HDMI | DPLL_EN_HDMI);
drivers/gpu/drm/gma500/oaktrail_hdmi.c
450
REG_WRITE(PIPEBCONF, temp | PIPEACONF_ENABLE);
drivers/gpu/drm/gma500/oaktrail_hdmi.c
457
REG_WRITE(PCH_PIPEBCONF, temp | PIPEACONF_ENABLE);
drivers/gpu/drm/gma500/oaktrail_hdmi.c
466
REG_WRITE(DSPBCNTR, temp | DISPLAY_PLANE_ENABLE);
drivers/gpu/drm/gma500/oaktrail_hdmi.c
468
REG_WRITE(DSPBSURF, REG_READ(DSPBSURF));
drivers/gpu/drm/gma500/oaktrail_hdmi.c
476
REG_WRITE(DSPARB, 0x00003fbf);
drivers/gpu/drm/gma500/oaktrail_hdmi.c
479
REG_WRITE(0x70034, 0x3f880a0a);
drivers/gpu/drm/gma500/oaktrail_hdmi.c
482
REG_WRITE(0x70038, 0x0b060808);
drivers/gpu/drm/gma500/oaktrail_hdmi.c
485
REG_WRITE(0x70050, 0x08030404);
drivers/gpu/drm/gma500/oaktrail_hdmi.c
488
REG_WRITE(0x70054, 0x04040404);
drivers/gpu/drm/gma500/oaktrail_hdmi.c
491
REG_WRITE(0x70400, 0x4000);
drivers/gpu/drm/gma500/oaktrail_lvds.c
112
REG_WRITE(LVDS, lvds_port);
drivers/gpu/drm/gma500/oaktrail_lvds.c
133
REG_WRITE(PFIT_CONTROL, 0);
drivers/gpu/drm/gma500/oaktrail_lvds.c
139
REG_WRITE(PFIT_CONTROL, PFIT_ENABLE);
drivers/gpu/drm/gma500/oaktrail_lvds.c
143
REG_WRITE(PFIT_CONTROL, PFIT_ENABLE |
drivers/gpu/drm/gma500/oaktrail_lvds.c
146
REG_WRITE(PFIT_CONTROL, PFIT_ENABLE |
drivers/gpu/drm/gma500/oaktrail_lvds.c
149
REG_WRITE(PFIT_CONTROL, PFIT_ENABLE);
drivers/gpu/drm/gma500/oaktrail_lvds.c
151
REG_WRITE(PFIT_CONTROL, PFIT_ENABLE);
drivers/gpu/drm/gma500/oaktrail_lvds.c
47
REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) |
drivers/gpu/drm/gma500/oaktrail_lvds.c
58
REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) &
drivers/gpu/drm/gma500/psb_device.c
71
REG_WRITE(BLC_PWM_CTL,
drivers/gpu/drm/gma500/psb_drv.h
702
REG_WRITE(reg, val);
drivers/gpu/drm/gma500/psb_intel_display.c
215
REG_WRITE(PFIT_CONTROL, 0);
drivers/gpu/drm/gma500/psb_intel_display.c
220
REG_WRITE(map->fp0, fp);
drivers/gpu/drm/gma500/psb_intel_display.c
221
REG_WRITE(map->dpll, dpll & ~DPLL_VCO_ENABLE);
drivers/gpu/drm/gma500/psb_intel_display.c
251
REG_WRITE(LVDS, lvds);
drivers/gpu/drm/gma500/psb_intel_display.c
255
REG_WRITE(map->fp0, fp);
drivers/gpu/drm/gma500/psb_intel_display.c
256
REG_WRITE(map->dpll, dpll);
drivers/gpu/drm/gma500/psb_intel_display.c
262
REG_WRITE(map->dpll, dpll);
drivers/gpu/drm/gma500/psb_intel_display.c
268
REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) |
drivers/gpu/drm/gma500/psb_intel_display.c
270
REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) |
drivers/gpu/drm/gma500/psb_intel_display.c
272
REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) |
drivers/gpu/drm/gma500/psb_intel_display.c
274
REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) |
drivers/gpu/drm/gma500/psb_intel_display.c
276
REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) |
drivers/gpu/drm/gma500/psb_intel_display.c
278
REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) |
drivers/gpu/drm/gma500/psb_intel_display.c
283
REG_WRITE(map->size,
drivers/gpu/drm/gma500/psb_intel_display.c
285
REG_WRITE(map->pos, 0);
drivers/gpu/drm/gma500/psb_intel_display.c
286
REG_WRITE(map->src,
drivers/gpu/drm/gma500/psb_intel_display.c
288
REG_WRITE(map->conf, pipeconf);
drivers/gpu/drm/gma500/psb_intel_display.c
293
REG_WRITE(map->cntr, dspcntr);
drivers/gpu/drm/gma500/psb_intel_display.c
470
REG_WRITE(control[gma_crtc->pipe], 0);
drivers/gpu/drm/gma500/psb_intel_display.c
471
REG_WRITE(base[gma_crtc->pipe], 0);
drivers/gpu/drm/gma500/psb_intel_lvds.c
148
REG_WRITE(BLC_PWM_CTL,
drivers/gpu/drm/gma500/psb_intel_lvds.c
192
REG_WRITE(BLC_PWM_CTL,
drivers/gpu/drm/gma500/psb_intel_lvds.c
221
REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) |
drivers/gpu/drm/gma500/psb_intel_lvds.c
232
REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) &
drivers/gpu/drm/gma500/psb_intel_lvds.c
309
REG_WRITE(BLC_PWM_CTL, lvds_priv->saveBLC_PWM_CTL);
drivers/gpu/drm/gma500/psb_intel_lvds.c
310
REG_WRITE(PFIT_CONTROL, lvds_priv->savePFIT_CONTROL);
drivers/gpu/drm/gma500/psb_intel_lvds.c
311
REG_WRITE(PFIT_PGM_RATIOS, lvds_priv->savePFIT_PGM_RATIOS);
drivers/gpu/drm/gma500/psb_intel_lvds.c
312
REG_WRITE(LVDSPP_ON, lvds_priv->savePP_ON);
drivers/gpu/drm/gma500/psb_intel_lvds.c
313
REG_WRITE(LVDSPP_OFF, lvds_priv->savePP_OFF);
drivers/gpu/drm/gma500/psb_intel_lvds.c
315
REG_WRITE(PP_CYCLE, lvds_priv->savePP_CYCLE);
drivers/gpu/drm/gma500/psb_intel_lvds.c
316
REG_WRITE(PP_CONTROL, lvds_priv->savePP_CONTROL);
drivers/gpu/drm/gma500/psb_intel_lvds.c
317
REG_WRITE(LVDS, lvds_priv->saveLVDS);
drivers/gpu/drm/gma500/psb_intel_lvds.c
320
REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) |
drivers/gpu/drm/gma500/psb_intel_lvds.c
326
REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) &
drivers/gpu/drm/gma500/psb_intel_lvds.c
486
REG_WRITE(PFIT_CONTROL, pfit_control);
drivers/gpu/drm/gma500/psb_intel_sdvo.c
1754
REG_WRITE(sdvo->sdvo_reg, sdvo->saveSDVO);
drivers/gpu/drm/gma500/psb_irq.c
237
REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT));
drivers/media/usb/dvb-usb-v2/ce6230.c
34
case REG_WRITE:
drivers/net/wireless/ath/ath9k/ani.c
135
REG_WRITE(ah, AR_PHY_ERR_1, 0);
drivers/net/wireless/ath/ath9k/ani.c
136
REG_WRITE(ah, AR_PHY_ERR_2, 0);
drivers/net/wireless/ath/ath9k/ani.c
137
REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
drivers/net/wireless/ath/ath9k/ani.c
138
REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
drivers/net/wireless/ath/ath9k/ani.c
451
REG_WRITE(ah, AR_FILT_OFDM, 0);
drivers/net/wireless/ath/ath9k/ani.c
452
REG_WRITE(ah, AR_FILT_CCK, 0);
drivers/net/wireless/ath/ath9k/ani.c
453
REG_WRITE(ah, AR_MIBC,
drivers/net/wireless/ath/ath9k/ani.c
456
REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
drivers/net/wireless/ath/ath9k/ani.c
457
REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
drivers/net/wireless/ath/ath9k/ani.c
469
REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC);
drivers/net/wireless/ath/ath9k/ani.c
471
REG_WRITE(ah, AR_MIBC, AR_MIBC_CMC);
drivers/net/wireless/ath/ath9k/ani.c
472
REG_WRITE(ah, AR_FILT_OFDM, 0);
drivers/net/wireless/ath/ath9k/ani.c
473
REG_WRITE(ah, AR_FILT_CCK, 0);
drivers/net/wireless/ath/ath9k/ar5008_phy.c
1256
REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
drivers/net/wireless/ath/ath9k/ar5008_phy.c
1257
REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
drivers/net/wireless/ath/ath9k/ar5008_phy.c
236
REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
drivers/net/wireless/ath/ath9k/ar5008_phy.c
239
REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
drivers/net/wireless/ath/ath9k/ar5008_phy.c
268
REG_WRITE(ah, AR_PHY(0x37), reg32);
drivers/net/wireless/ath/ath9k/ar5008_phy.c
312
REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
drivers/net/wireless/ath/ath9k/ar5008_phy.c
313
REG_WRITE(ah, chan_mask_reg[i], chan_mask);
drivers/net/wireless/ath/ath9k/ar5008_phy.c
345
REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
drivers/net/wireless/ath/ath9k/ar5008_phy.c
346
REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
drivers/net/wireless/ath/ath9k/ar5008_phy.c
356
REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
drivers/net/wireless/ath/ath9k/ar5008_phy.c
357
REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
drivers/net/wireless/ath/ath9k/ar5008_phy.c
367
REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
drivers/net/wireless/ath/ath9k/ar5008_phy.c
368
REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
drivers/net/wireless/ath/ath9k/ar5008_phy.c
378
REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
drivers/net/wireless/ath/ath9k/ar5008_phy.c
379
REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
drivers/net/wireless/ath/ath9k/ar5008_phy.c
389
REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
drivers/net/wireless/ath/ath9k/ar5008_phy.c
390
REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
drivers/net/wireless/ath/ath9k/ar5008_phy.c
400
REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
drivers/net/wireless/ath/ath9k/ar5008_phy.c
401
REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
drivers/net/wireless/ath/ath9k/ar5008_phy.c
411
REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
drivers/net/wireless/ath/ath9k/ar5008_phy.c
412
REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
drivers/net/wireless/ath/ath9k/ar5008_phy.c
422
REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
drivers/net/wireless/ath/ath9k/ar5008_phy.c
423
REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
drivers/net/wireless/ath/ath9k/ar5008_phy.c
468
REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
drivers/net/wireless/ath/ath9k/ar5008_phy.c
475
REG_WRITE(ah, AR_PHY_SPUR_REG, new);
drivers/net/wireless/ath/ath9k/ar5008_phy.c
486
REG_WRITE(ah, AR_PHY_TIMING11, new);
drivers/net/wireless/ath/ath9k/ar5008_phy.c
585
REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
drivers/net/wireless/ath/ath9k/ar5008_phy.c
605
REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
drivers/net/wireless/ath/ath9k/ar5008_phy.c
606
REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
drivers/net/wireless/ath/ath9k/ar5008_phy.c
614
REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
drivers/net/wireless/ath/ath9k/ar5008_phy.c
615
REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
drivers/net/wireless/ath/ath9k/ar5008_phy.c
622
REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
drivers/net/wireless/ath/ath9k/ar5008_phy.c
631
REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
drivers/net/wireless/ath/ath9k/ar5008_phy.c
666
REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
drivers/net/wireless/ath/ath9k/ar5008_phy.c
675
REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
drivers/net/wireless/ath/ath9k/ar5008_phy.c
684
REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val);
drivers/net/wireless/ath/ath9k/ar5008_phy.c
709
REG_WRITE(ah, AR_PHY_TURBO, phymode);
drivers/net/wireless/ath/ath9k/ar5008_phy.c
715
REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
drivers/net/wireless/ath/ath9k/ar5008_phy.c
716
REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
drivers/net/wireless/ath/ath9k/ar5008_phy.c
741
REG_WRITE(ah, AR_PHY(0), 0x00000007);
drivers/net/wireless/ath/ath9k/ar5008_phy.c
744
REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
drivers/net/wireless/ath/ath9k/ar5008_phy.c
749
REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
drivers/net/wireless/ath/ath9k/ar5008_phy.c
760
REG_WRITE(ah, reg, val);
drivers/net/wireless/ath/ath9k/ar5008_phy.c
792
REG_WRITE(ah, reg, val);
drivers/net/wireless/ath/ath9k/ar5008_phy.c
845
REG_WRITE(ah, AR_PHY_MODE, rfMode);
drivers/net/wireless/ath/ath9k/ar5008_phy.c
850
REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
drivers/net/wireless/ath/ath9k/ar5008_phy.c
889
REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
drivers/net/wireless/ath/ath9k/ar5008_phy.c
900
REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
drivers/net/wireless/ath/ath9k/ar5008_phy.c
908
REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
drivers/net/wireless/ath/ath9k/ar5008_phy.c
909
REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
drivers/net/wireless/ath/ath9k/ar5008_phy.c
98
REG_WRITE(ah, INI_RA(array, r, 0), data[r]);
drivers/net/wireless/ath/ath9k/ar9002_calib.c
311
REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
drivers/net/wireless/ath/ath9k/ar9002_calib.c
318
REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
drivers/net/wireless/ath/ath9k/ar9002_calib.c
366
REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
drivers/net/wireless/ath/ath9k/ar9002_calib.c
372
REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
drivers/net/wireless/ath/ath9k/ar9002_calib.c
494
REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0);
drivers/net/wireless/ath/ath9k/ar9002_calib.c
502
REG_WRITE(ah, AR9285_AN_RF2G6, regVal);
drivers/net/wireless/ath/ath9k/ar9002_calib.c
509
REG_WRITE(ah, AR9285_AN_RF2G6, regVal);
drivers/net/wireless/ath/ath9k/ar9002_calib.c
536
REG_WRITE(ah, regList[i][0], regList[i][1]);
drivers/net/wireless/ath/ath9k/ar9002_calib.c
569
REG_WRITE(ah, 0x7834, regVal);
drivers/net/wireless/ath/ath9k/ar9002_calib.c
572
REG_WRITE(ah, 0x9808, regVal);
drivers/net/wireless/ath/ath9k/ar9002_calib.c
589
REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0);
drivers/net/wireless/ath/ath9k/ar9002_calib.c
597
REG_WRITE(ah, 0x7834, regVal);
drivers/net/wireless/ath/ath9k/ar9002_calib.c
603
REG_WRITE(ah, 0x7834, regVal);
drivers/net/wireless/ath/ath9k/ar9002_calib.c
61
REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
drivers/net/wireless/ath/ath9k/ar9002_calib.c
634
REG_WRITE(ah, 0x7834, regVal);
drivers/net/wireless/ath/ath9k/ar9002_calib.c
637
REG_WRITE(ah, 0x9808, regVal);
drivers/net/wireless/ath/ath9k/ar9002_calib.c
640
REG_WRITE(ah, regList[i][0], regList[i][1]);
drivers/net/wireless/ath/ath9k/ar9002_calib.c
66
REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN);
drivers/net/wireless/ath/ath9k/ar9002_calib.c
70
REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER);
drivers/net/wireless/ath/ath9k/ar9002_calib.c
831
REG_WRITE(ah, AR9285_RF2G5,
drivers/net/wireless/ath/ath9k/ar9002_calib.c
835
REG_WRITE(ah, AR9285_RF2G5,
drivers/net/wireless/ath/ath9k/ar9002_calib.c
840
REG_WRITE(ah, AR9285_RF2G5, reg_rf2g5_org);
drivers/net/wireless/ath/ath9k/ar9002_calib.c
865
REG_WRITE(ah, AR_PHY_AGC_CONTROL(ah),
drivers/net/wireless/ath/ath9k/ar9002_hw.c
217
REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
drivers/net/wireless/ath/ath9k/ar9002_hw.c
223
REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
drivers/net/wireless/ath/ath9k/ar9002_hw.c
224
REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
drivers/net/wireless/ath/ath9k/ar9002_hw.c
227
REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
drivers/net/wireless/ath/ath9k/ar9002_hw.c
228
REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
drivers/net/wireless/ath/ath9k/ar9002_hw.c
229
REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
drivers/net/wireless/ath/ath9k/ar9002_hw.c
235
REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
drivers/net/wireless/ath/ath9k/ar9002_hw.c
237
REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
drivers/net/wireless/ath/ath9k/ar9002_hw.c
238
REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
drivers/net/wireless/ath/ath9k/ar9002_hw.c
239
REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
drivers/net/wireless/ath/ath9k/ar9002_hw.c
242
REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
drivers/net/wireless/ath/ath9k/ar9002_hw.c
289
REG_WRITE(ah, AR_WA(ah), val);
drivers/net/wireless/ath/ath9k/ar9002_hw.c
317
REG_WRITE(ah, AR_WA(ah), val);
drivers/net/wireless/ath/ath9k/ar9002_hw.c
331
REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
drivers/net/wireless/ath/ath9k/ar9002_hw.c
333
REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
drivers/net/wireless/ath/ath9k/ar9002_hw.c
347
REG_WRITE(ah, AR_PHY(0), 0x00000007);
drivers/net/wireless/ath/ath9k/ar9002_hw.c
448
REG_WRITE(ah, reg, val|val_orig);
drivers/net/wireless/ath/ath9k/ar9002_hw.c
450
REG_WRITE(ah, reg, val);
drivers/net/wireless/ath/ath9k/ar9002_mac.c
113
REG_WRITE(ah, AR_ISR_S0, s0_s);
drivers/net/wireless/ath/ath9k/ar9002_mac.c
115
REG_WRITE(ah, AR_ISR_S1, s1_s);
drivers/net/wireless/ath/ath9k/ar9002_mac.c
160
REG_WRITE(ah, AR_ISR_S5, s5_s);
drivers/net/wireless/ath/ath9k/ar9002_mac.c
166
REG_WRITE(ah, AR_ISR, isr);
drivers/net/wireless/ath/ath9k/ar9002_mac.c
195
REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
drivers/net/wireless/ath/ath9k/ar9002_mac.c
196
REG_WRITE(ah, AR_RC, 0);
drivers/net/wireless/ath/ath9k/ar9002_mac.c
204
REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR(ah), sync_cause);
drivers/net/wireless/ath/ath9k/ar9002_mac.c
24
REG_WRITE(ah, AR_CR, AR_CR_RXE(ah));
drivers/net/wireless/ath/ath9k/ar9002_mac.c
82
REG_WRITE(ah, AR_ISR_S2, isr2);
drivers/net/wireless/ath/ath9k/ar9002_phy.c
101
REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
drivers/net/wireless/ath/ath9k/ar9002_phy.c
104
REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
drivers/net/wireless/ath/ath9k/ar9002_phy.c
153
REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
drivers/net/wireless/ath/ath9k/ar9002_phy.c
233
REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
drivers/net/wireless/ath/ath9k/ar9002_phy.c
240
REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
drivers/net/wireless/ath/ath9k/ar9002_phy.c
270
REG_WRITE(ah, AR_PHY_TIMING11, newVal);
drivers/net/wireless/ath/ath9k/ar9002_phy.c
273
REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
drivers/net/wireless/ath/ath9k/ar9002_phy.c
411
REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regval);
drivers/net/wireless/ath/ath9k/ar9002_phy.c
430
REG_WRITE(ah, AR_BT_COEX_MODE2, btcoex->bt_coex_mode2);
drivers/net/wireless/ath/ath9k/ar9002_phy.c
432
REG_WRITE(ah, AR_PHY_SWITCH_COM, ATH_BT_COEX_ANT_DIV_SWITCH_COM);
drivers/net/wireless/ath/ath9k/ar9002_phy.c
445
REG_WRITE(ah, AR_BT_COEX_MODE2, btcoex->bt_coex_mode2);
drivers/net/wireless/ath/ath9k/ar9002_phy.c
451
REG_WRITE(ah, AR_PHY_SWITCH_COM, 0);
drivers/net/wireless/ath/ath9k/ar9002_phy.c
467
REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regval);
drivers/net/wireless/ath/ath9k/ar9002_phy.c
472
REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
drivers/net/wireless/ath/ath9k/ar9002_phy.c
560
REG_WRITE(ah, AR_CR, AR_CR_RXD);
drivers/net/wireless/ath/ath9k/ar9002_phy.c
561
REG_WRITE(ah, AR_DLCL_IFS(qnum), 0);
drivers/net/wireless/ath/ath9k/ar9002_phy.c
562
REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 20);
drivers/net/wireless/ath/ath9k/ar9002_phy.c
563
REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 20);
drivers/net/wireless/ath/ath9k/ar9002_phy.c
564
REG_WRITE(ah, AR_D_FPCTL, 0x10|qnum);
drivers/net/wireless/ath/ath9k/ar9002_phy.c
565
REG_WRITE(ah, AR_TIME_OUT, 0x00000400);
drivers/net/wireless/ath/ath9k/ar9002_phy.c
566
REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff);
drivers/net/wireless/ath/ath9k/ar9003_aic.c
111
REG_WRITE(ah, AR_PHY_BT_COEX_4, 0x2c200a00);
drivers/net/wireless/ath/ath9k/ar9003_aic.c
112
REG_WRITE(ah, AR_PHY_BT_COEX_5, 0x5c4e4438);
drivers/net/wireless/ath/ath9k/ar9003_aic.c
155
REG_WRITE(ah, (AR_PHY_AIC_SRAM_ADDR_B0 + 0x3000),
drivers/net/wireless/ath/ath9k/ar9003_aic.c
160
REG_WRITE(ah, (AR_PHY_AIC_SRAM_DATA_B0 + 0x3000),
drivers/net/wireless/ath/ath9k/ar9003_aic.c
171
REG_WRITE(ah, (AR_PHY_AIC_SRAM_ADDR_B0 + 0x3000),
drivers/net/wireless/ath/ath9k/ar9003_aic.c
176
REG_WRITE(ah, (AR_PHY_AIC_SRAM_DATA_B0 + 0x3000), 0);
drivers/net/wireless/ath/ath9k/ar9003_aic.c
180
REG_WRITE(ah, AR_PHY_AIC_CTRL_0_B0,
drivers/net/wireless/ath/ath9k/ar9003_aic.c
190
REG_WRITE(ah, AR_PHY_AIC_CTRL_0_B1,
drivers/net/wireless/ath/ath9k/ar9003_aic.c
197
REG_WRITE(ah, AR_PHY_AIC_CTRL_1_B0,
drivers/net/wireless/ath/ath9k/ar9003_aic.c
206
REG_WRITE(ah, AR_PHY_AIC_CTRL_1_B1,
drivers/net/wireless/ath/ath9k/ar9003_aic.c
210
REG_WRITE(ah, AR_PHY_AIC_CTRL_2_B0,
drivers/net/wireless/ath/ath9k/ar9003_aic.c
220
REG_WRITE(ah, AR_PHY_AIC_CTRL_3_B0,
drivers/net/wireless/ath/ath9k/ar9003_aic.c
230
REG_WRITE(ah, AR_PHY_AIC_CTRL_4_B0,
drivers/net/wireless/ath/ath9k/ar9003_aic.c
237
REG_WRITE(ah, AR_PHY_AIC_CTRL_4_B1,
drivers/net/wireless/ath/ath9k/ar9003_aic.c
247
REG_WRITE(ah, ATH_AIC_BT_JUPITER_CTRL,
drivers/net/wireless/ath/ath9k/ar9003_aic.c
440
REG_WRITE(ah, ATH_AIC_BT_JUPITER_CTRL,
drivers/net/wireless/ath/ath9k/ar9003_aic.c
484
REG_WRITE(ah, AR_PHY_AIC_SRAM_ADDR_B1,
drivers/net/wireless/ath/ath9k/ar9003_aic.c
549
REG_WRITE(ah, AR_PHY_AIC_SRAM_ADDR_B1, ATH_AIC_SRAM_AUTO_INCREMENT);
drivers/net/wireless/ath/ath9k/ar9003_aic.c
552
REG_WRITE(ah, AR_PHY_AIC_SRAM_DATA_B1, aic->aic_sram[i]);
drivers/net/wireless/ath/ath9k/ar9003_aic.c
556
REG_WRITE(ah, 0xa6b0, 0x80);
drivers/net/wireless/ath/ath9k/ar9003_aic.c
557
REG_WRITE(ah, 0xa6b4, 0x5b2df0);
drivers/net/wireless/ath/ath9k/ar9003_aic.c
558
REG_WRITE(ah, 0xa6b8, 0x10762cc8);
drivers/net/wireless/ath/ath9k/ar9003_aic.c
559
REG_WRITE(ah, 0xa6bc, 0x1219a4b);
drivers/net/wireless/ath/ath9k/ar9003_aic.c
560
REG_WRITE(ah, 0xa6c0, 0x1e01);
drivers/net/wireless/ath/ath9k/ar9003_aic.c
561
REG_WRITE(ah, 0xb6b4, 0xf0);
drivers/net/wireless/ath/ath9k/ar9003_aic.c
562
REG_WRITE(ah, 0xb6c0, 0x1e01);
drivers/net/wireless/ath/ath9k/ar9003_aic.c
563
REG_WRITE(ah, 0xb6b0, 0x81);
drivers/net/wireless/ath/ath9k/ar9003_aic.c
564
REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX4, 0x40000000);
drivers/net/wireless/ath/ath9k/ar9003_calib.c
1357
REG_WRITE(ah, CL_TAB_ENTRY(cl_idx[i]),
drivers/net/wireless/ath/ath9k/ar9003_calib.c
1432
REG_WRITE(ah, AR_PHY_AGC_CONTROL(ah), agc_ctrl);
drivers/net/wireless/ath/ath9k/ar9003_calib.c
1480
REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
drivers/net/wireless/ath/ath9k/ar9003_calib.c
1482
REG_WRITE(ah, AR_PHY_RX_DELAY, AR_PHY_RX_DELAY_DELAY);
drivers/net/wireless/ath/ath9k/ar9003_calib.c
1483
REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
drivers/net/wireless/ath/ath9k/ar9003_calib.c
1488
REG_WRITE(ah, AR_PHY_AGC_CONTROL(ah),
drivers/net/wireless/ath/ath9k/ar9003_calib.c
1501
REG_WRITE(ah, AR_PHY_RX_DELAY, rx_delay);
drivers/net/wireless/ath/ath9k/ar9003_calib.c
1510
REG_WRITE(ah, AR_PHY_AGC_CONTROL(ah), agc_ctrl);
drivers/net/wireless/ath/ath9k/ar9003_calib.c
1561
REG_WRITE(ah, AR_PHY_AGC_CONTROL(ah),
drivers/net/wireless/ath/ath9k/ar9003_calib.c
1625
REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
drivers/net/wireless/ath/ath9k/ar9003_calib.c
1627
REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
drivers/net/wireless/ath/ath9k/ar9003_calib.c
353
REG_WRITE(ah, AR_PHY_AGC_CONTROL(ah),
drivers/net/wireless/ath/ath9k/ar9003_calib.c
390
REG_WRITE(ah, AR_PHY_AGC_CONTROL(ah),
drivers/net/wireless/ath/ath9k/ar9003_calib.c
407
REG_WRITE(ah, AR_PHY_65NM_CH0_BB3,
drivers/net/wireless/ath/ath9k/ar9003_calib.c
409
REG_WRITE(ah, AR_PHY_65NM_CH1_BB3,
drivers/net/wireless/ath/ath9k/ar9003_calib.c
411
REG_WRITE(ah, AR_PHY_65NM_CH2_BB3,
drivers/net/wireless/ath/ath9k/ar9003_calib.c
429
REG_WRITE(ah, AR_PHY_65NM_CH0_BB3,
drivers/net/wireless/ath/ath9k/ar9003_calib.c
431
REG_WRITE(ah, AR_PHY_65NM_CH1_BB3,
drivers/net/wireless/ath/ath9k/ar9003_calib.c
433
REG_WRITE(ah, AR_PHY_65NM_CH2_BB3,
drivers/net/wireless/ath/ath9k/ar9003_calib.c
451
REG_WRITE(ah, AR_PHY_65NM_CH0_BB3,
drivers/net/wireless/ath/ath9k/ar9003_calib.c
453
REG_WRITE(ah, AR_PHY_65NM_CH1_BB3,
drivers/net/wireless/ath/ath9k/ar9003_calib.c
455
REG_WRITE(ah, AR_PHY_65NM_CH2_BB3,
drivers/net/wireless/ath/ath9k/ar9003_calib.c
483
REG_WRITE(ah, AR_PHY_65NM_CH0_BB1, val);
drivers/net/wireless/ath/ath9k/ar9003_calib.c
504
REG_WRITE(ah, AR_PHY_65NM_CH1_BB1, val);
drivers/net/wireless/ath/ath9k/ar9003_calib.c
525
REG_WRITE(ah, AR_PHY_65NM_CH2_BB1, val);
drivers/net/wireless/ath/ath9k/ar9003_calib.c
53
REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
3763
REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
3774
REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
3791
REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
3815
REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS1, reg);
drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
3828
REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS2, reg);
drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
3835
REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS4, reg);
drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
3946
REG_WRITE(ah, pmu_reg, pmu_set);
drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
3964
REG_WRITE(ah, AR_PHY_PMU2(ah), reg_pmu_set);
drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
3987
REG_WRITE(ah, AR_PHY_PMU1(ah), reg_pmu_set);
drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
3993
REG_WRITE(ah, AR_PHY_PMU2(ah), reg_pmu_set);
drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
3999
REG_WRITE(ah, AR_PHY_PMU2(ah), reg_pmu_set);
drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
4005
REG_WRITE(ah, AR_PHY_PMU1(ah), reg_val);
drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
4008
REG_WRITE(ah, AR_PHY_PMU2(ah), 0x10200000);
drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
4012
REG_WRITE(ah, AR_RTC_REG_CONTROL1,
drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
4015
REG_WRITE(ah, AR_RTC_REG_CONTROL0, reg_val);
drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
4017
REG_WRITE(ah, AR_RTC_REG_CONTROL1,
drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
4042
REG_WRITE(ah, AR_RTC_SLEEP_CLK(ah), reg_val);
drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
4471
REG_WRITE(ah, AR_TPC, val);
drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
4479
REG_WRITE(ah, AR_PHY_TX_FORCED_GAIN, 0);
drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
4484
REG_WRITE(ah, AR_PHY_POWER_TX_RATE(0),
drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
4491
REG_WRITE(ah, AR_PHY_POWER_TX_RATE(1),
drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
4500
REG_WRITE(ah, AR_PHY_POWER_TX_RATE(2),
drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
4507
REG_WRITE(ah, AR_PHY_POWER_TX_RATE(3),
drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
4517
REG_WRITE(ah, AR_PHY_POWER_TX_RATE(8),
drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
4527
REG_WRITE(ah, AR_PHY_POWER_TX_RATE(4),
drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
4535
REG_WRITE(ah, AR_PHY_POWER_TX_RATE(5),
drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
4543
REG_WRITE(ah, AR_PHY_POWER_TX_RATE(9),
drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
4553
REG_WRITE(ah, AR_PHY_POWER_TX_RATE(10),
drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
4565
REG_WRITE(ah, AR_PHY_POWER_TX_RATE(6),
drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
4573
REG_WRITE(ah, AR_PHY_POWER_TX_RATE(7),
drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
4581
REG_WRITE(ah, AR_PHY_POWER_TX_RATE(11),
drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
5543
REG_WRITE(ah, AR_PHY_PWRTX_MAX,
drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
5548
REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
5551
REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
5555
REG_WRITE(ah, AR_PHY_PWRTX_MAX, 0);
drivers/net/wireless/ath/ath9k/ar9003_hw.c
1028
REG_WRITE(ah, 0x570c, val);
drivers/net/wireless/ath/ath9k/ar9003_hw.c
1036
REG_WRITE(ah, AR_WA(ah), ah->WARegVal);
drivers/net/wireless/ath/ath9k/ar9003_hw.c
1047
REG_WRITE(ah,
drivers/net/wireless/ath/ath9k/ar9003_mac.c
23
REG_WRITE(hw, AR_CR, 0);
drivers/net/wireless/ath/ath9k/ar9003_mac.c
235
REG_WRITE(ah, AR_ISR_S2, isr2);
drivers/net/wireless/ath/ath9k/ar9003_mac.c
270
REG_WRITE(ah, AR_ISR_S0, s0);
drivers/net/wireless/ath/ath9k/ar9003_mac.c
272
REG_WRITE(ah, AR_ISR_S1, s1);
drivers/net/wireless/ath/ath9k/ar9003_mac.c
297
REG_WRITE(ah, AR_ISR_S5, s5);
drivers/net/wireless/ath/ath9k/ar9003_mac.c
306
REG_WRITE(ah, AR_ISR, isr);
drivers/net/wireless/ath/ath9k/ar9003_mac.c
339
REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
drivers/net/wireless/ath/ath9k/ar9003_mac.c
340
REG_WRITE(ah, AR_RC, 0);
drivers/net/wireless/ath/ath9k/ar9003_mac.c
348
REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR(ah), sync_cause);
drivers/net/wireless/ath/ath9k/ar9003_mac.c
467
REG_WRITE(ah, AR_DATABUF_SIZE, buf_size & AR_DATABUF_SIZE_MASK);
drivers/net/wireless/ath/ath9k/ar9003_mac.c
475
REG_WRITE(ah, AR_HP_RXDP, rxdp);
drivers/net/wireless/ath/ath9k/ar9003_mac.c
477
REG_WRITE(ah, AR_LP_RXDP, rxdp);
drivers/net/wireless/ath/ath9k/ar9003_mac.c
604
REG_WRITE(ah, AR_Q_STATUS_RING_START, ah->ts_paddr_start);
drivers/net/wireless/ath/ath9k/ar9003_mac.c
605
REG_WRITE(ah, AR_Q_STATUS_RING_END, ah->ts_paddr_end);
drivers/net/wireless/ath/ath9k/ar9003_mci.c
1004
REG_WRITE(ah, AR_MCI_COMMAND2, regval);
drivers/net/wireless/ath/ath9k/ar9003_mci.c
1007
REG_WRITE(ah, AR_MCI_COMMAND2, regval);
drivers/net/wireless/ath/ath9k/ar9003_mci.c
1012
REG_WRITE(ah, AR_MCI_MSG_ATTRIBUTES_TABLE,
drivers/net/wireless/ath/ath9k/ar9003_mci.c
1047
REG_WRITE(ah, AR_BTCOEX_CTRL, 0);
drivers/net/wireless/ath/ath9k/ar9003_mci.c
1150
REG_WRITE(ah, AR_SELFGEN_MASK, 0x02);
drivers/net/wireless/ath/ath9k/ar9003_mci.c
1194
REG_WRITE(ah, AR_MCI_INTERRUPT_EN, 0);
drivers/net/wireless/ath/ath9k/ar9003_mci.c
1198
REG_WRITE(ah, AR_MCI_INTERRUPT_RAW,
drivers/net/wireless/ath/ath9k/ar9003_mci.c
1204
REG_WRITE(ah, (AR_MCI_TX_PAYLOAD0 + i * 4),
drivers/net/wireless/ath/ath9k/ar9003_mci.c
1208
REG_WRITE(ah, AR_MCI_COMMAND0,
drivers/net/wireless/ath/ath9k/ar9003_mci.c
1224
REG_WRITE(ah, AR_MCI_INTERRUPT_EN, saved_mci_int_en);
drivers/net/wireless/ath/ath9k/ar9003_mci.c
1284
REG_WRITE(ah, AR_BTCOEX_CTRL, 0x00);
drivers/net/wireless/ath/ath9k/ar9003_mci.c
1434
REG_WRITE(ah, AR_BTCOEX_CTRL2, (btcoex_ctrl2 | BIT(23)));
drivers/net/wireless/ath/ath9k/ar9003_mci.c
1442
REG_WRITE(ah, AR_DIAG_SW, (diag_sw | BIT(27) | BIT(19) | BIT(18)));
drivers/net/wireless/ath/ath9k/ar9003_mci.c
1446
REG_WRITE(ah, AR_BTCOEX_CTRL2, btcoex_ctrl2);
drivers/net/wireless/ath/ath9k/ar9003_mci.c
1447
REG_WRITE(ah, AR_DIAG_SW, diag_sw);
drivers/net/wireless/ath/ath9k/ar9003_mci.c
1489
REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
drivers/net/wireless/ath/ath9k/ar9003_mci.c
234
REG_WRITE(ah, AR_MCI_INTERRUPT_EN, 0);
drivers/net/wireless/ath/ath9k/ar9003_mci.c
235
REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
drivers/net/wireless/ath/ath9k/ar9003_mci.c
237
REG_WRITE(ah, AR_MCI_INTERRUPT_RAW,
drivers/net/wireless/ath/ath9k/ar9003_mci.c
272
REG_WRITE(ah, AR_MCI_BT_PRI0, 0xFFFFFFFF);
drivers/net/wireless/ath/ath9k/ar9003_mci.c
273
REG_WRITE(ah, AR_MCI_BT_PRI1, 0xFFFFFFFF);
drivers/net/wireless/ath/ath9k/ar9003_mci.c
274
REG_WRITE(ah, AR_MCI_BT_PRI2, 0xFFFFFFFF);
drivers/net/wireless/ath/ath9k/ar9003_mci.c
275
REG_WRITE(ah, AR_MCI_BT_PRI3, 0xFFFFFFFF);
drivers/net/wireless/ath/ath9k/ar9003_mci.c
276
REG_WRITE(ah, AR_MCI_BT_PRI, 0X000000FF);
drivers/net/wireless/ath/ath9k/ar9003_mci.c
284
REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
drivers/net/wireless/ath/ath9k/ar9003_mci.c
286
REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, AR_MCI_INTERRUPT_BT_PRI);
drivers/net/wireless/ath/ath9k/ar9003_mci.c
312
REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
drivers/net/wireless/ath/ath9k/ar9003_mci.c
314
REG_WRITE(ah, AR_MCI_INTERRUPT_RAW,
drivers/net/wireless/ath/ath9k/ar9003_mci.c
318
REG_WRITE(ah, AR_MCI_INTERRUPT_EN, saved_mci_int_en);
drivers/net/wireless/ath/ath9k/ar9003_mci.c
336
REG_WRITE(ah, AR_MCI_INTERRUPT_EN, 0);
drivers/net/wireless/ath/ath9k/ar9003_mci.c
337
REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
drivers/net/wireless/ath/ath9k/ar9003_mci.c
342
REG_WRITE(ah, AR_MCI_INTERRUPT_EN, AR_MCI_INTERRUPT_DEFAULT);
drivers/net/wireless/ath/ath9k/ar9003_mci.c
343
REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN,
drivers/net/wireless/ath/ath9k/ar9003_mci.c
389
REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW, rx_msg_intr);
drivers/net/wireless/ath/ath9k/ar9003_mci.c
390
REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, raw_intr);
drivers/net/wireless/ath/ath9k/ar9003_mci.c
469
REG_WRITE(ah, AR_OBS(ah), 0x4b);
drivers/net/wireless/ath/ath9k/ar9003_mci.c
48
REG_WRITE(ah, address, bit_position);
drivers/net/wireless/ath/ath9k/ar9003_mci.c
58
REG_WRITE(ah, AR_MCI_INTERRUPT_RAW,
drivers/net/wireless/ath/ath9k/ar9003_mci.c
61
REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, AR_MCI_INTERRUPT_RX_MSG);
drivers/net/wireless/ath/ath9k/ar9003_mci.c
752
REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
drivers/net/wireless/ath/ath9k/ar9003_mci.c
790
REG_WRITE(ah, AR_MCI_MSG_ATTRIBUTES_TABLE, 0xffff0000);
drivers/net/wireless/ath/ath9k/ar9003_mci.c
791
REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS0, 0xffffffff);
drivers/net/wireless/ath/ath9k/ar9003_mci.c
792
REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS1, 0xffffffff);
drivers/net/wireless/ath/ath9k/ar9003_mci.c
793
REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS2, 0xffffffff);
drivers/net/wireless/ath/ath9k/ar9003_mci.c
794
REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS3, 0xffffffff);
drivers/net/wireless/ath/ath9k/ar9003_mci.c
879
REG_WRITE(ah, AR_BTCOEX_CTRL, regval);
drivers/net/wireless/ath/ath9k/ar9003_mci.c
898
REG_WRITE(ah, AR_BTCOEX_CTRL, regval);
drivers/net/wireless/ath/ath9k/ar9003_mci.c
915
REG_WRITE(ah, AR_BTCOEX_CTRL, regval);
drivers/net/wireless/ath/ath9k/ar9003_mci.c
934
REG_WRITE(ah, AR_MCI_GPM_0, mci->gpm_addr);
drivers/net/wireless/ath/ath9k/ar9003_mci.c
935
REG_WRITE(ah, AR_MCI_GPM_1, mci->gpm_len);
drivers/net/wireless/ath/ath9k/ar9003_mci.c
936
REG_WRITE(ah, AR_MCI_SCHD_TABLE_0, mci->sched_addr);
drivers/net/wireless/ath/ath9k/ar9003_mci.c
978
REG_WRITE(ah, AR_BTCOEX_MAX_TXPWR(i), 0x7f7f7f7f);
drivers/net/wireless/ath/ath9k/ar9003_mci.c
988
REG_WRITE(ah, AR_MCI_COMMAND2, regval);
drivers/net/wireless/ath/ath9k/ar9003_mci.c
993
REG_WRITE(ah, AR_MCI_COMMAND2, regval);
drivers/net/wireless/ath/ath9k/ar9003_paprd.c
769
REG_WRITE(ah, reg, paprd_table_val[i]);
drivers/net/wireless/ath/ath9k/ar9003_phy.c
1044
REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
drivers/net/wireless/ath/ath9k/ar9003_phy.c
1059
REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
drivers/net/wireless/ath/ath9k/ar9003_phy.c
1468
REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
drivers/net/wireless/ath/ath9k/ar9003_phy.c
1469
REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
drivers/net/wireless/ath/ath9k/ar9003_phy.c
1549
REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
drivers/net/wireless/ath/ath9k/ar9003_phy.c
1583
REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
drivers/net/wireless/ath/ath9k/ar9003_phy.c
1595
REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
drivers/net/wireless/ath/ath9k/ar9003_phy.c
1606
REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
drivers/net/wireless/ath/ath9k/ar9003_phy.c
1622
REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
drivers/net/wireless/ath/ath9k/ar9003_phy.c
1657
REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
drivers/net/wireless/ath/ath9k/ar9003_phy.c
1797
REG_WRITE(ah, AR_CR, AR_CR_RXD);
drivers/net/wireless/ath/ath9k/ar9003_phy.c
1798
REG_WRITE(ah, AR_DLCL_IFS(qnum), 0);
drivers/net/wireless/ath/ath9k/ar9003_phy.c
1799
REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 20); /* 50 OK */
drivers/net/wireless/ath/ath9k/ar9003_phy.c
1800
REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 20);
drivers/net/wireless/ath/ath9k/ar9003_phy.c
1801
REG_WRITE(ah, AR_TIME_OUT, 0x00000400);
drivers/net/wireless/ath/ath9k/ar9003_phy.c
1802
REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff);
drivers/net/wireless/ath/ath9k/ar9003_phy.c
2007
REG_WRITE(ah, AR_PHY_RADAR_0, val);
drivers/net/wireless/ath/ath9k/ar9003_phy.c
2012
REG_WRITE(ah, AR_PHY_RADAR_0, val);
drivers/net/wireless/ath/ath9k/ar9003_phy.c
2043
REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
drivers/net/wireless/ath/ath9k/ar9003_phy.c
2049
REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
drivers/net/wireless/ath/ath9k/ar9003_phy.c
206
REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
drivers/net/wireless/ath/ath9k/ar9003_phy.c
2060
REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
drivers/net/wireless/ath/ath9k/ar9003_phy.c
2085
REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
drivers/net/wireless/ath/ath9k/ar9003_phy.c
2106
REG_WRITE(ah, AR_PHY_WATCHDOG_STATUS,
drivers/net/wireless/ath/ath9k/ar9003_phy.c
215
REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
drivers/net/wireless/ath/ath9k/ar9003_phy.c
2165
REG_WRITE(ah, AR_PHY_RESTART, val);
drivers/net/wireless/ath/ath9k/ar9003_phy.c
221
REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
drivers/net/wireless/ath/ath9k/ar9003_phy.c
639
REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode);
drivers/net/wireless/ath/ath9k/ar9003_phy.c
645
REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
drivers/net/wireless/ath/ath9k/ar9003_phy.c
647
REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
drivers/net/wireless/ath/ath9k/ar9003_phy.c
663
REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
drivers/net/wireless/ath/ath9k/ar9003_phy.c
673
REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx);
drivers/net/wireless/ath/ath9k/ar9003_phy.c
674
REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx);
drivers/net/wireless/ath/ath9k/ar9003_phy.c
679
REG_WRITE(ah, AR_SELFGEN_MASK, tx);
drivers/net/wireless/ath/ath9k/ar9003_phy.c
707
REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
drivers/net/wireless/ath/ath9k/ar9003_phy.c
710
REG_WRITE(ah, AR_GLB_SWREG_DISCONT_MODE,
drivers/net/wireless/ath/ath9k/ar9003_phy.c
729
REG_WRITE(ah, AR_RTC_DERIVED_CLK(ah), 0x17c << 1);
drivers/net/wireless/ath/ath9k/ar9003_phy.c
730
REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
drivers/net/wireless/ath/ath9k/ar9003_phy.c
731
REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
drivers/net/wireless/ath/ath9k/ar9003_phy.c
733
REG_WRITE(ah, AR_RTC_DERIVED_CLK(ah), 0x261 << 1);
drivers/net/wireless/ath/ath9k/ar9003_phy.c
734
REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
drivers/net/wireless/ath/ath9k/ar9003_phy.c
735
REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
drivers/net/wireless/ath/ath9k/ar9003_phy.c
763
REG_WRITE(ah, reg, val);
drivers/net/wireless/ath/ath9k/ar9003_phy.c
987
REG_WRITE(ah, AR_PHY_MODE, rfMode);
drivers/net/wireless/ath/ath9k/ar9003_phy.c
992
REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
drivers/net/wireless/ath/ath9k/ar9003_rtt.c
150
REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val);
drivers/net/wireless/ath/ath9k/ar9003_rtt.c
154
REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val);
drivers/net/wireless/ath/ath9k/ar9003_rtt.c
40
REG_WRITE(ah, AR_PHY_RTT_CTRL, 1);
drivers/net/wireless/ath/ath9k/ar9003_rtt.c
45
REG_WRITE(ah, AR_PHY_RTT_CTRL, 0);
drivers/net/wireless/ath/ath9k/ar9003_rtt.c
78
REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_1_B(chain), val);
drivers/net/wireless/ath/ath9k/ar9003_rtt.c
83
REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val);
drivers/net/wireless/ath/ath9k/ar9003_rtt.c
87
REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val);
drivers/net/wireless/ath/ath9k/ar9003_rtt.c
96
REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val);
drivers/net/wireless/ath/ath9k/ar9003_wow.c
111
REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + (12 * 4)), 0);
drivers/net/wireless/ath/ath9k/ar9003_wow.c
118
REG_WRITE(ah, (wow_ka_data_word0 + i*4), data_word[i]);
drivers/net/wireless/ath/ath9k/ar9003_wow.c
139
REG_WRITE(ah, (AR_WOW_TB_PATTERN(pattern_count) + i),
drivers/net/wireless/ath/ath9k/ar9003_wow.c
146
REG_WRITE(ah, (AR_WOW_TB_MASK(pattern_count) + i), mask_val);
drivers/net/wireless/ath/ath9k/ar9003_wow.c
235
REG_WRITE(ah, AR_WOW_PATTERN,
drivers/net/wireless/ath/ath9k/ar9003_wow.c
237
REG_WRITE(ah, AR_MAC_PCU_WOW4,
drivers/net/wireless/ath/ath9k/ar9003_wow.c
243
REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
drivers/net/wireless/ath/ath9k/ar9003_wow.c
286
REG_WRITE(ah, AR_WA(ah), wa_reg);
drivers/net/wireless/ath/ath9k/ar9003_wow.c
339
REG_WRITE(ah, AR_WOW_BCN_TIMO, AR_WOW_BEACON_TIMO);
drivers/net/wireless/ath/ath9k/ar9003_wow.c
341
REG_WRITE(ah, AR_WOW_BCN_TIMO, AR_WOW_BEACON_TIMO_MAX);
drivers/net/wireless/ath/ath9k/ar9003_wow.c
347
REG_WRITE(ah, AR_WOW_KEEP_ALIVE_TIMO, AR_WOW_KEEP_ALIVE_NEVER);
drivers/net/wireless/ath/ath9k/ar9003_wow.c
349
REG_WRITE(ah, AR_WOW_KEEP_ALIVE_TIMO, KAL_TIMEOUT * 32);
drivers/net/wireless/ath/ath9k/ar9003_wow.c
354
REG_WRITE(ah, AR_WOW_KEEP_ALIVE_DELAY, KAL_DELAY * 1000);
drivers/net/wireless/ath/ath9k/ar9003_wow.c
376
REG_WRITE(ah, AR_WOW_KEEP_ALIVE, keep_alive);
drivers/net/wireless/ath/ath9k/ar9003_wow.c
405
REG_WRITE(ah, AR_WOW_PATTERN, magic_pattern);
drivers/net/wireless/ath/ath9k/ar9003_wow.c
411
REG_WRITE(ah, AR_WOW_PATTERN_MATCH_LT_256B,
drivers/net/wireless/ath/ath9k/ar9003_wow.c
433
REG_WRITE(ah, AR_PCIE_PM_CTRL(ah), host_pm_ctrl);
drivers/net/wireless/ath/ath9k/ar9003_wow.c
44
REG_WRITE(ah, AR_CR, AR_CR_RXD);
drivers/net/wireless/ath/ath9k/ar9003_wow.c
446
REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
drivers/net/wireless/ath/ath9k/ar9003_wow.c
62
REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
drivers/net/wireless/ath/ath9k/ar9003_wow.c
64
REG_WRITE(ah, AR_RTC_FORCE_WAKE(ah), AR_RTC_FORCE_WAKE_ON_INT);
drivers/net/wireless/ath/ath9k/ar9003_wow.c
92
REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + i * 4), ctl[i]);
drivers/net/wireless/ath/ath9k/btcoex.c
323
REG_WRITE(ah, AR_BT_COEX_MODE, btcoex->bt_coex_mode);
drivers/net/wireless/ath/ath9k/btcoex.c
324
REG_WRITE(ah, AR_BT_COEX_MODE2, btcoex->bt_coex_mode2);
drivers/net/wireless/ath/ath9k/btcoex.c
327
REG_WRITE(ah, AR_BT_COEX_MODE3, btcoex->bt_coex_mode3);
drivers/net/wireless/ath/ath9k/btcoex.c
330
REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS0, btcoex->wlan_weight[0]);
drivers/net/wireless/ath/ath9k/btcoex.c
331
REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS1, btcoex->wlan_weight[1]);
drivers/net/wireless/ath/ath9k/btcoex.c
333
REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS(i),
drivers/net/wireless/ath/ath9k/btcoex.c
336
REG_WRITE(ah, AR_BT_COEX_WEIGHT, btcoex->bt_coex_weights);
drivers/net/wireless/ath/ath9k/btcoex.c
341
REG_WRITE(ah, 0x50040, val);
drivers/net/wireless/ath/ath9k/btcoex.c
358
REG_WRITE(ah, AR_MCI_COEX_WL_WEIGHTS(i),
drivers/net/wireless/ath/ath9k/btcoex.c
373
REG_WRITE(ah, AR_MCI_COEX_WL_WEIGHTS(i),
drivers/net/wireless/ath/ath9k/btcoex.c
425
REG_WRITE(ah, AR_BT_COEX_MODE, AR_BT_QUIET | AR_BT_MODE);
drivers/net/wireless/ath/ath9k/btcoex.c
426
REG_WRITE(ah, AR_BT_COEX_MODE2, 0);
drivers/net/wireless/ath/ath9k/btcoex.c
429
REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS0, 0);
drivers/net/wireless/ath/ath9k/btcoex.c
430
REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS1, 0);
drivers/net/wireless/ath/ath9k/btcoex.c
432
REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS(i), 0);
drivers/net/wireless/ath/ath9k/btcoex.c
434
REG_WRITE(ah, AR_BT_COEX_WEIGHT, 0);
drivers/net/wireless/ath/ath9k/eeprom.c
21
REG_WRITE(ah, reg, val);
drivers/net/wireless/ath/ath9k/eeprom_4k.c
346
REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset,
drivers/net/wireless/ath/ath9k/eeprom_4k.c
361
REG_WRITE(ah, regOffset, reg32);
drivers/net/wireless/ath/ath9k/eeprom_4k.c
620
REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
drivers/net/wireless/ath/ath9k/eeprom_4k.c
625
REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
drivers/net/wireless/ath/ath9k/eeprom_4k.c
632
REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
drivers/net/wireless/ath/ath9k/eeprom_4k.c
637
REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
drivers/net/wireless/ath/ath9k/eeprom_4k.c
644
REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
drivers/net/wireless/ath/ath9k/eeprom_4k.c
649
REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
drivers/net/wireless/ath/ath9k/eeprom_4k.c
657
REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
drivers/net/wireless/ath/ath9k/eeprom_4k.c
666
REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
drivers/net/wireless/ath/ath9k/eeprom_4k.c
675
REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
drivers/net/wireless/ath/ath9k/eeprom_4k.c
689
REG_WRITE(ah, AR_PHY_POWER_TX_RATE_MAX,
drivers/net/wireless/ath/ath9k/eeprom_4k.c
693
REG_WRITE(ah, AR_PHY_POWER_TX_RATE_MAX, MAX_RATE_POWER);
drivers/net/wireless/ath/ath9k/eeprom_4k.c
772
REG_WRITE(ah, AR_PHY_SWITCH_COM, le32_to_cpu(pModal->antCtrlCommon));
drivers/net/wireless/ath/ath9k/eeprom_4k.c
797
REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regVal);
drivers/net/wireless/ath/ath9k/eeprom_4k.c
804
REG_WRITE(ah, AR_PHY_CCK_DETECT, regVal);
drivers/net/wireless/ath/ath9k/eeprom_4k.c
822
REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regVal);
drivers/net/wireless/ath/ath9k/eeprom_9287.c
323
REG_WRITE(ah, 0xa270, tmpVal);
drivers/net/wireless/ath/ath9k/eeprom_9287.c
330
REG_WRITE(ah, 0xb270, tmpVal);
drivers/net/wireless/ath/ath9k/eeprom_9287.c
339
REG_WRITE(ah, 0xa398, tmpVal);
drivers/net/wireless/ath/ath9k/eeprom_9287.c
349
REG_WRITE(ah, 0xb398, tmpVal);
drivers/net/wireless/ath/ath9k/eeprom_9287.c
454
REG_WRITE(ah,
drivers/net/wireless/ath/ath9k/eeprom_9287.c
482
REG_WRITE(ah, regOffset, reg32);
drivers/net/wireless/ath/ath9k/eeprom_9287.c
749
REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
drivers/net/wireless/ath/ath9k/eeprom_9287.c
755
REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
drivers/net/wireless/ath/ath9k/eeprom_9287.c
763
REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
drivers/net/wireless/ath/ath9k/eeprom_9287.c
768
REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
drivers/net/wireless/ath/ath9k/eeprom_9287.c
776
REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
drivers/net/wireless/ath/ath9k/eeprom_9287.c
782
REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
drivers/net/wireless/ath/ath9k/eeprom_9287.c
791
REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
drivers/net/wireless/ath/ath9k/eeprom_9287.c
797
REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
drivers/net/wireless/ath/ath9k/eeprom_9287.c
803
REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
drivers/net/wireless/ath/ath9k/eeprom_9287.c
813
REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
drivers/net/wireless/ath/ath9k/eeprom_9287.c
825
REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
drivers/net/wireless/ath/ath9k/eeprom_9287.c
839
REG_WRITE(ah, AR_PHY_POWER_TX_RATE_MAX,
drivers/net/wireless/ath/ath9k/eeprom_9287.c
843
REG_WRITE(ah, AR_PHY_POWER_TX_RATE_MAX, MAX_RATE_POWER);
drivers/net/wireless/ath/ath9k/eeprom_9287.c
860
REG_WRITE(ah, AR_PHY_SWITCH_COM, le32_to_cpu(pModal->antCtrlCommon));
drivers/net/wireless/ath/ath9k/eeprom_9287.c
865
REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
drivers/net/wireless/ath/ath9k/eeprom_9287.c
868
REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
drivers/net/wireless/ath/ath9k/eeprom_9287.c
904
REG_WRITE(ah, AR_PHY_RF_CTL4,
drivers/net/wireless/ath/ath9k/eeprom_def.c
1194
REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
drivers/net/wireless/ath/ath9k/eeprom_def.c
1199
REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
drivers/net/wireless/ath/ath9k/eeprom_def.c
1208
REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
drivers/net/wireless/ath/ath9k/eeprom_def.c
1213
REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
drivers/net/wireless/ath/ath9k/eeprom_def.c
1219
REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
drivers/net/wireless/ath/ath9k/eeprom_def.c
1224
REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
drivers/net/wireless/ath/ath9k/eeprom_def.c
1232
REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
drivers/net/wireless/ath/ath9k/eeprom_def.c
1237
REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
drivers/net/wireless/ath/ath9k/eeprom_def.c
1244
REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
drivers/net/wireless/ath/ath9k/eeprom_def.c
1253
REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
drivers/net/wireless/ath/ath9k/eeprom_def.c
1263
REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
drivers/net/wireless/ath/ath9k/eeprom_def.c
1269
REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
drivers/net/wireless/ath/ath9k/eeprom_def.c
1277
REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
drivers/net/wireless/ath/ath9k/eeprom_def.c
1288
REG_WRITE(ah, AR_PHY_POWER_TX_RATE_MAX,
drivers/net/wireless/ath/ath9k/eeprom_def.c
1292
REG_WRITE(ah, AR_PHY_POWER_TX_RATE_MAX, MAX_RATE_POWER);
drivers/net/wireless/ath/ath9k/eeprom_def.c
479
REG_WRITE(ah, AR_PHY_SWITCH_COM, antCtrlCommon & 0xffff);
drivers/net/wireless/ath/ath9k/eeprom_def.c
492
REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
drivers/net/wireless/ath/ath9k/eeprom_def.c
495
REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
drivers/net/wireless/ath/ath9k/eeprom_def.c
567
REG_WRITE(ah, AR_PHY_RF_CTL4,
drivers/net/wireless/ath/ath9k/eeprom_def.c
873
REG_WRITE(ah,
drivers/net/wireless/ath/ath9k/eeprom_def.c
880
REG_WRITE(ah,
drivers/net/wireless/ath/ath9k/eeprom_def.c
896
REG_WRITE(ah, regOffset, reg32);
drivers/net/wireless/ath/ath9k/htc_drv_init.c
501
REG_WRITE(ah, reg_offset, val);
drivers/net/wireless/ath/ath9k/hw.c
1000
REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK(ah), 0);
drivers/net/wireless/ath/ath9k/hw.c
1001
REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE(ah), 0);
drivers/net/wireless/ath/ath9k/hw.c
1002
REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK(ah), 0);
drivers/net/wireless/ath/ath9k/hw.c
1010
REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val);
drivers/net/wireless/ath/ath9k/hw.c
1017
REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
drivers/net/wireless/ath/ath9k/hw.c
1148
REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs));
drivers/net/wireless/ath/ath9k/hw.c
118
REG_WRITE(ah, INI_RA(array, r, 0),
drivers/net/wireless/ath/ath9k/hw.c
1231
REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
drivers/net/wireless/ath/ath9k/hw.c
1259
REG_WRITE(ah, AR_PCU_TXBUF_CTRL, txbuf_size);
drivers/net/wireless/ath/ath9k/hw.c
1345
REG_WRITE(ah, AR_RTC_RESET(ah), 1);
drivers/net/wireless/ath/ath9k/hw.c
1365
REG_WRITE(ah, AR_WA(ah), ah->WARegVal);
drivers/net/wireless/ath/ath9k/hw.c
1369
REG_WRITE(ah, AR_RTC_FORCE_WAKE(ah), AR_RTC_FORCE_WAKE_EN |
drivers/net/wireless/ath/ath9k/hw.c
1385
REG_WRITE(ah, AR_INTR_SYNC_ENABLE(ah), 0);
drivers/net/wireless/ath/ath9k/hw.c
1390
REG_WRITE(ah, AR_RC, val);
drivers/net/wireless/ath/ath9k/hw.c
1393
REG_WRITE(ah, AR_RC, AR_RC_AHB);
drivers/net/wireless/ath/ath9k/hw.c
1418
REG_WRITE(ah, AR_RTC_RC(ah), rst_flags);
drivers/net/wireless/ath/ath9k/hw.c
1429
REG_WRITE(ah, AR_RTC_RC(ah), 0);
drivers/net/wireless/ath/ath9k/hw.c
1436
REG_WRITE(ah, AR_RC, 0);
drivers/net/wireless/ath/ath9k/hw.c
1449
REG_WRITE(ah, AR_WA(ah), ah->WARegVal);
drivers/net/wireless/ath/ath9k/hw.c
1453
REG_WRITE(ah, AR_RTC_FORCE_WAKE(ah), AR_RTC_FORCE_WAKE_EN |
drivers/net/wireless/ath/ath9k/hw.c
1457
REG_WRITE(ah, AR_RC, AR_RC_AHB);
drivers/net/wireless/ath/ath9k/hw.c
1459
REG_WRITE(ah, AR_RTC_RESET(ah), 0);
drivers/net/wireless/ath/ath9k/hw.c
1466
REG_WRITE(ah, AR_RC, 0);
drivers/net/wireless/ath/ath9k/hw.c
1468
REG_WRITE(ah, AR_RTC_RESET(ah), 1);
drivers/net/wireless/ath/ath9k/hw.c
1487
REG_WRITE(ah, AR_WA(ah), ah->WARegVal);
drivers/net/wireless/ath/ath9k/hw.c
1491
REG_WRITE(ah, AR_RTC_FORCE_WAKE(ah),
drivers/net/wireless/ath/ath9k/hw.c
1636
REG_WRITE(ah, AR_NAV, 0);
drivers/net/wireless/ath/ath9k/hw.c
1720
REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
drivers/net/wireless/ath/ath9k/hw.c
1722
REG_WRITE(ah, AR_ISR, ~0);
drivers/net/wireless/ath/ath9k/hw.c
1723
REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
drivers/net/wireless/ath/ath9k/hw.c
1737
REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
drivers/net/wireless/ath/ath9k/hw.c
1761
REG_WRITE(ah, AR_CFG, mask);
drivers/net/wireless/ath/ath9k/hw.c
1769
REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
drivers/net/wireless/ath/ath9k/hw.c
1771
REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
drivers/net/wireless/ath/ath9k/hw.c
1779
REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
drivers/net/wireless/ath/ath9k/hw.c
1925
REG_WRITE(ah,
drivers/net/wireless/ath/ath9k/hw.c
1939
REG_WRITE(ah,
drivers/net/wireless/ath/ath9k/hw.c
2012
REG_WRITE(ah, AR_OBS(ah), 8);
drivers/net/wireless/ath/ath9k/hw.c
2041
REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
drivers/net/wireless/ath/ath9k/hw.c
2098
REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
drivers/net/wireless/ath/ath9k/hw.c
2112
REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
drivers/net/wireless/ath/ath9k/hw.c
2122
REG_WRITE(ah, AR_WA(ah), ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
drivers/net/wireless/ath/ath9k/hw.c
2138
REG_WRITE(ah, AR_RTC_FORCE_WAKE(ah),
drivers/net/wireless/ath/ath9k/hw.c
2166
REG_WRITE(ah, AR_WA(ah), ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
drivers/net/wireless/ath/ath9k/hw.c
2176
REG_WRITE(ah, AR_WA(ah), ah->WARegVal);
drivers/net/wireless/ath/ath9k/hw.c
2289
REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
drivers/net/wireless/ath/ath9k/hw.c
2290
REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
drivers/net/wireless/ath/ath9k/hw.c
2292
REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
drivers/net/wireless/ath/ath9k/hw.c
2303
REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
drivers/net/wireless/ath/ath9k/hw.c
2304
REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
drivers/net/wireless/ath/ath9k/hw.c
2305
REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
drivers/net/wireless/ath/ath9k/hw.c
2322
REG_WRITE(ah, AR_NEXT_TBTT_TIMER, bs->bs_nexttbtt);
drivers/net/wireless/ath/ath9k/hw.c
2323
REG_WRITE(ah, AR_BEACON_PERIOD, bs->bs_intval);
drivers/net/wireless/ath/ath9k/hw.c
2324
REG_WRITE(ah, AR_DMA_BEACON_PERIOD, bs->bs_intval);
drivers/net/wireless/ath/ath9k/hw.c
2352
REG_WRITE(ah, AR_NEXT_DTIM, bs->bs_nextdtim - SLEEP_SLOP);
drivers/net/wireless/ath/ath9k/hw.c
2353
REG_WRITE(ah, AR_NEXT_TIM, nextTbtt - SLEEP_SLOP);
drivers/net/wireless/ath/ath9k/hw.c
2355
REG_WRITE(ah, AR_SLEEP1,
drivers/net/wireless/ath/ath9k/hw.c
2364
REG_WRITE(ah, AR_SLEEP2,
drivers/net/wireless/ath/ath9k/hw.c
2367
REG_WRITE(ah, AR_TIM_PERIOD, beaconintval);
drivers/net/wireless/ath/ath9k/hw.c
2368
REG_WRITE(ah, AR_DTIM_PERIOD, dtimperiod);
drivers/net/wireless/ath/ath9k/hw.c
2377
REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
drivers/net/wireless/ath/ath9k/hw.c
2713
REG_WRITE(ah, addr, tmp);
drivers/net/wireless/ath/ath9k/hw.c
2859
REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
drivers/net/wireless/ath/ath9k/hw.c
2887
REG_WRITE(ah, AR_RX_FILTER, bits);
drivers/net/wireless/ath/ath9k/hw.c
2894
REG_WRITE(ah, AR_PHY_ERR, phybits);
drivers/net/wireless/ath/ath9k/hw.c
2991
REG_WRITE(ah, AR_MCAST_FIL0, filter0);
drivers/net/wireless/ath/ath9k/hw.c
2992
REG_WRITE(ah, AR_MCAST_FIL1, filter1);
drivers/net/wireless/ath/ath9k/hw.c
3000
REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
drivers/net/wireless/ath/ath9k/hw.c
3001
REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
drivers/net/wireless/ath/ath9k/hw.c
3030
REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
drivers/net/wireless/ath/ath9k/hw.c
3031
REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
drivers/net/wireless/ath/ath9k/hw.c
3042
REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
drivers/net/wireless/ath/ath9k/hw.c
3064
REG_WRITE(ah, AR_2040_MODE, macmode);
drivers/net/wireless/ath/ath9k/hw.c
3164
REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
drivers/net/wireless/ath/ath9k/hw.c
3166
REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
drivers/net/wireless/ath/ath9k/hw.c
331
REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
drivers/net/wireless/ath/ath9k/hw.c
332
REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
drivers/net/wireless/ath/ath9k/hw.c
333
REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
drivers/net/wireless/ath/ath9k/hw.c
334
REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
drivers/net/wireless/ath/ath9k/hw.c
335
REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
drivers/net/wireless/ath/ath9k/hw.c
336
REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
drivers/net/wireless/ath/ath9k/hw.c
337
REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
drivers/net/wireless/ath/ath9k/hw.c
338
REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
drivers/net/wireless/ath/ath9k/hw.c
339
REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
drivers/net/wireless/ath/ath9k/hw.c
341
REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
drivers/net/wireless/ath/ath9k/hw.c
368
REG_WRITE(ah, addr, wrData);
drivers/net/wireless/ath/ath9k/hw.c
379
REG_WRITE(ah, addr, wrData);
drivers/net/wireless/ath/ath9k/hw.c
388
REG_WRITE(ah, regAddr[i], regHold[i]);
drivers/net/wireless/ath/ath9k/hw.c
622
REG_WRITE(ah, AR_WA(ah), ah->WARegVal);
drivers/net/wireless/ath/ath9k/hw.c
719
REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
drivers/net/wireless/ath/ath9k/hw.c
720
REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
drivers/net/wireless/ath/ath9k/hw.c
722
REG_WRITE(ah, AR_QOS_NO_ACK,
drivers/net/wireless/ath/ath9k/hw.c
727
REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
drivers/net/wireless/ath/ath9k/hw.c
728
REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
drivers/net/wireless/ath/ath9k/hw.c
729
REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
drivers/net/wireless/ath/ath9k/hw.c
730
REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
drivers/net/wireless/ath/ath9k/hw.c
731
REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
drivers/net/wireless/ath/ath9k/hw.c
812
REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2);
drivers/net/wireless/ath/ath9k/hw.c
818
REG_WRITE(ah, AR_RTC_PLL_CONTROL(ah),
drivers/net/wireless/ath/ath9k/hw.c
823
REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2);
drivers/net/wireless/ath/ath9k/hw.c
836
REG_WRITE(ah, AR_RTC_PLL_CONTROL(ah),
drivers/net/wireless/ath/ath9k/hw.c
872
REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
drivers/net/wireless/ath/ath9k/hw.c
875
REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
drivers/net/wireless/ath/ath9k/hw.c
901
REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
drivers/net/wireless/ath/ath9k/hw.c
904
REG_WRITE(ah, AR_PHY_PLL_MODE,
drivers/net/wireless/ath/ath9k/hw.c
907
REG_WRITE(ah, AR_PHY_PLL_MODE,
drivers/net/wireless/ath/ath9k/hw.c
915
REG_WRITE(ah, AR_RTC_PLL_CONTROL(ah), pll);
drivers/net/wireless/ath/ath9k/hw.c
924
REG_WRITE(ah, 0x50040, 0x304);
drivers/net/wireless/ath/ath9k/hw.c
929
REG_WRITE(ah, AR_RTC_SLEEP_CLK(ah), AR_RTC_FORCE_DERIVED_CLK);
drivers/net/wireless/ath/ath9k/hw.c
976
REG_WRITE(ah, AR_IMR, imr_reg);
drivers/net/wireless/ath/ath9k/hw.c
978
REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
drivers/net/wireless/ath/ath9k/hw.c
984
REG_WRITE(ah, AR_INTCFG, msi_cfg);
drivers/net/wireless/ath/ath9k/hw.c
991
REG_WRITE(ah, AR_INTR_SYNC_CAUSE(ah), 0xFFFFFFFF);
drivers/net/wireless/ath/ath9k/hw.c
992
REG_WRITE(ah, AR_INTR_SYNC_ENABLE(ah), sync_default);
drivers/net/wireless/ath/ath9k/hw.c
993
REG_WRITE(ah, AR_INTR_SYNC_MASK(ah), 0);
drivers/net/wireless/ath/ath9k/hw.c
999
REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE(ah), 0);
drivers/net/wireless/ath/ath9k/mac.c
1015
REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
drivers/net/wireless/ath/ath9k/mac.c
1045
REG_WRITE(ah, AR_D_TXBLK_BASE, filter);
drivers/net/wireless/ath/ath9k/mac.c
123
REG_WRITE(ah, AR_TXCFG,
drivers/net/wireless/ath/ath9k/mac.c
146
REG_WRITE(ah, AR_Q_TXD, AR_Q_TXD_M);
drivers/net/wireless/ath/ath9k/mac.c
166
REG_WRITE(ah, AR_Q_TXD, 0);
drivers/net/wireless/ath/ath9k/mac.c
177
REG_WRITE(ah, AR_Q_TXD, 1 << q);
drivers/net/wireless/ath/ath9k/mac.c
187
REG_WRITE(ah, AR_Q_TXD, 0);
drivers/net/wireless/ath/ath9k/mac.c
32
REG_WRITE(ah, AR_IMR_S0,
drivers/net/wireless/ath/ath9k/mac.c
35
REG_WRITE(ah, AR_IMR_S1,
drivers/net/wireless/ath/ath9k/mac.c
390
REG_WRITE(ah, AR_DLCL_IFS(q),
drivers/net/wireless/ath/ath9k/mac.c
395
REG_WRITE(ah, AR_DRETRY_LIMIT(q),
drivers/net/wireless/ath/ath9k/mac.c
400
REG_WRITE(ah, AR_QMISC(q), AR_Q_MISC_DCU_EARLY_TERM_REQ);
drivers/net/wireless/ath/ath9k/mac.c
403
REG_WRITE(ah, AR_DMISC(q),
drivers/net/wireless/ath/ath9k/mac.c
406
REG_WRITE(ah, AR_DMISC(q),
drivers/net/wireless/ath/ath9k/mac.c
41
REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
drivers/net/wireless/ath/ath9k/mac.c
410
REG_WRITE(ah, AR_QCBRCFG(q),
drivers/net/wireless/ath/ath9k/mac.c
418
REG_WRITE(ah, AR_QRDYTIMECFG(q),
drivers/net/wireless/ath/ath9k/mac.c
423
REG_WRITE(ah, AR_DCHNTIME(q),
drivers/net/wireless/ath/ath9k/mac.c
463
REG_WRITE(ah, AR_DLCL_IFS(q), SM(0, AR_D_LCL_IFS_CWMIN)
drivers/net/wireless/ath/ath9k/mac.c
478
REG_WRITE(ah, AR_QRDYTIMECFG(q),
drivers/net/wireless/ath/ath9k/mac.c
505
REG_WRITE(ah, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN);
drivers/net/wireless/ath/ath9k/mac.c
54
REG_WRITE(ah, AR_QTXDP(q), txdp);
drivers/net/wireless/ath/ath9k/mac.c
61
REG_WRITE(ah, AR_Q_TXE, 1 << q);
drivers/net/wireless/ath/ath9k/mac.c
671
REG_WRITE(ah, AR_RXDP, rxdp);
drivers/net/wireless/ath/ath9k/mac.c
701
REG_WRITE(ah, AR_MACMISC,
drivers/net/wireless/ath/ath9k/mac.c
706
REG_WRITE(ah, AR_CR, AR_CR_RXD);
drivers/net/wireless/ath/ath9k/mac.c
786
REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
drivers/net/wireless/ath/ath9k/mac.c
789
REG_WRITE(ah, AR_INTR_ASYNC_ENABLE(ah), 0);
drivers/net/wireless/ath/ath9k/mac.c
792
REG_WRITE(ah, AR_INTR_SYNC_ENABLE(ah), 0);
drivers/net/wireless/ath/ath9k/mac.c
825
REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
drivers/net/wireless/ath/ath9k/mac.c
827
REG_WRITE(ah, AR_INTR_ASYNC_ENABLE(ah), async_mask);
drivers/net/wireless/ath/ath9k/mac.c
828
REG_WRITE(ah, AR_INTR_ASYNC_MASK(ah), async_mask);
drivers/net/wireless/ath/ath9k/mac.c
830
REG_WRITE(ah, AR_INTR_SYNC_ENABLE(ah), sync_default);
drivers/net/wireless/ath/ath9k/mac.c
831
REG_WRITE(ah, AR_INTR_SYNC_MASK(ah), sync_default);
drivers/net/wireless/ath/ath9k/mac.c
844
REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE(ah), ah->msi_mask);
drivers/net/wireless/ath/ath9k/mac.c
845
REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK(ah), ah->msi_mask);
drivers/net/wireless/ath/ath9k/mac.c
860
REG_WRITE(ah, AR_PCIE_MSI(ah),
drivers/net/wireless/ath/ath9k/mac.c
921
REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE(ah), 0);
drivers/net/wireless/ath/ath9k/mac.c
999
REG_WRITE(ah, AR_IMR, mask);
drivers/net/wireless/ath/hw.c
123
REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
drivers/net/wireless/ath/hw.c
126
REG_WRITE(ah, AR_STA_ID1, id1);
drivers/net/wireless/ath/hw.c
128
REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(common->bssidmask));
drivers/net/wireless/ath/hw.c
129
REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(common->bssidmask + 4));
drivers/net/wireless/ath/hw.c
148
REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC);
drivers/net/wireless/ath/hw.c
157
REG_WRITE(ah, AR_CCCNT, 0);
drivers/net/wireless/ath/hw.c
158
REG_WRITE(ah, AR_RFCNT, 0);
drivers/net/wireless/ath/hw.c
159
REG_WRITE(ah, AR_RCCNT, 0);
drivers/net/wireless/ath/hw.c
160
REG_WRITE(ah, AR_TFCNT, 0);
drivers/net/wireless/ath/hw.c
163
REG_WRITE(ah, AR_MIBC, 0);
drivers/net/wireless/ath/key.c
120
REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
drivers/net/wireless/ath/key.c
121
REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | unicast_flag);
drivers/net/wireless/ath/key.c
208
REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
drivers/net/wireless/ath/key.c
209
REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
drivers/net/wireless/ath/key.c
212
REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
drivers/net/wireless/ath/key.c
213
REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
drivers/net/wireless/ath/key.c
216
REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
drivers/net/wireless/ath/key.c
217
REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
drivers/net/wireless/ath/key.c
246
REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
drivers/net/wireless/ath/key.c
247
REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
drivers/net/wireless/ath/key.c
250
REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
drivers/net/wireless/ath/key.c
251
REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
drivers/net/wireless/ath/key.c
254
REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
drivers/net/wireless/ath/key.c
255
REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
drivers/net/wireless/ath/key.c
285
REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
drivers/net/wireless/ath/key.c
286
REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
drivers/net/wireless/ath/key.c
289
REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
drivers/net/wireless/ath/key.c
290
REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
drivers/net/wireless/ath/key.c
293
REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
drivers/net/wireless/ath/key.c
294
REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
drivers/net/wireless/ath/key.c
303
REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
drivers/net/wireless/ath/key.c
304
REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
drivers/net/wireless/ath/key.c
311
REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
drivers/net/wireless/ath/key.c
312
REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
drivers/net/wireless/ath/key.c
319
REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
drivers/net/wireless/ath/key.c
320
REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
drivers/net/wireless/ath/key.c
323
REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
drivers/net/wireless/ath/key.c
324
REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
drivers/net/wireless/ath/key.c
327
REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
drivers/net/wireless/ath/key.c
328
REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
drivers/net/wireless/ath/key.c
57
REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
drivers/net/wireless/ath/key.c
58
REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
drivers/net/wireless/ath/key.c
59
REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
drivers/net/wireless/ath/key.c
60
REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
drivers/net/wireless/ath/key.c
61
REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
drivers/net/wireless/ath/key.c
62
REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
drivers/net/wireless/ath/key.c
63
REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
drivers/net/wireless/ath/key.c
64
REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
drivers/net/wireless/ath/key.c
69
REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
drivers/net/wireless/ath/key.c
70
REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
drivers/net/wireless/ath/key.c
71
REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
drivers/net/wireless/ath/key.c
72
REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
drivers/net/wireless/ath/key.c
74
REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
drivers/net/wireless/ath/key.c
75
REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
drivers/net/wireless/mediatek/mt76/mt76_connac_mcu.c
2681
mt76_mcu_send_msg(dev, MCU_CE_CMD(REG_WRITE), &req,
drivers/net/wireless/st/cw1200/fwio.c
132
REG_WRITE(ST90TDS_SRAM_BASE_ADDR_REG_ID, 0xFFF20000);
drivers/net/wireless/st/cw1200/fwio.c
133
REG_WRITE(ST90TDS_AHB_DPORT_REG_ID, 0xEAFFFFFE);
drivers/net/wireless/st/cw1200/fwio.c
138
REG_WRITE(ST90TDS_CONFIG_REG_ID, val32);
drivers/net/wireless/st/cw1200/fwio.c
142
REG_WRITE(ST90TDS_CONFIG_REG_ID, val32);