REG_WOL_CTRL
AT_READ_REG(hw, REG_WOL_CTRL, p++);
AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
AT_WRITE_REG(hw, REG_WOL_CTRL, wol_ctrl);
AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
AT_READ_REG(hw, REG_WOL_CTRL, &data);
AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
AT_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0);
regs_buff[21] = AT_READ_REG(hw, REG_WOL_CTRL);
AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
AT_WRITE_REG(hw, REG_WOL_CTRL, wol_ctrl_data);
AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
AT_READ_REG(&adapter->hw, REG_WOL_CTRL); /* clear WOL status */
AT_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0);
iowrite32(ctrl, hw->hw_addr + REG_WOL_CTRL);
ioread32(hw->hw_addr + REG_WOL_CTRL);
iowrite32(ctrl, hw->hw_addr + REG_WOL_CTRL);
ioread32(hw->hw_addr + REG_WOL_CTRL);
iowrite32(0, hw->hw_addr + REG_WOL_CTRL);
ioread32(hw->hw_addr + REG_WOL_CTRL);
iowrite32(0, adapter->hw.hw_addr + REG_WOL_CTRL);
ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl);
ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl);
ATL2_WRITE_REG(hw, REG_WOL_CTRL, 0);
ATL2_READ_REG(&adapter->hw, REG_WOL_CTRL); /* clear WOL status */
ATL2_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0);
regs_buff[21] = ATL2_READ_REG(hw, REG_WOL_CTRL);