drivers/clk/mediatek/clk-pll.c

243

r = readl(pll->base_addr + REG_CON0) | pll->data->en_mask;

drivers/clk/mediatek/clk-pll.c

244

writel(r, pll->base_addr + REG_CON0);

drivers/clk/mediatek/clk-pll.c

252

r = readl(pll->base_addr + REG_CON0);

drivers/clk/mediatek/clk-pll.c

254

writel(r, pll->base_addr + REG_CON0);

drivers/clk/mediatek/clk-pll.c

266

r = readl(pll->base_addr + REG_CON0);

drivers/clk/mediatek/clk-pll.c

268

writel(r, pll->base_addr + REG_CON0);

drivers/clk/mediatek/clk-pll.c

274

r = readl(pll->base_addr + REG_CON0) & ~pll->data->en_mask;

drivers/clk/mediatek/clk-pll.c

275

writel(r, pll->base_addr + REG_CON0);

drivers/clk/mediatek/clk-pll.c

350

pll->en_addr = pll->base_addr + REG_CON0;