REG_W0
[REG_W0] = 0,
int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
EMIT2(0x1700, REG_W0, REG_W0);
EMIT4(0xb9970000, REG_W0, src_reg);
EMIT4(0xb91d0000, REG_W0, src_reg);
int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
EMIT4_IMM(0xa7090000, REG_W0, 0);
EMIT4(0xb9870000, REG_W0, src_reg);
EMIT4(0xb90d0000, REG_W0, src_reg);
int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
EMIT2(0x1700, REG_W0, REG_W0);
EMIT6_DISP_LH(0xe3000000, 0x0097, REG_W0, REG_0,
EMIT6_DISP_LH(0xe3000000, 0x001d, REG_W0, REG_0,
EMIT2(0x1700, REG_W0, REG_W0);
EMIT4(0xb9970000, REG_W0, dst_reg);
EMIT4(0xb90d0000, REG_W0, dst_reg);
int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
EMIT4_IMM(0xa7090000, REG_W0, 0);
EMIT6_DISP_LH(0xe3000000, 0x0087, REG_W0, REG_0,
EMIT6_DISP_LH(0xe3000000, 0x000d, REG_W0, REG_0,
EMIT4_IMM(0xa7090000, REG_W0, 0);
EMIT4(0xb9870000, REG_W0, dst_reg);
EMIT4(0xb90d0000, REG_W0, dst_reg);
EMIT6_PCREL_RILB(0xc4080000, REG_W0,
EMIT4(0xb9800000, dst_reg, REG_W0);
EMIT6_PCREL_RILB(0xc4080000, REG_W0,
EMIT4(0xb9810000, dst_reg, REG_W0);
EMIT6_PCREL_RILB(0xc4080000, REG_W0,
EMIT4(0xb9820000, dst_reg, REG_W0);
EMIT4_IMM(0xa7080000, REG_W0, (u8) imm);
EMIT6_DISP_LH(0xe3000000, 0x0072, REG_W0, dst_reg,
EMIT4_IMM(0xa7080000, REG_W0, (u16) imm);
EMIT6_DISP_LH(0xe3000000, 0x0070, REG_W0, dst_reg,
EMIT6_IMM(0xc00f0000, REG_W0, (u32) imm);
EMIT6_DISP_LH(0xe3000000, 0x0050, REG_W0, dst_reg,
EMIT6_IMM(0xc0010000, REG_W0, imm);
EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W0, dst_reg,
(insn->imm & BPF_FETCH) ? src_reg : REG_W0, \
is32 ? 0x0058 : 0x0004, REG_W0, REG_0,
REG_W0, src_reg, probe.arena_reg, off);
EMIT4(is32 ? 0xb9160000 : 0xb9040000, src_reg, REG_W0);
EMIT4_IMM(0xa7080000, REG_W0, 1);
EMIT6_DISP_LH(0xeb000000, 0x00fa, REG_W1, REG_W0, REG_15, off);
load_imm64(jit, REG_W0, tlink->cookie);
EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W0, REG_0, REG_15, cookie_off);
#define REG_0 REG_W0 /* Register 0 */