drivers/accel/ivpu/ivpu_hw_btrs.c

391

val = REG_CLR_FLD(VPU_HW_BTRS_MTL_VPU_D0I3_CONTROL, I3, val);

drivers/accel/ivpu/ivpu_hw_btrs.c

416

val = REG_CLR_FLD(VPU_HW_BTRS_LNL_D0I3_CONTROL, I3, val);

drivers/accel/ivpu/ivpu_hw_btrs.c

542

val = REG_CLR_FLD(VPU_HW_BTRS_LNL_VPU_STATUS, PERF_CLK, val);

drivers/accel/ivpu/ivpu_hw_ip.c

236

val = REG_CLR_FLD(VPU_37XX_HOST_SS_AON_VPU_IDLE_GEN, EN, val);

drivers/accel/ivpu/ivpu_hw_ip.c

248

val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_IDLE_GEN, EN, val);

drivers/accel/ivpu/ivpu_hw_ip.c

292

val = REG_CLR_FLD(VPU_37XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, MSS_CPU, val);

drivers/accel/ivpu/ivpu_hw_ip.c

304

val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, CSS_CPU, val);

drivers/accel/ivpu/ivpu_hw_ip.c

316

val = REG_CLR_FLD(VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0, MSS_CPU, val);

drivers/accel/ivpu/ivpu_hw_ip.c

328

val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0, CSS_CPU, val);

drivers/accel/ivpu/ivpu_hw_ip.c

366

val = REG_CLR_FLD(VPU_37XX_HOST_SS_AON_PWR_ISO_EN0, MSS_CPU, val);

drivers/accel/ivpu/ivpu_hw_ip.c

378

val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0, CSS_CPU, val);

drivers/accel/ivpu/ivpu_hw_ip.c

405

val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, TOP_NOC, val);

drivers/accel/ivpu/ivpu_hw_ip.c

406

val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, DSS_MAS, val);

drivers/accel/ivpu/ivpu_hw_ip.c

407

val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, MSS_MAS, val);

drivers/accel/ivpu/ivpu_hw_ip.c

422

val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, TOP_NOC, val);

drivers/accel/ivpu/ivpu_hw_ip.c

423

val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, DSS_MAS, val);

drivers/accel/ivpu/ivpu_hw_ip.c

424

val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, CSS_MAS, val);

drivers/accel/ivpu/ivpu_hw_ip.c

452

val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, TOP_NOC, val);

drivers/accel/ivpu/ivpu_hw_ip.c

453

val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, DSS_MAS, val);

drivers/accel/ivpu/ivpu_hw_ip.c

454

val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, MSS_MAS, val);

drivers/accel/ivpu/ivpu_hw_ip.c

469

val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, TOP_NOC, val);

drivers/accel/ivpu/ivpu_hw_ip.c

470

val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, DSS_MAS, val);

drivers/accel/ivpu/ivpu_hw_ip.c

471

val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, CSS_MAS, val);

drivers/accel/ivpu/ivpu_hw_ip.c

497

val = REG_CLR_FLD(VPU_37XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, val);

drivers/accel/ivpu/ivpu_hw_ip.c

508

val = REG_CLR_FLD(VPU_40XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, val);

drivers/accel/ivpu/ivpu_hw_ip.c

547

val = REG_CLR_FLD(VPU_40XX_TOP_NOC_QREQN, CPU_CTRL, val);

drivers/accel/ivpu/ivpu_hw_ip.c

548

val = REG_CLR_FLD(VPU_40XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, val);

drivers/accel/ivpu/ivpu_hw_ip.c

562

val = REG_CLR_FLD(VPU_37XX_TOP_NOC_QREQN, CPU_CTRL, val);

drivers/accel/ivpu/ivpu_hw_ip.c

563

val = REG_CLR_FLD(VPU_37XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, val);

drivers/accel/ivpu/ivpu_hw_ip.c

673

val = REG_CLR_FLD(VPU_37XX_HOST_SS_AON_DPU_ACTIVE, DPU_ACTIVE, val);

drivers/accel/ivpu/ivpu_hw_ip.c

753

val = REG_CLR_FLD(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES, AW_NOSNOOP_OVERRIDE, val);

drivers/accel/ivpu/ivpu_hw_ip.c

756

val = REG_CLR_FLD(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES, AR_NOSNOOP_OVERRIDE, val);

drivers/accel/ivpu/ivpu_hw_ip.c

773

val = REG_CLR_FLD(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, AR_SNOOP_OVERRIDE, val);

drivers/accel/ivpu/ivpu_hw_ip.c

835

val = REG_CLR_FLD(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, IRQI_RSTVEC, val);

drivers/accel/ivpu/ivpu_hw_ip.c

841

val = REG_CLR_FLD(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, IRQI_RESUME0, val);

drivers/accel/ivpu/ivpu_hw_ip.c

880

val = REG_CLR_FLD(VPU_40XX_CPU_SS_CPR_NOC_QREQN, TOP_MMIO, val);

drivers/accel/ivpu/ivpu_hw_ip.c

980

val = REG_CLR_FLD(VPU_37XX_CPU_SS_TIM_GEN_CONFIG, WDOG_TO_INT_CLR, val);

drivers/accel/ivpu/ivpu_hw_ip.c

995

val = REG_CLR_FLD(VPU_40XX_CPU_SS_TIM_GEN_CONFIG, WDOG_TO_INT_CLR, val);

drivers/accel/ivpu/ivpu_mmu.c

880

val = REG_CLR_FLD(IVPU_MMU_REG_CR0, EVTQEN, val);