drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c

70

REG_UPDATE(BIOS_SCRATCH_6, S6_ACC_MODE, state);

drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c

79

REG_UPDATE(BIOS_SCRATCH_6, S6_CRITICAL_STATE, critial_state);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

180

REG_UPDATE(DENTIST_DISPCLK_CNTL,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

207

REG_UPDATE(DENTIST_DISPCLK_CNTL,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

210

REG_UPDATE(DENTIST_DISPCLK_CNTL,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

419

REG_UPDATE(DENTIST_DISPCLK_CNTL,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

466

REG_UPDATE(DENTIST_DISPCLK_CNTL,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

635

REG_UPDATE(DENTIST_DISPCLK_CNTL,

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

104

REG_UPDATE(DISPCLK_FREQ_CHANGE_CNTL,

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

116

REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst],

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

128

REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst],

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

181

REG_UPDATE(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, enable ? 0 : 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

67

REG_UPDATE(DPPCLK_DTO_CTRL,

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

70

REG_UPDATE(DPPCLK_DTO_CTRL,

drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c

92

REG_UPDATE(DPPCLK_DTO_CTRL,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

105

REG_UPDATE(DPSTREAMCLK_CNTL,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

109

REG_UPDATE(DPSTREAMCLK_CNTL,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

113

REG_UPDATE(DPSTREAMCLK_CNTL,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

117

REG_UPDATE(DPSTREAMCLK_CNTL,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

141

REG_UPDATE(DPSTREAMCLK_CNTL,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

145

REG_UPDATE(DPSTREAMCLK_CNTL,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

149

REG_UPDATE(DPSTREAMCLK_CNTL,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

153

REG_UPDATE(DPSTREAMCLK_CNTL,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

364

REG_UPDATE(DSCCLK_DTO_CTRL,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

371

REG_UPDATE(DSCCLK_DTO_CTRL,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

378

REG_UPDATE(DSCCLK_DTO_CTRL,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

386

REG_UPDATE(DSCCLK_DTO_CTRL,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

411

REG_UPDATE(DSCCLK_DTO_CTRL,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

418

REG_UPDATE(DSCCLK_DTO_CTRL,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

425

REG_UPDATE(DSCCLK_DTO_CTRL,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

430

REG_UPDATE(DSCCLK_DTO_CTRL,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

459

REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

466

REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

476

REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

483

REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

493

REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

500

REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

510

REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

517

REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

527

REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

534

REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

581

REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst],

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

587

REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst],

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

598

REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst],

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

632

REG_UPDATE(DCCG_AUDIO_DTO_SOURCE,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

638

REG_UPDATE(DCCG_AUDIO_DTO_SOURCE,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

661

REG_UPDATE(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_MODE,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

700

REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst],

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

709

REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst],

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

75

REG_UPDATE(DPPCLK_DTO_CTRL,

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

78

REG_UPDATE(DPPCLK_DTO_CTRL,

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

164

REG_UPDATE(DTBCLK_P_CNTL,

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

173

REG_UPDATE(DTBCLK_P_CNTL,

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

182

REG_UPDATE(DTBCLK_P_CNTL,

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

191

REG_UPDATE(DTBCLK_P_CNTL,

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

224

REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst],

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

238

REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst],

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

342

REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_ENABLE[dpp_inst], 0);

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

348

REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_ENABLE[dpp_inst], 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c

56

REG_UPDATE(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, dispclk_rdivider_value);

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

163

REG_UPDATE(DTBCLK_P_CNTL,

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

172

REG_UPDATE(DTBCLK_P_CNTL,

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

181

REG_UPDATE(DTBCLK_P_CNTL,

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

190

REG_UPDATE(DTBCLK_P_CNTL,

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

223

REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst],

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

237

REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst],

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

318

REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst],

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

327

REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst],

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c

56

REG_UPDATE(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, dispclk_rdivider_value);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1116

REG_UPDATE(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, dispclk_rdivider_value);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1138

REG_UPDATE(DPPCLK_CTRL, DPPCLK0_EN, enable);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1141

REG_UPDATE(DPPCLK_CTRL, DPPCLK1_EN, enable);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1144

REG_UPDATE(DPPCLK_CTRL, DPPCLK2_EN, enable);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1147

REG_UPDATE(DPPCLK_CTRL, DPPCLK3_EN, enable);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1205

REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK0_ROOT_GATE_DISABLE, disallow_rcg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1208

REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK1_ROOT_GATE_DISABLE, disallow_rcg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1211

REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK2_ROOT_GATE_DISABLE, disallow_rcg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1214

REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK3_ROOT_GATE_DISABLE, disallow_rcg);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1332

REG_UPDATE(DTBCLK_P_CNTL,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1341

REG_UPDATE(DTBCLK_P_CNTL,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1350

REG_UPDATE(DTBCLK_P_CNTL,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1359

REG_UPDATE(DTBCLK_P_CNTL,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1387

REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1390

REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1393

REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1396

REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1407

REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst],

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1430

REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, 0);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1433

REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, 0);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1436

REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, 0);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1439

REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, 0);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1447

REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst],

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

147

REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK0_ROOT_GATE_DISABLE, allow_rcg ? 0 : 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1474

REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK0_ROOT_GATE_DISABLE, (src == REFCLK) ? 0 : 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1480

REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK1_ROOT_GATE_DISABLE, (src == REFCLK) ? 0 : 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1486

REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK2_ROOT_GATE_DISABLE, (src == REFCLK) ? 0 : 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1492

REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK3_ROOT_GATE_DISABLE, (src == REFCLK) ? 0 : 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

150

REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK1_ROOT_GATE_DISABLE, allow_rcg ? 0 : 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1509

REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK0_ROOT_GATE_DISABLE, enable ? 1 : 0);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1510

REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK0_GATE_DISABLE, enable ? 1 : 0);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1515

REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK1_ROOT_GATE_DISABLE, enable ? 1 : 0);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1516

REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK1_GATE_DISABLE, enable ? 1 : 0);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1521

REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK2_ROOT_GATE_DISABLE, enable ? 1 : 0);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1522

REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK2_GATE_DISABLE, enable ? 1 : 0);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1527

REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK3_ROOT_GATE_DISABLE, enable ? 1 : 0);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1528

REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK3_GATE_DISABLE, enable ? 1 : 0);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

153

REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK2_ROOT_GATE_DISABLE, allow_rcg ? 0 : 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1553

REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1557

REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

156

REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK3_ROOT_GATE_DISABLE, allow_rcg ? 0 : 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1561

REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1565

REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1569

REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1712

REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1723

REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1734

REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1745

REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1805

REG_UPDATE(DCCG_GLOBAL_FGCG_REP_CNTL, DCCG_GLOBAL_FGCG_REP_DIS, !value);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1815

REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK0_ROOT_GATE_DISABLE, 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1820

REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK0_EN, 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1823

REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK1_ROOT_GATE_DISABLE, 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1828

REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK1_EN, 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1831

REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK2_ROOT_GATE_DISABLE, 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1836

REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK2_EN, 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1839

REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK3_ROOT_GATE_DISABLE, 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1844

REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK3_EN, 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1861

REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK0_EN, 0);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1866

REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK0_ROOT_GATE_DISABLE, 0);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1869

REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK1_EN, 0);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1874

REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK1_ROOT_GATE_DISABLE, 0);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1877

REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK2_EN, 0);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1882

REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK2_ROOT_GATE_DISABLE, 0);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1885

REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK3_EN, 0);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1890

REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK3_ROOT_GATE_DISABLE, 0);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1906

REG_UPDATE(SYMCLKA_CLOCK_ENABLE,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1909

REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKA_ROOT_GATE_DISABLE, 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1912

REG_UPDATE(SYMCLKB_CLOCK_ENABLE,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1915

REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKB_ROOT_GATE_DISABLE, 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1918

REG_UPDATE(SYMCLKC_CLOCK_ENABLE,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1921

REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKC_ROOT_GATE_DISABLE, 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1924

REG_UPDATE(SYMCLKD_CLOCK_ENABLE,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1927

REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKD_ROOT_GATE_DISABLE, 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1930

REG_UPDATE(SYMCLKE_CLOCK_ENABLE,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1933

REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKE_ROOT_GATE_DISABLE, 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1943

REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKA_FE_ROOT_GATE_DISABLE, 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1950

REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKB_FE_ROOT_GATE_DISABLE, 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1957

REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKC_FE_ROOT_GATE_DISABLE, 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1964

REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKD_FE_ROOT_GATE_DISABLE, 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1971

REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKE_FE_ROOT_GATE_DISABLE, 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2057

REG_UPDATE(SYMCLKA_CLOCK_ENABLE,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2063

REG_UPDATE(SYMCLKB_CLOCK_ENABLE,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2069

REG_UPDATE(SYMCLKC_CLOCK_ENABLE,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2075

REG_UPDATE(SYMCLKD_CLOCK_ENABLE,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2081

REG_UPDATE(SYMCLKE_CLOCK_ENABLE,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2323

REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst],

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

2337

REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst],

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

246

REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

250

REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

254

REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

258

REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

262

REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

283

REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

285

REG_UPDATE(DCCG_GATE_DISABLE_CNTL5,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

289

REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

291

REG_UPDATE(DCCG_GATE_DISABLE_CNTL5,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

295

REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

297

REG_UPDATE(DCCG_GATE_DISABLE_CNTL5,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

301

REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

303

REG_UPDATE(DCCG_GATE_DISABLE_CNTL5,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

307

REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

309

REG_UPDATE(DCCG_GATE_DISABLE_CNTL5,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

332

REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

334

REG_UPDATE(DCCG_GATE_DISABLE_CNTL5,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

338

REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

340

REG_UPDATE(DCCG_GATE_DISABLE_CNTL5,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

344

REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

346

REG_UPDATE(DCCG_GATE_DISABLE_CNTL5,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

350

REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

352

REG_UPDATE(DCCG_GATE_DISABLE_CNTL5,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

356

REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

358

REG_UPDATE(DCCG_GATE_DISABLE_CNTL5,

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

377

REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, enable ? 0 : 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

380

REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, enable ? 0 : 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

383

REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, enable ? 0 : 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

386

REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, enable ? 0 : 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

403

REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK0_ROOT_GATE_DISABLE, allow_rcg ? 0 : 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

406

REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK1_ROOT_GATE_DISABLE, allow_rcg ? 0 : 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

409

REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK2_ROOT_GATE_DISABLE, allow_rcg ? 0 : 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

412

REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK3_ROOT_GATE_DISABLE, allow_rcg ? 0 : 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

506

REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK0_EN, src);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

509

REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK1_EN, src);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

512

REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK2_EN, src);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

515

REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK3_EN, src);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

606

REG_UPDATE(DPPCLK_CTRL, DPPCLK0_EN, src);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

609

REG_UPDATE(DPPCLK_CTRL, DPPCLK1_EN, src);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

612

REG_UPDATE(DPPCLK_CTRL, DPPCLK2_EN, src);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

615

REG_UPDATE(DPPCLK_CTRL, DPPCLK3_EN, src);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

183

REG_UPDATE(OTG_PIXEL_RATE_DIV,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

189

REG_UPDATE(OTG_PIXEL_RATE_DIV,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

195

REG_UPDATE(OTG_PIXEL_RATE_DIV,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

201

REG_UPDATE(OTG_PIXEL_RATE_DIV,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

227

REG_UPDATE(DTBCLK_P_CNTL,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

236

REG_UPDATE(DTBCLK_P_CNTL,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

245

REG_UPDATE(DTBCLK_P_CNTL,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

254

REG_UPDATE(DTBCLK_P_CNTL,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

284

REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

291

REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

301

REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

308

REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

318

REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

325

REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

335

REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

342

REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

369

REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst],

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

378

REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst],

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

541

REG_UPDATE(DPSTREAMCLK_CNTL,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

549

REG_UPDATE(DPSTREAMCLK_CNTL,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

557

REG_UPDATE(DPSTREAMCLK_CNTL,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

565

REG_UPDATE(DPSTREAMCLK_CNTL,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

626

REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

63

REG_UPDATE(DPPCLK_CTRL, DPPCLK0_EN, enable);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

634

REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

642

REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

650

REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

66

REG_UPDATE(DPPCLK_CTRL, DPPCLK1_EN, enable);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

666

REG_UPDATE(OTG_PIXEL_RATE_DIV,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

670

REG_UPDATE(OTG_PIXEL_RATE_DIV,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

674

REG_UPDATE(OTG_PIXEL_RATE_DIV,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

678

REG_UPDATE(OTG_PIXEL_RATE_DIV,

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

69

REG_UPDATE(DPPCLK_CTRL, DPPCLK2_EN, enable);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

72

REG_UPDATE(DPPCLK_CTRL, DPPCLK3_EN, enable);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

735

REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK0_EN, 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

742

REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK1_EN, 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

748

REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK2_EN, 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

754

REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK3_EN, 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

769

REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK0_EN, 0);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

775

REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK1_EN, 0);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

781

REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK2_EN, 0);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

787

REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK3_EN, 0);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

807

REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKA_FE_ROOT_GATE_DISABLE, 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

814

REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKB_FE_ROOT_GATE_DISABLE, 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

821

REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKC_FE_ROOT_GATE_DISABLE, 1);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

828

REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKD_FE_ROOT_GATE_DISABLE, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_abm.c

110

REG_UPDATE(BL1_PWM_USER_LEVEL, BL1_PWM_USER_LEVEL, backlight_pwm_u16_16);

drivers/gpu/drm/amd/display/dc/dce/dce_abm.c

118

REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_BL_SET);

drivers/gpu/drm/amd/display/dc/dce/dce_abm.c

121

REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_abm.c

158

REG_UPDATE(BL1_PWM_CURRENT_ABM_LEVEL,

drivers/gpu/drm/amd/display/dc/dce/dce_abm.c

161

REG_UPDATE(BL1_PWM_TARGET_ABM_LEVEL,

drivers/gpu/drm/amd/display/dc/dce/dce_abm.c

164

REG_UPDATE(BL1_PWM_USER_LEVEL,

drivers/gpu/drm/amd/display/dc/dce/dce_abm.c

215

REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_abm.c

78

REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_audio.c

1107

REG_UPDATE(DCCG_AUDIO_DTO0_MODULE,

drivers/gpu/drm/amd/display/dc/dce/dce_audio.c

1111

REG_UPDATE(DCCG_AUDIO_DTO0_PHASE,

drivers/gpu/drm/amd/display/dc/dce/dce_audio.c

1129

REG_UPDATE(DCCG_AUDIO_DTO_SOURCE,

drivers/gpu/drm/amd/display/dc/dce/dce_audio.c

1139

REG_UPDATE(DCCG_AUDIO_DTO1_MODULE,

drivers/gpu/drm/amd/display/dc/dce/dce_audio.c

1143

REG_UPDATE(DCCG_AUDIO_DTO1_PHASE,

drivers/gpu/drm/amd/display/dc/dce/dce_audio.c

1147

REG_UPDATE(DCCG_AUDIO_DTO_SOURCE,

drivers/gpu/drm/amd/display/dc/dce/dce_audio.c

1200

REG_UPDATE(DCCG_AUDIO_DTO0_MODULE,

drivers/gpu/drm/amd/display/dc/dce/dce_audio.c

1204

REG_UPDATE(DCCG_AUDIO_DTO0_PHASE,

drivers/gpu/drm/amd/display/dc/dce/dce_audio.c

1222

REG_UPDATE(DCCG_AUDIO_DTO_SOURCE,

drivers/gpu/drm/amd/display/dc/dce/dce_audio.c

1232

REG_UPDATE(DCCG_AUDIO_DTO1_MODULE,

drivers/gpu/drm/amd/display/dc/dce/dce_audio.c

1236

REG_UPDATE(DCCG_AUDIO_DTO1_PHASE,

drivers/gpu/drm/amd/display/dc/dce/dce_audio.c

1282

REG_UPDATE(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES,

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

163

REG_UPDATE(AUX_ARB_CONTROL, AUX_SW_USE_AUX_REG_REQ, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

219

REG_UPDATE(AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

276

REG_UPDATE(AUX_SW_CONTROL, AUX_SW_GO, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1007

REG_UPDATE(PIXEL_RATE_CNTL[inst],

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1012

REG_UPDATE(PIXEL_RATE_CNTL[inst],

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1312

REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 0);

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1315

REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1356

REG_UPDATE(PIXEL_RATE_CNTL[inst],

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

765

REG_UPDATE(RESYNC_CNTL,

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

778

REG_UPDATE(RESYNC_CNTL,

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

782

REG_UPDATE(RESYNC_CNTL,

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

786

REG_UPDATE(RESYNC_CNTL,

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

790

REG_UPDATE(RESYNC_CNTL,

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

839

REG_UPDATE(PIXCLK_RESYNC_CNTL,

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

1005

REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

1009

REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

113

REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

126

REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 0);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

145

REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

148

REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

152

REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

195

REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

199

REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

203

REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

207

REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

224

REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

271

REG_UPDATE(MASTER_COMM_CMD_REG,

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

275

REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

318

REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, PSR_SET_WAITLOOP);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

321

REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

369

REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

373

REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

424

REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

428

REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

507

REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

511

REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

530

REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

543

REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 0);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

566

REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

569

REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

573

REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

630

REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

634

REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

638

REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

642

REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

659

REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

668

REG_UPDATE(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

711

REG_UPDATE(MASTER_COMM_CMD_REG,

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

715

REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

744

REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, PSR_SET_WAITLOOP);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

747

REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

780

REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_SYNC_PHY_LOCK);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

783

REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

803

REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_SYNC_PHY_UNLOCK);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

806

REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

840

REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_SEND_EDID_CEA);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

847

REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

873

REG_UPDATE(SLAVE_COMM_CNTL_REG, SLAVE_COMM_INTERRUPT, 0);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

973

REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

977

REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c

310

REG_UPDATE(DC_I2C_ARBITRATION, DC_I2C_SW_USE_I2C_REG_REQ, true);

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c

322

REG_UPDATE(DC_I2C_CONTROL, DC_I2C_SOFT_RESET, false);

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c

329

REG_UPDATE(DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, 0);

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c

373

REG_UPDATE(DC_I2C_ARBITRATION,

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c

400

REG_UPDATE(DC_I2C_ARBITRATION, DC_I2C_SW_DONE_USING_I2C_REG, true);

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c

425

REG_UPDATE(DC_I2C_CONTROL, DC_I2C_SW_STATUS_RESET, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c

433

REG_UPDATE(DC_I2C_ARBITRATION, DC_I2C_SW_DONE_USING_I2C_REG, true);

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c

438

REG_UPDATE(DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c

59

REG_UPDATE(DC_I2C_CONTROL, DC_I2C_GO, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c

134

REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, false);

drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c

144

REG_UPDATE(PRESCALE_GRPH_CONTROL,

drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c

160

REG_UPDATE(PRESCALE_GRPH_CONTROL,

drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c

164

REG_UPDATE(INPUT_GAMMA_CONTROL,

drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c

184

REG_UPDATE(DC_LUT_RW_MODE, DC_LUT_RW_MODE, 0);

drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c

213

REG_UPDATE(PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c

214

REG_UPDATE(INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);

drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c

49

REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, true);

drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c

53

REG_UPDATE(CUR_CONTROL, CURSOR_EN, position->enable);

drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c

64

REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, false);

drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c

75

REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, true);

drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c

1105

REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 0);

drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c

1109

REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c

1114

REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 2);

drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c

1118

REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 3);

drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c

1122

REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 5);

drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c

159

REG_UPDATE(DP_DPHY_CNTL, DPHY_BYPASS, enable);

drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c

1701

REG_UPDATE(DP_MSE_SAT_UPDATE,

drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c

1749

REG_UPDATE(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, field);

drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c

180

REG_UPDATE(DP_DPHY_PRBS_CNTL, DPHY_PRBS_EN, 0);

drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c

249

REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, complete);

drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c

465

REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0);

drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c

469

REG_UPDATE(DP_DPHY_HBR2_PATTERN_CONTROL,

drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c

479

REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);

drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c

521

REG_UPDATE(DP_DPHY_HBR2_PATTERN_CONTROL,

drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c

531

REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);

drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c

553

REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0x1FF);

drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c

629

REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_ADVANCE, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c

674

REG_UPDATE(DP_DPHY_FAST_TRAINING,

drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c

677

REG_UPDATE(DP_DPHY_FAST_TRAINING,

drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c

688

REG_UPDATE(DP_DPHY_BS_SR_SWAP_CNTL, DPHY_LOAD_BS_COUNT, 0x5);

drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c

718

REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, 0);

drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c

730

REG_UPDATE(DIG_BE_CNTL, DIG_HPD_SELECT, hpd_source);

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c

150

REG_UPDATE(GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT,

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c

169

REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c

184

REG_UPDATE(DPG_PIPE_ARBITRATION_CONTROL3,

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c

199

REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c

218

REG_UPDATE(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL,

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c

226

REG_UPDATE(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL,

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c

237

REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c

245

REG_UPDATE(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL,

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c

250

REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c

258

REG_UPDATE(DPG_PIPE_LOW_POWER_CONTROL,

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c

269

REG_UPDATE(DPG_PIPE_STUTTER_CONTROL,

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c

272

REG_UPDATE(DPG_PIPE_STUTTER_CONTROL,

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c

283

REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c

301

REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c

305

REG_UPDATE(DPG_PIPE_STUTTER_CONTROL2,

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c

308

REG_UPDATE(DPG_PIPE_STUTTER_CONTROL,

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c

635

REG_UPDATE(GRPH_CONTROL,

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c

640

REG_UPDATE(GRPH_CONTROL,

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c

645

REG_UPDATE(GRPH_CONTROL,

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c

660

REG_UPDATE(GRPH_ENABLE, GRPH_ENABLE, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c

680

REG_UPDATE(GRPH_ENABLE, GRPH_ENABLE, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c

770

REG_UPDATE(DPG_PIPE_ARBITRATION_CONTROL1,

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c

778

REG_UPDATE(MC_HUB_RDREQ_DMIF_LIMIT,

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c

808

REG_UPDATE(MC_HUB_RDREQ_DMIF_LIMIT,

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c

863

REG_UPDATE(GRPH_UPDATE, GRPH_UPDATE_LOCK, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c

865

REG_UPDATE(

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c

893

REG_UPDATE(GRPH_UPDATE, GRPH_UPDATE_LOCK, 0);

drivers/gpu/drm/amd/display/dc/dce/dce_opp.c

214

REG_UPDATE(FMT_BIT_DEPTH_CONTROL,

drivers/gpu/drm/amd/display/dc/dce/dce_opp.c

245

REG_UPDATE(FMT_DITHER_RAND_R_SEED,

drivers/gpu/drm/amd/display/dc/dce/dce_opp.c

248

REG_UPDATE(FMT_DITHER_RAND_G_SEED,

drivers/gpu/drm/amd/display/dc/dce/dce_opp.c

251

REG_UPDATE(FMT_DITHER_RAND_B_SEED,

drivers/gpu/drm/amd/display/dc/dce/dce_opp.c

341

REG_UPDATE(FMT_BIT_DEPTH_CONTROL,

drivers/gpu/drm/amd/display/dc/dce/dce_opp.c

350

REG_UPDATE(FMT_BIT_DEPTH_CONTROL,

drivers/gpu/drm/amd/display/dc/dce/dce_opp.c

516

REG_UPDATE(FMT_CONTROL,

drivers/gpu/drm/amd/display/dc/dce/dce_opp.c

520

REG_UPDATE(FMT_CONTROL,

drivers/gpu/drm/amd/display/dc/dce/dce_opp.c

589

REG_UPDATE(FMT_CONTROL,

drivers/gpu/drm/amd/display/dc/dce/dce_opp.c

593

REG_UPDATE(CONTROL,

drivers/gpu/drm/amd/display/dc/dce/dce_opp.c

642

REG_UPDATE(FMT_CONTROL,

drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c

108

REG_UPDATE(PWRSEQ_REF_DIV,

drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c

136

REG_UPDATE(BL_PWM_CNTL, BL_PWM_EN, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c

139

REG_UPDATE(BL_PWM_GRP1_REG_LOCK,

drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c

242

REG_UPDATE(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, backlight_16bit);

drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c

245

REG_UPDATE(BL_PWM_GRP1_REG_LOCK,

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

1009

REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

1019

REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, value);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

1252

REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, channels);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

1274

REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

1299

REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

1302

REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

1305

REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

1308

REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

1311

REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

1314

REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

1328

REG_UPDATE(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

1360

REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

1369

REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

1372

REG_UPDATE(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, 0);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

1384

REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, !!enable);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

140

REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

1403

REG_UPDATE(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

1411

REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

1432

REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

144

REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

1442

REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, !mute);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

148

REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

1491

REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

1492

REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

1502

REG_UPDATE(DAC_SOURCE_SELECT, DAC_SOURCE_SELECT, tg_inst);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

1504

REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

152

REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

156

REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

160

REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

164

REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

168

REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

298

REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

302

REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

310

REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

318

REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

321

REG_UPDATE(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

324

REG_UPDATE(DP_VID_TIMING, DP_VID_N_MUL, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

327

REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

339

REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

343

REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

347

REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

352

REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

356

REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

510

REG_UPDATE(TMDS_CNTL, TMDS_PIXEL_ENCODING, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

513

REG_UPDATE(TMDS_CNTL, TMDS_PIXEL_ENCODING, 0);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

516

REG_UPDATE(TMDS_CNTL, TMDS_COLOR_FORMAT, 0);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

520

REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

523

REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 0);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

526

REG_UPDATE(DIG_FE_CNTL, TMDS_COLOR_FORMAT, 0);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

572

REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

634

REG_UPDATE(HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, 0);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

637

REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

639

REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

641

REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE,

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

644

REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

738

REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

74

REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

748

REG_UPDATE(AFMT_AVI_INFO3, AFMT_AVI_INFO_VERSION,

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

755

REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE,

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

776

REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

857

REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

858

REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

859

REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

870

REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

896

REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

920

REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

928

REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

94

REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

945

REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, true);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

975

REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

981

REG_UPDATE(DP_VID_N, DP_VID_N, n_vid);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

983

REG_UPDATE(DP_VID_M, DP_VID_M, m_vid);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

985

REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

99

REG_UPDATE(AFMT_VBI_PACKET_CONTROL,

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

990

REG_UPDATE(DIG_FE_CNTL, DIG_START, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

994

REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0);

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

127

REG_UPDATE(SCL_MODE, SCL_MODE, 0);

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

136

REG_UPDATE(SCL_MODE, SCL_MODE, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

138

REG_UPDATE(SCL_MODE, SCL_MODE, 2);

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

141

REG_UPDATE(SCL_MODE, SCL_PSCL_EN, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1424

REG_UPDATE(DCFE_MEM_PWR_CTRL,

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1427

REG_UPDATE(DCFE_MEM_LIGHT_SLEEP_CNTL,

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1457

REG_UPDATE(REGAMMA_LUT_WRITE_EN_MASK,

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1478

REG_UPDATE(DCFE_MEM_PWR_CTRL,

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1481

REG_UPDATE(DCFE_MEM_LIGHT_SLEEP_CNTL,

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

487

REG_UPDATE(SCL_UPDATE, SCL_COEF_UPDATE_COMPLETE, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

489

REG_UPDATE(LB_DATA_FORMAT, ALPHA_EN, data->lb_params.alpha_en);

drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c

101

REG_UPDATE(BL1_PWM_TARGET_ABM_LEVEL,

drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c

104

REG_UPDATE(BL1_PWM_USER_LEVEL,

drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c

98

REG_UPDATE(BL1_PWM_CURRENT_ABM_LEVEL,

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c

76

REG_UPDATE(WB_ENABLE, WB_ENABLE, 1);

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c

86

REG_UPDATE(CNV_MODE, CNV_FRAME_CAPTURE_EN, 0);

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c

89

REG_UPDATE(WB_ENABLE, WB_ENABLE, 0);

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c

92

REG_UPDATE(WB_SOFT_RESET, WB_SOFT_RESET, 1);

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c

93

REG_UPDATE(WB_SOFT_RESET, WB_SOFT_RESET, 0);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

118

REG_UPDATE(WB_ENABLE, WB_ENABLE, 1);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

127

REG_UPDATE(CNV_MODE, CNV_FRAME_CAPTURE_EN, DWB_FRAME_CAPTURE_ENABLE);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

130

REG_UPDATE(WB_WARM_UP_MODE_CTL1, GMC_WARM_UP_ENABLE, 0);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

141

REG_UPDATE(CNV_MODE, CNV_FRAME_CAPTURE_EN, DWB_FRAME_CAPTURE_DISABLE);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

144

REG_UPDATE(WB_ENABLE, WB_ENABLE, 0);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

147

REG_UPDATE(WB_SOFT_RESET, WB_SOFT_RESET, 1);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

148

REG_UPDATE(WB_SOFT_RESET, WB_SOFT_RESET, 0);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

181

REG_UPDATE(CNV_UPDATE, CNV_UPDATE_LOCK, 1);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

192

REG_UPDATE(CNV_UPDATE, CNV_UPDATE_LOCK, 0);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

218

REG_UPDATE(CNV_MODE, CNV_STEREO_TYPE, stereo_params->stereo_type);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

219

REG_UPDATE(CNV_MODE, CNV_EYE_SELECTION, stereo_params->stereo_eye_select);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

220

REG_UPDATE(CNV_MODE, CNV_STEREO_POLARITY, stereo_params->stereo_polarity);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

222

REG_UPDATE(CNV_MODE, CNV_EYE_SELECTION, 0);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

232

REG_UPDATE(CNV_MODE, CNV_NEW_CONTENT, is_new_content);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

241

REG_UPDATE(WB_WARM_UP_MODE_CTL1, GMC_WARM_UP_ENABLE, warmup_params->warmup_en);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

242

REG_UPDATE(WB_WARM_UP_MODE_CTL1, WIDTH_WARMUP, warmup_params->warmup_width);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

243

REG_UPDATE(WB_WARM_UP_MODE_CTL1, HEIGHT_WARMUP, warmup_params->warmup_height);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

245

REG_UPDATE(WB_WARM_UP_MODE_CTL2, DATA_VALUE_WARMUP, warmup_params->warmup_data);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

246

REG_UPDATE(WB_WARM_UP_MODE_CTL2, MODE_WARMUP, warmup_params->warmup_mode);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

247

REG_UPDATE(WB_WARM_UP_MODE_CTL2, DATA_DEPTH_WARMUP, warmup_params->warmup_depth);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

261

REG_UPDATE(WBSCL_DEST_SIZE, WBSCL_DEST_WIDTH, params->dest_width);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

262

REG_UPDATE(WBSCL_DEST_SIZE, WBSCL_DEST_HEIGHT, params->dest_height);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

265

REG_UPDATE(WBSCL_ROUND_OFFSET, WBSCL_ROUND_OFFSET_Y_RGB, 0x40);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

266

REG_UPDATE(WBSCL_ROUND_OFFSET, WBSCL_ROUND_OFFSET_CBCR, 0x200);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

269

REG_UPDATE(WBSCL_CLAMP_Y_RGB, WBSCL_CLAMP_UPPER_Y_RGB, 0x3fe);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

270

REG_UPDATE(WBSCL_CLAMP_Y_RGB, WBSCL_CLAMP_LOWER_Y_RGB, 0x1);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

271

REG_UPDATE(WBSCL_CLAMP_CBCR, WBSCL_CLAMP_UPPER_CBCR, 0x3fe);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

272

REG_UPDATE(WBSCL_CLAMP_CBCR, WBSCL_CLAMP_LOWER_CBCR, 0x1);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

275

REG_UPDATE(WBSCL_OUTSIDE_PIX_STRATEGY, WBSCL_OUTSIDE_PIX_STRATEGY, DWB_OUTSIDE_PIX_STRATEGY_EDGE);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

310

REG_UPDATE(WBSCL_MODE, WBSCL_COEF_RAM_SEL, !coef_ram_current);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

83

REG_UPDATE(CNV_MODE, CNV_WINDOW_CROP_EN, 1);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

84

REG_UPDATE(CNV_WINDOW_START, CNV_WINDOW_START_X, params->cnv_params.crop_x);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

85

REG_UPDATE(CNV_WINDOW_START, CNV_WINDOW_START_Y, params->cnv_params.crop_y);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

86

REG_UPDATE(CNV_WINDOW_SIZE, CNV_WINDOW_WIDTH, params->cnv_params.crop_width);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

87

REG_UPDATE(CNV_WINDOW_SIZE, CNV_WINDOW_HEIGHT, params->cnv_params.crop_height);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

89

REG_UPDATE(CNV_MODE, CNV_WINDOW_CROP_EN, 0);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

93

REG_UPDATE(CNV_MODE, CNV_FRAME_CAPTURE_RATE, params->capture_rate);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

96

REG_UPDATE(CNV_MODE, CNV_OUT_BPC, params->cnv_params.cnv_out_bpc);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c

754

REG_UPDATE(WBSCL_HORZ_FILTER_SCALE_RATIO, WBSCL_H_SCALE_RATIO, h_ratio_luma);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c

757

REG_UPDATE(WBSCL_TAP_CONTROL, WBSCL_H_NUM_OF_TAPS_Y_RGB, h_taps_luma - 1);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c

758

REG_UPDATE(WBSCL_TAP_CONTROL, WBSCL_H_NUM_OF_TAPS_CBCR, h_taps_chroma - 1);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c

780

REG_UPDATE(WBSCL_HORZ_FILTER_INIT_Y_RGB, WBSCL_H_INIT_INT_Y_RGB, h_init_phase_luma_int);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c

781

REG_UPDATE(WBSCL_HORZ_FILTER_INIT_Y_RGB, WBSCL_H_INIT_FRAC_Y_RGB, h_init_phase_luma_frac);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c

782

REG_UPDATE(WBSCL_HORZ_FILTER_INIT_CBCR, WBSCL_H_INIT_INT_CBCR, h_init_phase_chroma_int);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c

783

REG_UPDATE(WBSCL_HORZ_FILTER_INIT_CBCR, WBSCL_H_INIT_FRAC_CBCR, h_init_phase_chroma_frac);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c

832

REG_UPDATE(WBSCL_VERT_FILTER_SCALE_RATIO, WBSCL_V_SCALE_RATIO, v_ratio_luma);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c

835

REG_UPDATE(WBSCL_TAP_CONTROL, WBSCL_V_NUM_OF_TAPS_Y_RGB, v_taps_luma - 1);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c

836

REG_UPDATE(WBSCL_TAP_CONTROL, WBSCL_V_NUM_OF_TAPS_CBCR, v_taps_chroma - 1);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c

859

REG_UPDATE(WBSCL_VERT_FILTER_INIT_Y_RGB, WBSCL_V_INIT_INT_Y_RGB, v_init_phase_luma_int);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c

860

REG_UPDATE(WBSCL_VERT_FILTER_INIT_Y_RGB, WBSCL_V_INIT_FRAC_Y_RGB, v_init_phase_luma_frac);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c

861

REG_UPDATE(WBSCL_VERT_FILTER_INIT_CBCR, WBSCL_V_INIT_INT_CBCR, v_init_phase_chroma_int);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c

862

REG_UPDATE(WBSCL_VERT_FILTER_INIT_CBCR, WBSCL_V_INIT_FRAC_CBCR, v_init_phase_chroma_frac);

drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c

218

REG_UPDATE(RDPCSTX_PHY_CNTL6,

drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c

227

REG_UPDATE(RDPCSTX_PHY_CNTL6,

drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c

233

REG_UPDATE(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_REF_CLK_EN, 1);

drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c

245

REG_UPDATE(RDPCSTX_PHY_CNTL6,

drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c

249

REG_UPDATE(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_REF_CLK_EN, 0);

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_afmt.c

139

REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, channels);

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_afmt.c

143

REG_UPDATE(AFMT_MEM_PWR, AFMT_MEM_PWR_FORCE, 0);

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_afmt.c

156

REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, !mute);

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_afmt.c

165

REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_afmt.c

177

REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_afmt.c

186

REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_afmt.c

189

REG_UPDATE(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, 0);

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_afmt.c

56

REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_afmt.c

71

REG_UPDATE(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c

100

REG_UPDATE(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_EN, false);

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c

110

REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, MCIF_ADDR(params->luma_address[0]));

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c

111

REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_address[0]));

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c

114

REG_UPDATE(MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, MCIF_ADDR(params->chroma_address[0]));

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c

115

REG_UPDATE(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_address[0]));

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c

118

REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB_BUF_2_ADDR_Y, MCIF_ADDR(params->luma_address[1]));

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c

119

REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_address[1]));

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c

122

REG_UPDATE(MCIF_WB_BUF_2_ADDR_C, MCIF_WB_BUF_2_ADDR_C, MCIF_ADDR(params->chroma_address[1]));

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c

123

REG_UPDATE(MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_address[1]));

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c

126

REG_UPDATE(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB_BUF_3_ADDR_Y, MCIF_ADDR(params->luma_address[2]));

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c

127

REG_UPDATE(MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_address[2]));

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c

130

REG_UPDATE(MCIF_WB_BUF_3_ADDR_C, MCIF_WB_BUF_3_ADDR_C, MCIF_ADDR(params->chroma_address[2]));

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c

131

REG_UPDATE(MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_address[2]));

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c

134

REG_UPDATE(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB_BUF_4_ADDR_Y, MCIF_ADDR(params->luma_address[3]));

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c

135

REG_UPDATE(MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_address[3]));

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c

138

REG_UPDATE(MCIF_WB_BUF_4_ADDR_C, MCIF_WB_BUF_4_ADDR_C, MCIF_ADDR(params->chroma_address[3]));

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c

139

REG_UPDATE(MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_address[3]));

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c

145

REG_UPDATE(MCIF_WB_BUF_LUMA_SIZE, MCIF_WB_BUF_LUMA_SIZE, (params->luma_pitch>>8) * dest_height);

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c

146

REG_UPDATE(MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB_BUF_CHROMA_SIZE, (params->chroma_pitch>>8) * dest_height);

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c

149

REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, 1);

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c

162

REG_UPDATE(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_TIME_PER_PIXEL, params->time_per_pixel);

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c

167

REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK_MASK, 0x0);

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c

169

REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, params->cli_watermark[0]);

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c

170

REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK_MASK, 0x1);

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c

172

REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, params->cli_watermark[1]);

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c

173

REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK_MASK, 0x2);

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c

175

REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, params->cli_watermark[2]);

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c

176

REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK_MASK, 0x3);

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c

178

REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, params->cli_watermark[3]);

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c

182

REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x0);

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c

183

REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK,

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c

186

REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x1);

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c

187

REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK,

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c

190

REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x2);

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c

191

REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK,

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c

194

REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x3);

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c

195

REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK,

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c

199

REG_UPDATE(MCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI,

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c

203

REG_UPDATE(MULTI_LEVEL_QOS_CTRL, MAX_SCALED_TIME_TO_URGENT, params->max_scaled_time);

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c

206

REG_UPDATE(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_SLICE_SIZE, params->slice_lines-1);

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c

211

REG_UPDATE(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_CLIENT_ARBITRATION_SLICE, params->arbitration_slice);

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c

97

REG_UPDATE(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_SW_INT_ACK, 1);

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_vpg.c

113

REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_vpg.c

117

REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_vpg.c

121

REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_vpg.c

125

REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_vpg.c

129

REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_vpg.c

133

REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_vpg.c

137

REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_vpg.c

141

REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_vpg.c

145

REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_vpg.c

149

REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_vpg.c

153

REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_vpg.c

157

REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_vpg.c

161

REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_vpg.c

165

REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_vpg.c

169

REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_vpg.c

178

REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_vpg.c

182

REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_vpg.c

186

REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_vpg.c

190

REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_vpg.c

194

REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_vpg.c

198

REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_vpg.c

202

REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_vpg.c

206

REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_vpg.c

210

REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_vpg.c

214

REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_vpg.c

218

REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_vpg.c

222

REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_vpg.c

226

REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_vpg.c

230

REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_vpg.c

234

REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_vpg.c

79

REG_UPDATE(VPG_GENERIC_STATUS, VPG_GENERIC_CONFLICT_CLR, 1);

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_vpg.c

82

REG_UPDATE(VPG_GENERIC_PACKET_ACCESS_CTRL,

drivers/gpu/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c

116

REG_UPDATE(PWRSEQ_REF_DIV,

drivers/gpu/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c

139

REG_UPDATE(BL_PWM_CNTL, BL_PWM_EN, 1);

drivers/gpu/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c

142

REG_UPDATE(BL_PWM_GRP1_REG_LOCK,

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_apg.c

53

REG_UPDATE(APG_CONTROL, APG_RESET, 1);

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_apg.c

57

REG_UPDATE(APG_CONTROL, APG_RESET, 0);

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_apg.c

63

REG_UPDATE(APG_CONTROL2, APG_ENABLE, 1);

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_apg.c

72

REG_UPDATE(APG_CONTROL2, APG_ENABLE, 0);

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_apg.c

88

REG_UPDATE(APG_CONTROL2, APG_DP_AUDIO_STREAM_ID, 0);

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_apg.c

92

REG_UPDATE(APG_DBG_GEN_CONTROL, APG_DBG_AUDIO_CHANNEL_ENABLE, 0xFF);

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_apg.c

95

REG_UPDATE(APG_MEM_PWR, APG_MEM_PWR_FORCE, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_dio.c

27

REG_UPDATE(DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

115

REG_UPDATE(DP_DPHY_CNTL, DPHY_BYPASS, enable);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

1322

REG_UPDATE(DP_MSE_SAT_UPDATE,

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

136

REG_UPDATE(DP_DPHY_PRBS_CNTL, DPHY_PRBS_EN, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

1370

REG_UPDATE(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, field);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

205

REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, complete);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

378

REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

382

REG_UPDATE(DP_DPHY_HBR2_PATTERN_CONTROL,

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

392

REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

413

REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0x1FF);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

498

REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_ADVANCE, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

507

REG_UPDATE(DP_DPHY_FAST_TRAINING,

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

510

REG_UPDATE(DP_DPHY_FAST_TRAINING,

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

521

REG_UPDATE(DP_DPHY_BS_SR_SWAP_CNTL, DPHY_LOAD_BS_COUNT, 0x5);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

551

REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

563

REG_UPDATE(DIG_BE_CNTL, DIG_HPD_SELECT, hpd_source);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

899

REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

903

REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

908

REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 2);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

912

REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 3);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

916

REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 5);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

976

REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

1006

REG_UPDATE(DIG_FE_CNTL, DIG_START, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

1010

REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

1025

REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

1038

REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, value);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

122

REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

1244

REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, channels);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

1256

REG_UPDATE(HDMI_AUDIO_PACKET_CONTROL,

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

126

REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

1260

REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

1285

REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

1288

REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

1291

REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

1294

REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

1297

REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

130

REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

1300

REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

1316

REG_UPDATE(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

134

REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

1350

REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

1359

REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

1362

REG_UPDATE(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

1374

REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, !!enable);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

138

REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

1393

REG_UPDATE(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

1401

REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

142

REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

1423

REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

1433

REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, !mute);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

146

REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

1485

REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

1486

REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

1495

REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

150

REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

470

REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

473

REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

476

REG_UPDATE(DIG_FE_CNTL, TMDS_COLOR_FORMAT, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

514

REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

586

REG_UPDATE(HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

589

REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

591

REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

593

REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE,

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

596

REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

664

REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

68

REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

764

REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

765

REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

766

REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

767

REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP5_ENABLE, info_frame->adaptive_sync.valid);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

778

REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

799

REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP4_SEND, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

802

REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP4_SEND_ANY_LINE, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

805

REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

815

REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

818

REG_UPDATE(AFMT_VBI_PACKET_CONTROL,

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

857

REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

861

REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP4_SEND, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

87

REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

872

REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

899

REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

90

REG_UPDATE(AFMT_VBI_PACKET_CONTROL,

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

925

REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

933

REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

952

REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, true);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

989

REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

995

REG_UPDATE(DP_VID_N, DP_VID_N, n_vid);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

997

REG_UPDATE(DP_VID_M, DP_VID_M, m_vid);

drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c

178

REG_UPDATE(DP_DPHY_CNTL, DPHY_FEC_EN, enable);

drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c

185

REG_UPDATE(DP_DPHY_CNTL, DPHY_FEC_READY_SHADOW, ready);

drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c

353

REG_UPDATE(TMDS_CTL_BITS, TMDS_CTL0, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

105

REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL2,

drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

112

REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL3,

drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

119

REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL3,

drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

126

REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL4,

drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

133

REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL4,

drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

152

REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

228

REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP7_PPS, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

231

REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

243

REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

246

REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_INDEX, 7);

drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

258

REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_INDEX, packet_index);

drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

324

REG_UPDATE(DP_SEC_CNTL6,

drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

342

REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

343

REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP7_PPS, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

404

REG_UPDATE(DIG_FE_CNTL,

drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

408

REG_UPDATE(DME_CONTROL,

drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

411

REG_UPDATE(DME_CONTROL,

drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

415

REG_UPDATE(DP_SEC_METADATA_TRANSMISSION,

drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

418

REG_UPDATE(HDMI_METADATA_PACKET_CONTROL,

drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

420

REG_UPDATE(DIG_FE_CNTL,

drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

435

REG_UPDATE(DP_SEC_CNTL1, DP_SEC_GSP5_LINE_REFERENCE, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

437

REG_UPDATE(DP_SEC_CNTL5, DP_SEC_GSP5_LINE_NUM,

drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

456

REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

499

REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

505

REG_UPDATE(DP_VID_N, DP_VID_N, n_vid);

drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

507

REG_UPDATE(DP_VID_M, DP_VID_M, m_vid);

drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

515

REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, false);

drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

519

REG_UPDATE(DIG_FE_CNTL, DIG_START, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

524

REG_UPDATE(DIG_FE_CNTL, DIG_START, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

529

REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

532

REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

547

REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);

drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

559

REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_COMBINE, odm_combine);

drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

577

REG_UPDATE(DP_SEC_FRAMING4,

drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

84

REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL1,

drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

91

REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL1,

drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

98

REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL2,

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c

257

REG_UPDATE(TMDS_CTL_BITS, TMDS_CTL0, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

106

REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL2,

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

113

REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL3,

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

120

REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL3,

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

127

REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL4,

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

134

REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL4,

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

141

REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL7,

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

148

REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL7,

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

155

REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL8,

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

162

REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL8,

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

169

REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL9,

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

176

REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL9,

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

183

REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL10,

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

202

REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

203

REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

294

REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL10,

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

331

REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP11_PPS, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

338

REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

359

REG_UPDATE(DP_GSP11_CNTL,

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

372

REG_UPDATE(DP_GSP11_CNTL,

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

374

REG_UPDATE(DP_SEC_CNTL,

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

378

REG_UPDATE(DP_GSP11_CNTL, DP_SEC_GSP11_ENABLE, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

379

REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP11_PPS, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

414

REG_UPDATE(DP_SEC_CNTL1, DP_SEC_GSP5_LINE_REFERENCE, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

416

REG_UPDATE(DP_SEC_CNTL5, DP_SEC_GSP5_LINE_NUM,

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

494

REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid);

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

495

REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid);

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

496

REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid);

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

497

REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP5_ENABLE, info_frame->adaptive_sync.valid);

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

508

REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

515

REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

524

REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_COMBINE, odm_combine);

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

553

REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F);

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

560

REG_UPDATE(DIG_FE_CNTL, DIG_START, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

564

REG_UPDATE(DIG_FE_CNTL, DIG_START, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

599

REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F);

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

606

REG_UPDATE(DIG_FE_CNTL, DIG_START, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

610

REG_UPDATE(DIG_FE_CNTL, DIG_START, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

629

REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

692

REG_UPDATE(HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

696

REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

703

REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE,

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

707

REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

770

REG_UPDATE(HDMI_AUDIO_PACKET_CONTROL,

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

791

REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz);

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

794

REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz);

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

797

REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz);

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

800

REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz);

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

803

REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz);

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

806

REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz);

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

85

REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL1,

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

92

REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL1,

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

99

REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL2,

drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

144

REG_UPDATE(DIO_LINKA_CNTL,

drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

147

REG_UPDATE(DIO_LINKA_CNTL,

drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

149

REG_UPDATE(DIO_LINKA_CNTL,

drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

154

REG_UPDATE(DIO_LINKB_CNTL,

drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

157

REG_UPDATE(DIO_LINKB_CNTL,

drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

159

REG_UPDATE(DIO_LINKB_CNTL,

drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

164

REG_UPDATE(DIO_LINKC_CNTL,

drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

167

REG_UPDATE(DIO_LINKC_CNTL,

drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

169

REG_UPDATE(DIO_LINKC_CNTL,

drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

174

REG_UPDATE(DIO_LINKD_CNTL,

drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

177

REG_UPDATE(DIO_LINKD_CNTL,

drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

179

REG_UPDATE(DIO_LINKD_CNTL,

drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

184

REG_UPDATE(DIO_LINKE_CNTL,

drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

187

REG_UPDATE(DIO_LINKE_CNTL,

drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

189

REG_UPDATE(DIO_LINKE_CNTL,

drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

194

REG_UPDATE(DIO_LINKF_CNTL,

drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

197

REG_UPDATE(DIO_LINKF_CNTL,

drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

199

REG_UPDATE(DIO_LINKF_CNTL,

drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

244

REG_UPDATE(TMDS_CTL_BITS, TMDS_CTL0, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

450

REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

101

REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_PER_CYCLE_PROCESSING_MODE, odm_combine);

drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

130

REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F);

drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

170

REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F);

drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

194

REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

257

REG_UPDATE(HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

261

REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

268

REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE,

drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

272

REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

330

REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

336

REG_UPDATE(DP_VID_N, DP_VID_N, n_vid);

drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

338

REG_UPDATE(DP_VID_M, DP_VID_M, m_vid);

drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

344

REG_UPDATE(DP_PIXEL_FORMAT,

drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

350

REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, false);

drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

358

REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

361

REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

376

REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);

drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

399

REG_UPDATE(DP_DSC_CNTL, DP_DSC_MODE, dsc_mode == OPTC_DSC_DISABLED ? 0 : 1);

drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

428

REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_MODE, pix_per_container == 2 ? 0x1 : 0x0);

drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

58

REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, reset_val);

drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

71

REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_READ_START_LEVEL, 0x7);

drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

76

REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

83

REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c

136

REG_UPDATE(TMDS_CTL_BITS, TMDS_CTL0, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

128

REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F);

drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

152

REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

215

REG_UPDATE(HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

219

REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

226

REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE,

drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

230

REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

278

REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

284

REG_UPDATE(DP_VID_N, DP_VID_N, n_vid);

drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

286

REG_UPDATE(DP_VID_M, DP_VID_M, m_vid);

drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

292

REG_UPDATE(DP_PIXEL_FORMAT,

drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

298

REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, false);

drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

306

REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

309

REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

319

REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_READ_START_LEVEL, 0x7);

drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

321

REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

325

REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

329

REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

344

REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);

drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

361

REG_UPDATE(DP_DSC_CNTL, DP_DSC_MODE, dsc_mode == OPTC_DSC_DISABLED ? 0 : 1);

drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

391

REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_MODE, pix_per_container == 2 ? 0x1 : 0x0);

drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

400

REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, reset_val);

drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

413

REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_READ_START_LEVEL, 0x7);

drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

418

REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

59

REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_PER_CYCLE_PROCESSING_MODE, two_pixel_per_cyle ? 1 : 0);

drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

88

REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F);

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c

101

REG_UPDATE(DIG_BE_CLK_CNTL, DIG_BE_MODE, 2);

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c

105

REG_UPDATE(DIG_BE_CLK_CNTL, DIG_BE_MODE, 3);

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c

109

REG_UPDATE(DIG_BE_CLK_CNTL, DIG_BE_MODE, 5);

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c

116

REG_UPDATE(DIG_BE_CLK_CNTL, DIG_BE_CLK_EN, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c

129

REG_UPDATE(DIO_CLK_CNTL, DIO_FGCG_REP_DIS, !enable);

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c

299

REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c

96

REG_UPDATE(DIG_BE_CLK_CNTL, DIG_BE_MODE, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

115

REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F);

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

140

REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

203

REG_UPDATE(HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

207

REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

214

REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE,

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

218

REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

221

REG_UPDATE(HDMI_CONTROL, TMDS_PIXEL_ENCODING, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

224

REG_UPDATE(HDMI_CONTROL, TMDS_PIXEL_ENCODING, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

227

REG_UPDATE(HDMI_CONTROL, TMDS_COLOR_FORMAT, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

244

REG_UPDATE(DIG_FE_CLK_CNTL, DIG_FE_MODE, 2);

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

248

REG_UPDATE(DIG_FE_CLK_CNTL, DIG_FE_MODE, 3);

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

252

REG_UPDATE(DIG_FE_CLK_CNTL, DIG_FE_MODE, 5);

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

258

REG_UPDATE(DIG_FE_CLK_CNTL, DIG_FE_MODE, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

310

REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

316

REG_UPDATE(DP_VID_N, DP_VID_N, n_vid);

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

318

REG_UPDATE(DP_VID_M, DP_VID_M, m_vid);

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

324

REG_UPDATE(DP_PIXEL_FORMAT,

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

330

REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, false);

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

338

REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

341

REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

356

REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

375

REG_UPDATE(STREAM_MAPPER_CONTROL,

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

385

REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, reset_val);

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

406

REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

407

REG_UPDATE(DIG_FE_EN_CNTL, DIG_FE_ENABLE, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

408

REG_UPDATE(DIG_FE_CLK_CNTL, DIG_FE_CLK_EN, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

415

REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_READ_START_LEVEL, 0x7);

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

416

REG_UPDATE(DIG_FE_CLK_CNTL, DIG_FE_CLK_EN, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

417

REG_UPDATE(DIG_FE_EN_CNTL, DIG_FE_ENABLE, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

422

REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

76

REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F);

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c

106

REG_UPDATE(TMDS_CTL_BITS, TMDS_CTL0, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c

133

REG_UPDATE(DIG_BE_CLK_CNTL, DIG_BE_MODE, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c

138

REG_UPDATE(DIG_BE_CLK_CNTL, DIG_BE_MODE, 2);

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c

142

REG_UPDATE(DIG_BE_CLK_CNTL, DIG_BE_MODE, 3);

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c

146

REG_UPDATE(DIG_BE_CLK_CNTL, DIG_BE_MODE, 5);

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c

153

REG_UPDATE(DIG_BE_CLK_CNTL, DIG_BE_CLK_EN, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c

154

REG_UPDATE(DIG_BE_EN_CNTL, DIG_BE_ENABLE, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

128

REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F);

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

152

REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

215

REG_UPDATE(HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

218

REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

225

REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE,

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

229

REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

240

REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE, 0x1);

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

243

REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE, 0x2);

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

246

REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE, 0x3);

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

249

REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE, 0x0);

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

293

REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

299

REG_UPDATE(DP_VID_N, DP_VID_N, n_vid);

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

301

REG_UPDATE(DP_VID_M, DP_VID_M, m_vid);

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

306

REG_UPDATE(DP_VID_TIMING, DP_VID_N_INTERVAL, 0x1);

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

309

REG_UPDATE(DP_VID_TIMING, DP_VID_N_INTERVAL, 0x2);

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

312

REG_UPDATE(DP_VID_TIMING, DP_VID_N_INTERVAL, 0x3);

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

315

REG_UPDATE(DP_VID_TIMING, DP_VID_N_INTERVAL, 0x0);

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

319

REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

323

REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, false);

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

331

REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

334

REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

336

REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_ENABLE, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

346

REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_READ_START_LEVEL, 0x7);

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

348

REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

352

REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

356

REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

371

REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

408

REG_UPDATE(DIG_FE_CLK_CNTL, DIG_FE_MODE, 2);

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

412

REG_UPDATE(DIG_FE_CLK_CNTL, DIG_FE_MODE, 3);

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

416

REG_UPDATE(DIG_FE_CLK_CNTL, DIG_FE_MODE, 5);

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

422

REG_UPDATE(DIG_FE_CLK_CNTL, DIG_FE_MODE, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

429

REG_UPDATE(DIG_FE_CLK_CNTL, DIG_FE_CLK_EN, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

430

REG_UPDATE(DIG_FE_EN_CNTL, DIG_FE_ENABLE, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

432

REG_UPDATE(DIG_FE_EN_CNTL, DIG_FE_ENABLE, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

433

REG_UPDATE(DIG_FE_CLK_CNTL, DIG_FE_CLK_EN, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

704

REG_UPDATE(DP_SEC_FRAMING4,

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

715

REG_UPDATE(STREAM_MAPPER_CONTROL,

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

822

REG_UPDATE(HDMI_CONTROL,

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

826

REG_UPDATE(DME_CONTROL,

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

829

REG_UPDATE(DME_CONTROL,

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

833

REG_UPDATE(DP_SEC_METADATA_TRANSMISSION,

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

836

REG_UPDATE(HDMI_METADATA_PACKET_CONTROL,

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

838

REG_UPDATE(HDMI_CONTROL,

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

849

REG_UPDATE(HDMI_CONTROL, TMDS_PIXEL_ENCODING, 1);

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

852

REG_UPDATE(HDMI_CONTROL, TMDS_PIXEL_ENCODING, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

855

REG_UPDATE(HDMI_CONTROL, TMDS_COLOR_FORMAT, 0);

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

88

REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

271

REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 3);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

272

REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, 1);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

274

REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 2);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

275

REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, 0);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

387

REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

408

REG_UPDATE(CURSOR_CONTROL,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

410

REG_UPDATE(CURSOR0_CONTROL,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

428

REG_UPDATE(CURSOR0_COLOR0,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

430

REG_UPDATE(CURSOR0_COLOR1,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

490

REG_UPDATE(CURSOR0_CONTROL, CUR0_ENABLE, cur_en);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

505

REG_UPDATE(CURSOR0_FP_SCALE_BIAS, CUR0_FP_BIAS, attr->bias);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

506

REG_UPDATE(CURSOR0_FP_SCALE_BIAS, CUR0_FP_SCALE, attr->scale);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

527

REG_UPDATE(DPP_CONTROL, DPP_CLOCK_ENABLE, 1);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

529

REG_UPDATE(DPP_CONTROL, DPP_CLOCK_ENABLE, 0);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

537

REG_UPDATE(CURSOR0_CONTROL, CUR0_ENABLE, 0);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

425

REG_UPDATE(CM_RGAM_LUT_WRITE_EN_MASK,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

427

REG_UPDATE(CM_RGAM_LUT_WRITE_EN_MASK,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

658

REG_UPDATE(CM_CMOUT_CONTROL, CM_CMOUT_ROUND_TRUNC_MODE, 8);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

659

REG_UPDATE(CM_CONTROL, CM_BYPASS_EN, 0);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

672

REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 0);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

675

REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 1);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

678

REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 2);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

681

REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 3);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

696

REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 3);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

698

REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 4);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

732

REG_UPDATE(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_HOST_EN, 0);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

733

REG_UPDATE(CM_DGAM_LUT_WRITE_EN_MASK,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

735

REG_UPDATE(CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_LUT_WRITE_SEL,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

840

REG_UPDATE(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_SEL, 0);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

842

REG_UPDATE(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_SEL, 1);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

844

REG_UPDATE(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_RW_MODE, 0);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

846

REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 0);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

848

REG_UPDATE(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_WRITE_EN_MASK, 7);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

856

REG_UPDATE(CM_IGAM_LUT_RW_INDEX, CM_IGAM_LUT_RW_INDEX, 0);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

871

REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, rama_occupied ? 3 : 2);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

881

REG_UPDATE(CM_HDR_MULT_COEF, CM_HDR_MULT_COEF, multiplier);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

165

REG_UPDATE(DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_FORCE, 0);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

172

REG_UPDATE(DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_FORCE, 3);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

656

REG_UPDATE(SCL_MODE, DSCL_MODE, dscl_mode);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

124

REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

125

REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

126

REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

127

REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

221

REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

222

REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

223

REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT2, alpha_2bit_lut->lut2);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

224

REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT3, alpha_2bit_lut->lut3);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

229

REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

249

REG_UPDATE(CURSOR_CONTROL,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

251

REG_UPDATE(CURSOR0_CONTROL,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

322

REG_UPDATE(COLOR_KEYER_CONTROL, COLOR_KEYER_EN, color_keyer->color_keyer_en);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

324

REG_UPDATE(COLOR_KEYER_CONTROL, COLOR_KEYER_MODE, color_keyer->color_keyer_mode);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

326

REG_UPDATE(COLOR_KEYER_ALPHA, COLOR_KEYER_ALPHA_LOW, color_keyer->color_keyer_alpha_low);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

327

REG_UPDATE(COLOR_KEYER_ALPHA, COLOR_KEYER_ALPHA_HIGH, color_keyer->color_keyer_alpha_high);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

329

REG_UPDATE(COLOR_KEYER_RED, COLOR_KEYER_RED_LOW, color_keyer->color_keyer_red_low);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

330

REG_UPDATE(COLOR_KEYER_RED, COLOR_KEYER_RED_HIGH, color_keyer->color_keyer_red_high);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

332

REG_UPDATE(COLOR_KEYER_GREEN, COLOR_KEYER_GREEN_LOW, color_keyer->color_keyer_green_low);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

333

REG_UPDATE(COLOR_KEYER_GREEN, COLOR_KEYER_GREEN_HIGH, color_keyer->color_keyer_green_high);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

335

REG_UPDATE(COLOR_KEYER_BLUE, COLOR_KEYER_BLUE_LOW, color_keyer->color_keyer_blue_low);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

336

REG_UPDATE(COLOR_KEYER_BLUE, COLOR_KEYER_BLUE_HIGH, color_keyer->color_keyer_blue_high);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

361

REG_UPDATE(CURSOR0_COLOR0,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

363

REG_UPDATE(CURSOR0_COLOR1,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

83

REG_UPDATE(CM_MEM_PWR_CTRL, SHARED_MEM_PWR_DIS, power_on == true ? 1:0);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

85

REG_UPDATE(OBUF_MEM_PWR_CTRL,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

88

REG_UPDATE(DSCL_MEM_PWR_CTRL,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

1110

REG_UPDATE(CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_WRITE_EN_MASK,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

1201

REG_UPDATE(CM_HDR_MULT_COEF, CM_HDR_MULT_COEF, multiplier);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

144

REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 0);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

147

REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 1);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

150

REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 2);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

153

REG_UPDATE(CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, 3);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

382

REG_UPDATE(CM_BLNDGAM_LUT_WRITE_EN_MASK,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

384

REG_UPDATE(CM_BLNDGAM_LUT_WRITE_EN_MASK,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

60

REG_UPDATE(CM_CONTROL, CM_BYPASS, cm_bypass_mode);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

621

REG_UPDATE(CM_SHAPER_LUT_WRITE_EN_MASK,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

623

REG_UPDATE(CM_SHAPER_LUT_WRITE_EN_MASK,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

94

REG_UPDATE(CM_DGAM_LUT_WRITE_EN_MASK,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

96

REG_UPDATE(CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_LUT_WRITE_SEL,

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

167

REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0);

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

168

REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1);

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

169

REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT2, alpha_2bit_lut->lut2);

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

170

REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT3, alpha_2bit_lut->lut3);

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

175

REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en);

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

180

REG_UPDATE(CURSOR_CONTROL,

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

182

REG_UPDATE(CURSOR0_CONTROL,

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

71

REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0);

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

72

REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0);

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

73

REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0);

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

74

REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1397

REG_UPDATE(CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_WRITE_EN_MASK,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

245

REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

246

REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

247

REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

248

REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

250

REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_R, 0);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

251

REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_G, 1);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

252

REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_B, 2);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

354

REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

355

REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

356

REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT2, alpha_2bit_lut->lut2);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

357

REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT3, alpha_2bit_lut->lut3);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

363

REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

391

REG_UPDATE(CURSOR_CONTROL,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

393

REG_UPDATE(CURSOR0_CONTROL,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

425

REG_UPDATE(CURSOR0_COLOR0,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

427

REG_UPDATE(CURSOR0_COLOR1,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

546

REG_UPDATE(DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_FORCE, 3);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

553

REG_UPDATE(CM_MEM_PWR_CTRL, GAMCOR_MEM_PWR_FORCE, 3);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

562

REG_UPDATE(CM_MEM_PWR_CTRL, BLNDGAM_MEM_PWR_FORCE, 3);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

571

REG_UPDATE(CM_MEM_PWR_CTRL2, HDR3DLUT_MEM_PWR_FORCE, 3);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

580

REG_UPDATE(CM_MEM_PWR_CTRL2, SHAPER_MEM_PWR_FORCE, 3);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

595

REG_UPDATE(CM_MEM_PWR_CTRL, BLNDGAM_MEM_PWR_FORCE, 0);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

612

REG_UPDATE(CM_MEM_PWR_CTRL2, HDR3DLUT_MEM_PWR_FORCE, 0);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

629

REG_UPDATE(CM_MEM_PWR_CTRL2, SHAPER_MEM_PWR_FORCE, 0);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

668

REG_UPDATE(CM_BLNDGAM_LUT_CONTROL, CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 4);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

674

REG_UPDATE(CM_BLNDGAM_LUT_CONTROL, CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 2);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

680

REG_UPDATE(CM_BLNDGAM_LUT_CONTROL, CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 1);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

903

REG_UPDATE(CM_SHAPER_LUT_WRITE_EN_MASK,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

905

REG_UPDATE(CM_SHAPER_LUT_WRITE_EN_MASK,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

108

REG_UPDATE(CM_GAMCOR_LUT_CONTROL,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

117

REG_UPDATE(CM_GAMCOR_LUT_CONTROL,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

134

REG_UPDATE(CM_MEM_PWR_CTRL, GAMCOR_MEM_PWR_FORCE, 0);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

207

REG_UPDATE(CM_GAMCOR_LUT_CONTROL,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

209

REG_UPDATE(CM_GAMCOR_LUT_CONTROL,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

299

REG_UPDATE(CM_GAMCOR_CONTROL, CM_GAMCOR_SELECT, next_mode == LUT_RAM_A ? 0:1);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

310

REG_UPDATE(CM_HDR_MULT_COEF, CM_HDR_MULT_COEF, multiplier);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

54

REG_UPDATE(CM_CONTROL, CM_BYPASS, cm_bypass_mode);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

99

REG_UPDATE(CM_GAMCOR_LUT_CONTROL,

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

149

REG_UPDATE(DPP_CONTROL, DPP_FGCG_REP_DIS, !enable);

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

58

REG_UPDATE(DPP_CONTROL,

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

66

REG_UPDATE(DPP_CONTROL,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

184

REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

185

REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

186

REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT2, alpha_2bit_lut->lut2);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

187

REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT3, alpha_2bit_lut->lut3);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

193

REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

79

REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

80

REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

81

REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

82

REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

84

REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_R, 0);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

85

REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_G, 1);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

86

REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_B, 2);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

116

REG_UPDATE(CURSOR0_COLOR0,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

118

REG_UPDATE(CURSOR0_COLOR1,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

140

REG_UPDATE(CURSOR0_CONTROL, CUR0_ENABLE, cur_en);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

155

REG_UPDATE(CURSOR0_FP_SCALE_BIAS_G_Y, CUR0_FP_BIAS_G_Y, attr->bias);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

156

REG_UPDATE(CURSOR0_FP_SCALE_BIAS_G_Y, CUR0_FP_SCALE_G_Y, attr->scale);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

157

REG_UPDATE(CURSOR0_FP_SCALE_BIAS_RB_CRCB, CUR0_FP_BIAS_RB_CRCB, attr->bias);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

158

REG_UPDATE(CURSOR0_FP_SCALE_BIAS_RB_CRCB, CUR0_FP_SCALE_RB_CRCB, attr->scale);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1126

REG_UPDATE(SCL_MODE, DSCL_MODE, dscl_mode);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

157

REG_UPDATE(DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_FORCE, 0);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

164

REG_UPDATE(DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_FORCE, 3);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

913

REG_UPDATE(DSCL_EASF_V_MODE,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

916

REG_UPDATE(DSCL_EASF_H_MODE,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

928

REG_UPDATE(ISHARP_DELTA_CTRL,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

243

REG_UPDATE(DSC_TOP_CONTROL,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

264

REG_UPDATE(DSCRM_DSC_FORWARD_CONFIG,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

267

REG_UPDATE(DSC_TOP_CONTROL,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

284

REG_UPDATE(DSCRM_DSC_FORWARD_CONFIG,

drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c

103

REG_UPDATE(DSC_TOP_CONTROL,

drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c

113

REG_UPDATE(DSC_TOP_CONTROL, DSC_FGCG_REP_DIS, !enable);

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

155

REG_UPDATE(DSC_TOP_CONTROL,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

176

REG_UPDATE(DSCRM_DSC_FORWARD_CONFIG,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

179

REG_UPDATE(DSC_TOP_CONTROL,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

196

REG_UPDATE(DSCRM_DSC_FORWARD_CONFIG,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

393

REG_UPDATE(DSC_TOP_CONTROL, DSC_FGCG_REP_DIS, !enable);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

111

REG_UPDATE(FC_MODE_CTRL, FC_FRAME_CAPTURE_EN, DWB_FRAME_CAPTURE_ENABLE);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

114

REG_UPDATE(FC_FLOW_CTRL, FC_FIRST_PIXEL_DELAY_COUNT, 96);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

124

REG_UPDATE(FC_MODE_CTRL, FC_FRAME_CAPTURE_EN, DWB_FRAME_CAPTURE_DISABLE);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

127

REG_UPDATE(DWB_ENABLE_CLK_CTRL, DWB_ENABLE, 0);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

142

REG_UPDATE(DWB_UPDATE_CTRL, DWB_UPDATE_LOCK, 1);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

145

REG_UPDATE(FC_MODE_CTRL, FC_FRAME_CAPTURE_EN, enable);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

149

REG_UPDATE(DWB_UPDATE_CTRL, DWB_UPDATE_LOCK, 0);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

171

REG_UPDATE(DWB_UPDATE_CTRL, DWB_UPDATE_LOCK, 1);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

187

REG_UPDATE(DWB_UPDATE_CTRL, DWB_UPDATE_LOCK, 0);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

211

REG_UPDATE(FC_MODE_CTRL, FC_EYE_SELECTION, stereo_params->stereo_eye_select);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

212

REG_UPDATE(FC_MODE_CTRL, FC_STEREO_EYE_POLARITY, stereo_params->stereo_polarity);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

215

REG_UPDATE(FC_MODE_CTRL, FC_EYE_SELECTION, 0);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

225

REG_UPDATE(FC_MODE_CTRL, FC_NEW_CONTENT, is_new_content);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

233

REG_UPDATE(DWB_OUT_CTRL, OUT_FORMAT, params->cnv_params.fc_out_format);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

238

REG_UPDATE(DWB_OUT_CTRL, OUT_DENORM, params->cnv_params.out_denorm_mode);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

239

REG_UPDATE(DWB_OUT_CTRL, OUT_MAX, params->cnv_params.out_max_pix_val);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

240

REG_UPDATE(DWB_OUT_CTRL, OUT_MIN, params->cnv_params.out_min_pix_val);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

76

REG_UPDATE(FC_MODE_CTRL, FC_WINDOW_CROP_EN, 1);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

77

REG_UPDATE(FC_WINDOW_START, FC_WINDOW_START_X, params->cnv_params.crop_x);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

78

REG_UPDATE(FC_WINDOW_START, FC_WINDOW_START_Y, params->cnv_params.crop_y);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

79

REG_UPDATE(FC_WINDOW_SIZE, FC_WINDOW_WIDTH, params->cnv_params.crop_width);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

80

REG_UPDATE(FC_WINDOW_SIZE, FC_WINDOW_HEIGHT, params->cnv_params.crop_height);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

82

REG_UPDATE(FC_MODE_CTRL, FC_WINDOW_CROP_EN, 0);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

86

REG_UPDATE(FC_MODE_CTRL, FC_FRAME_CAPTURE_RATE, params->capture_rate);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

97

REG_UPDATE(DWB_ENABLE_CLK_CTRL, DWB_ENABLE, 1);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

204

REG_UPDATE(DWB_OGAM_LUT_CONTROL,

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

214

REG_UPDATE(DWB_OGAM_LUT_CONTROL,

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

224

REG_UPDATE(DWB_OGAM_LUT_CONTROL,

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

267

REG_UPDATE(DWB_OGAM_CONTROL, DWB_OGAM_SELECT, next_mode == LUT_RAM_A ? 0 : 1);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

316

REG_UPDATE(DWB_GAMUT_REMAP_COEF_FORMAT, DWB_GAMUT_REMAP_COEF_FORMAT, coef_format);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

394

REG_UPDATE(DWB_HDR_MULT_COEF, DWB_HDR_MULT_COEF, params->hdr_mult);

drivers/gpu/drm/amd/display/dc/dwb/dcn35/dcn35_dwb.c

56

REG_UPDATE(DWB_ENABLE_CLK_CTRL, DWB_FGCG_REP_DIS, !enable);

drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c

148

REG_UPDATE(gpio.MASK_reg,

drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c

153

REG_UPDATE(dc_gpio_aux_ctrl_5, DDC_PAD_I2CMODE, 1);

drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c

157

REG_UPDATE(phy_aux_cntl, AUX_PAD_RXSEL, 1);

drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c

167

REG_UPDATE(dc_gpio_aux_ctrl_5,

drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c

107

REG_UPDATE(A_reg, A, value);

drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c

114

REG_UPDATE(EN_reg, EN, ~value);

drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c

151

REG_UPDATE(EN_reg, EN, 0);

drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c

152

REG_UPDATE(MASK_reg, MASK, 1);

drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c

157

REG_UPDATE(A_reg, A, 0);

drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c

158

REG_UPDATE(MASK_reg, MASK, 1);

drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c

163

REG_UPDATE(A_reg, A, 0);

drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c

164

REG_UPDATE(MASK_reg, MASK, 1);

drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c

168

REG_UPDATE(MASK_reg, MASK, 0);

drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c

172

REG_UPDATE(MASK_reg, MASK, 0);

drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c

54

REG_UPDATE(MASK_reg, MASK, gpio->store.mask);

drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c

55

REG_UPDATE(A_reg, A, gpio->store.a);

drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c

56

REG_UPDATE(EN_reg, EN, gpio->store.en);

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

102

REG_UPDATE(DP_DPHY_SYM32_CONTROL,

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

106

REG_UPDATE(DP_DPHY_SYM32_CONTROL,

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

115

REG_UPDATE(DP_DPHY_SYM32_CONTROL,

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

124

REG_UPDATE(DP_DPHY_SYM32_CONTROL,

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

138

REG_UPDATE(DP_DPHY_SYM32_CONTROL,

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

152

REG_UPDATE(DP_DPHY_SYM32_CONTROL,

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

166

REG_UPDATE(DP_DPHY_SYM32_CONTROL,

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

180

REG_UPDATE(DP_DPHY_SYM32_CONTROL,

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

194

REG_UPDATE(DP_DPHY_SYM32_CONTROL,

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

208

REG_UPDATE(DP_DPHY_SYM32_CONTROL,

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

241

REG_UPDATE(DP_DPHY_SYM32_CONTROL,

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

257

REG_UPDATE(DP_DPHY_SYM32_CONTROL,

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

367

REG_UPDATE(DP_DPHY_SYM32_SAT_UPDATE,

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

61

REG_UPDATE(DP_LINK_ENC_CLOCK_CONTROL, DP_LINK_ENC_CLOCK_EN, 1);

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

65

REG_UPDATE(DP_DPHY_SYM32_CONTROL, DPHY_RESET, 1);

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

66

REG_UPDATE(DP_DPHY_SYM32_CONTROL, DPHY_RESET, 0);

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

82

REG_UPDATE(DP_DPHY_SYM32_CONTROL,

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

86

REG_UPDATE(DP_LINK_ENC_CLOCK_CONTROL, DP_LINK_ENC_CLOCK_EN, 0);

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

98

REG_UPDATE(DP_DPHY_SYM32_CONTROL,

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

101

REG_UPDATE(DP_SYM32_ENC_VID_STREAM_CONTROL,

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

105

REG_UPDATE(DP_SYM32_ENC_VID_FIFO_CONTROL,

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

110

REG_UPDATE(DP_SYM32_ENC_VID_FIFO_CONTROL,

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

115

REG_UPDATE(DP_SYM32_ENC_VID_FIFO_CONTROL,

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

119

REG_UPDATE(DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0,

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

124

REG_UPDATE(DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0,

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

135

REG_UPDATE(DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0,

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

145

REG_UPDATE(DP_SYM32_ENC_VID_STREAM_CONTROL,

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

158

REG_UPDATE(DP_SYM32_ENC_SDP_CONTROL,

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

162

REG_UPDATE(DP_SYM32_ENC_VID_FIFO_CONTROL,

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

166

REG_UPDATE(DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0,

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

176

REG_UPDATE(DP_SYM32_ENC_CONTROL,

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

180

REG_UPDATE(DP_STREAM_ENC_CLOCK_CONTROL,

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

224

REG_UPDATE(DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL,

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

226

REG_UPDATE(DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL,

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

443

REG_UPDATE(DP_SYM32_ENC_SDP_GSP_CONTROL5, GSP_SOF_REFERENCE, 1);

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

445

REG_UPDATE(DP_SYM32_ENC_SDP_GSP_CONTROL5, GSP_TRANSMISSION_LINE_NUMBER,

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

492

REG_UPDATE(DP_SYM32_ENC_SDP_GSP_CONTROL0, GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE, info_frame->vsc.valid);

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

493

REG_UPDATE(DP_SYM32_ENC_SDP_GSP_CONTROL2, GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE, info_frame->spd.valid);

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

494

REG_UPDATE(DP_SYM32_ENC_SDP_GSP_CONTROL3, GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE, info_frame->hdrsmd.valid);

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

495

REG_UPDATE(DP_SYM32_ENC_SDP_GSP_CONTROL5, GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE, info_frame->adaptive_sync.valid);

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

502

REG_UPDATE(DP_SYM32_ENC_SDP_CONTROL,

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

516

REG_UPDATE(DP_SYM32_ENC_SDP_GSP_CONTROL0, GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE, 0);

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

517

REG_UPDATE(DP_SYM32_ENC_SDP_GSP_CONTROL2, GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE, 0);

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

518

REG_UPDATE(DP_SYM32_ENC_SDP_GSP_CONTROL3, GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE, 0);

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

527

REG_UPDATE(DP_SYM32_ENC_SDP_CONTROL,

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

561

REG_UPDATE(DP_SYM32_ENC_SDP_GSP_CONTROL11,

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

583

REG_UPDATE(DP_SYM32_ENC_SDP_GSP_CONTROL11,

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

591

REG_UPDATE(DP_SYM32_ENC_SDP_GSP_CONTROL11,

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

593

REG_UPDATE(DP_SYM32_ENC_SDP_CONTROL,

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

614

REG_UPDATE(DP_STREAM_MAPPER_CONTROL0,

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

618

REG_UPDATE(DP_STREAM_MAPPER_CONTROL1,

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

622

REG_UPDATE(DP_STREAM_MAPPER_CONTROL2,

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

626

REG_UPDATE(DP_STREAM_MAPPER_CONTROL3,

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

640

REG_UPDATE(DP_STREAM_ENC_AUDIO_CONTROL,

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

653

REG_UPDATE(DP_SYM32_ENC_SDP_AUDIO_CONTROL0, ASP_ENABLE, 1);

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

66

REG_UPDATE(DP_STREAM_ENC_CLOCK_CONTROL,

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

661

REG_UPDATE(DP_SYM32_ENC_SDP_CONTROL,

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

682

REG_UPDATE(DP_SYM32_ENC_SDP_CONTROL,

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

70

REG_UPDATE(DP_SYM32_ENC_CONTROL,

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

78

REG_UPDATE(DP_SYM32_ENC_CONTROL,

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

86

REG_UPDATE(DP_SYM32_ENC_CONTROL,

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

97

REG_UPDATE(DP_STREAM_ENC_INPUT_MUX_CONTROL,

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

604

REG_UPDATE(DCHUBBUB_ARB_SAT_LEVEL,

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

606

REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND,

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

634

REG_UPDATE(DCHUBBUB_SDPIF_FB_TOP,

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

637

REG_UPDATE(DCHUBBUB_SDPIF_FB_BASE,

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

640

REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE,

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

643

REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT,

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

646

REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP,

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

653

REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE,

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

656

REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT,

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

659

REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP,

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

665

REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE,

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

668

REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT,

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

671

REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP,

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

688

REG_UPDATE(DCHUBBUB_SOFT_RESET,

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

952

REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, refdiv);

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

954

REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, enable ? 1 : 0);

drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

442

REG_UPDATE(DCN_VM_FB_LOCATION_TOP,

drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

445

REG_UPDATE(DCN_VM_FB_LOCATION_BASE,

drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

449

REG_UPDATE(DCN_VM_AGP_BASE,

drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

454

REG_UPDATE(DCN_VM_AGP_BOT,

drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

459

REG_UPDATE(DCN_VM_AGP_TOP,

drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

467

REG_UPDATE(DCN_VM_AGP_BASE,

drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

472

REG_UPDATE(DCN_VM_AGP_BOT,

drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

477

REG_UPDATE(DCN_VM_AGP_TOP,

drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

485

REG_UPDATE(DCN_VM_AGP_BASE,

drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

490

REG_UPDATE(DCN_VM_AGP_BOT,

drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

495

REG_UPDATE(DCN_VM_AGP_TOP,

drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

624

REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 180);

drivers/gpu/drm/amd/display/dc/hubbub/dcn201/dcn201_hubbub.c

70

REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND,

drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

610

REG_UPDATE(DCHUBBUB_ARB_HOSTVM_CNTL,

drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

74

REG_UPDATE(DCHVM_CTRL0, HOSTVM_INIT_REQ, 1);

drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

88

REG_UPDATE(DCHVM_RIOMMU_CTRL0, HOSTVM_POWERSTATUS, 1);

drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

91

REG_UPDATE(DCHVM_RIOMMU_CTRL0, HOSTVM_PREFETCH_REQ, 1);

drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

129

REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND,

drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

1054

REG_UPDATE(DCHUBBUB_SDPIF_CFG0, SDPIF_PORT_CONTROL, 1);

drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

149

REG_UPDATE(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE, compbuf_size_segments);

drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

73

REG_UPDATE(DCHUBBUB_DEBUG_CTRL_0, DET_DEPTH, 0x17F);

drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

84

REG_UPDATE(DCHUBBUB_DET0_CTRL,

drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

89

REG_UPDATE(DCHUBBUB_DET1_CTRL,

drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

94

REG_UPDATE(DCHUBBUB_DET2_CTRL,

drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

99

REG_UPDATE(DCHUBBUB_DET3_CTRL,

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

1009

REG_UPDATE(DCHUBBUB_SDPIF_CFG1,

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

109

REG_UPDATE(DCHUBBUB_DET0_CTRL,

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

114

REG_UPDATE(DCHUBBUB_DET1_CTRL,

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

119

REG_UPDATE(DCHUBBUB_DET2_CTRL,

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

124

REG_UPDATE(DCHUBBUB_DET3_CTRL,

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

155

REG_UPDATE(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE, compbuf_size_segments);

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

73

REG_UPDATE(DCHUBBUB_DEBUG_CTRL_0, DET_DEPTH, 0x47F);

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

80

REG_UPDATE(DCHUBBUB_SDPIF_CFG0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

97

REG_UPDATE(SDPIF_REQUEST_RATE_LIMIT, SDPIF_REQUEST_RATE_LIMIT, request_limit);

drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

327

REG_UPDATE(DCHUBBUB_ARB_HOSTVM_CNTL, DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD, 0xF);

drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

514

REG_UPDATE(DCHUBBUB_CLOCK_CNTL, DCHUBBUB_FGCG_REP_DIS, !enable);

drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

536

REG_UPDATE(DCHUBBUB_SDPIF_CFG0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

542

REG_UPDATE(DCHUBBUB_SDPIF_CFG1,

drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

559

REG_UPDATE(DCHVM_CTRL0, HOSTVM_INIT_REQ, 1);

drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

573

REG_UPDATE(DCHVM_MEM_CTRL, HVM_GPUVMRET_PWR_REQ_DIS, 1);

drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

581

REG_UPDATE(DCHVM_RIOMMU_CTRL0, HOSTVM_POWERSTATUS, 1);

drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

584

REG_UPDATE(DCHVM_RIOMMU_CTRL0, HOSTVM_PREFETCH_REQ, 1);

drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

590

REG_UPDATE(DCHVM_MEM_CTRL, HVM_GPUVMRET_PWR_REQ_DIS, 0);

drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

71

REG_UPDATE(DCHUBBUB_DEBUG_CTRL_0, DET_DEPTH, 0x5FF);

drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

89

REG_UPDATE(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE, compbuf_size_segments);

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

1119

REG_UPDATE(DCHUBBUB_DET0_CTRL,

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

1124

REG_UPDATE(DCHUBBUB_DET1_CTRL,

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

1129

REG_UPDATE(DCHUBBUB_DET2_CTRL,

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

1134

REG_UPDATE(DCHUBBUB_DET3_CTRL,

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

1166

REG_UPDATE(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE, compbuf_size_seg);

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

1206

REG_UPDATE(DCHUBBUB_TIMEOUT_DETECTION_CTRL2, DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD, arb_regs->pstate_stall_threshold);

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

1218

REG_UPDATE(DCHUBBUB_CTRL_STATUS, DCHUBBUB_HW_DEBUG, temp);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

107

REG_UPDATE(DCHUBP_CNTL, HUBP_UNDERFLOW_CLEAR, 1);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

115

REG_UPDATE(DCHUBP_CNTL, HUBP_BLANK_EN, blank_en);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1177

REG_UPDATE(CURSOR_SURFACE_ADDRESS_HIGH,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1179

REG_UPDATE(CURSOR_SURFACE_ADDRESS,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1275

REG_UPDATE(CURSOR_CONTROL,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1304

REG_UPDATE(HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, clk_enable);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1311

REG_UPDATE(DCHUBP_CNTL, HUBP_VTG_SEL, otg_inst);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1327

REG_UPDATE(DCHUBP_CNTL, HUBP_DISABLE, reset ? 1 : 0);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1339

REG_UPDATE(DCSURF_SURFACE_FLIP_INTERRUPT,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

262

REG_UPDATE(DCSURF_SURFACE_CONFIG,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

266

REG_UPDATE(DCSURF_SURFACE_CONFIG,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

271

REG_UPDATE(DCSURF_SURFACE_CONFIG,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

277

REG_UPDATE(DCSURF_SURFACE_CONFIG,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

282

REG_UPDATE(DCSURF_SURFACE_CONFIG,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

287

REG_UPDATE(DCSURF_SURFACE_CONFIG,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

292

REG_UPDATE(DCSURF_SURFACE_CONFIG,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

296

REG_UPDATE(DCSURF_SURFACE_CONFIG,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

300

REG_UPDATE(DCSURF_SURFACE_CONFIG,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

304

REG_UPDATE(DCSURF_SURFACE_CONFIG,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

308

REG_UPDATE(DCSURF_SURFACE_CONFIG,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

312

REG_UPDATE(DCSURF_SURFACE_CONFIG,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

316

REG_UPDATE(DCSURF_SURFACE_CONFIG,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

320

REG_UPDATE(DCSURF_SURFACE_CONFIG,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

324

REG_UPDATE(DCSURF_SURFACE_CONFIG,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

328

REG_UPDATE(DCSURF_SURFACE_CONFIG,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

358

REG_UPDATE(DCSURF_FLIP_CONTROL,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

363

REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x1);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

364

REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x1);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

368

REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x0);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

369

REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x0);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

525

REG_UPDATE(DCHUBP_REQ_SIZE_CONFIG, SWATH_HEIGHT, 0);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

526

REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, DC_SW_LINEAR);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

579

REG_UPDATE(HUBPRET_CONTROL,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

74

REG_UPDATE(DCHUBP_CNTL,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

77

REG_UPDATE(CURSOR_CONTROL,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

86

REG_UPDATE(DCHUBP_CNTL,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1070

REG_UPDATE(CURSOR_CONTROL, CURSOR_ENABLE, cur_en);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1121

REG_UPDATE(HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, clk_enable);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1128

REG_UPDATE(DCHUBP_CNTL, HUBP_VTG_SEL, otg_inst);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1135

REG_UPDATE(DCHUBP_CNTL, HUBP_UNDERFLOW_CLEAR, 1);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

194

REG_UPDATE(DCHUBP_CNTL, HUBP_VREADY_AT_OR_AFTER_VSYNC, value);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

202

REG_UPDATE(HUBPRET_CONTROL,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

413

REG_UPDATE(DCHUBP_REQ_SIZE_CONFIG, SWATH_HEIGHT, 0);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

414

REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, DC_SW_LINEAR);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

463

REG_UPDATE(DCSURF_SURFACE_CONFIG,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

467

REG_UPDATE(DCSURF_SURFACE_CONFIG,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

472

REG_UPDATE(DCSURF_SURFACE_CONFIG,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

478

REG_UPDATE(DCSURF_SURFACE_CONFIG,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

483

REG_UPDATE(DCSURF_SURFACE_CONFIG,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

488

REG_UPDATE(DCSURF_SURFACE_CONFIG,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

493

REG_UPDATE(DCSURF_SURFACE_CONFIG,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

497

REG_UPDATE(DCSURF_SURFACE_CONFIG,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

501

REG_UPDATE(DCSURF_SURFACE_CONFIG,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

505

REG_UPDATE(DCSURF_SURFACE_CONFIG,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

509

REG_UPDATE(DCSURF_SURFACE_CONFIG,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

513

REG_UPDATE(DCSURF_SURFACE_CONFIG,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

517

REG_UPDATE(DCSURF_SURFACE_CONFIG,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

521

REG_UPDATE(DCSURF_SURFACE_CONFIG,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

525

REG_UPDATE(DCSURF_SURFACE_CONFIG,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

529

REG_UPDATE(DCSURF_SURFACE_CONFIG,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

617

REG_UPDATE(CURSOR_SURFACE_ADDRESS_HIGH,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

619

REG_UPDATE(CURSOR_SURFACE_ADDRESS,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

663

REG_UPDATE(DMDATA_CNTL,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

667

REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, 1);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

670

REG_UPDATE(DMDATA_CNTL,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

679

REG_UPDATE(DMDATA_ADDRESS_HIGH,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

682

REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, 0);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

689

REG_UPDATE(DMDATA_SW_CNTL,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

736

REG_UPDATE(DCSURF_FLIP_CONTROL,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

740

REG_UPDATE(VMID_SETTINGS_0,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

902

REG_UPDATE(DCSURF_FLIP_CONTROL2,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

922

REG_UPDATE(DCSURF_FLIP_CONTROL2, SURFACE_GSL_ENABLE, enable ? 1 : 0);

drivers/gpu/drm/amd/display/dc/hubp/dcn201/dcn201_hubp.c

71

REG_UPDATE(HUBPRET_CONTROL,

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

143

REG_UPDATE(HUBPRET_CONTROL,

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

603

REG_UPDATE(VMID_SETTINGS_0,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

341

REG_UPDATE(DCHUBP_REQ_SIZE_CONFIG, SWATH_HEIGHT, 0);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

342

REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, DC_SW_LINEAR);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

387

REG_UPDATE(DMDATA_CNTL,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

391

REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, 1);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

394

REG_UPDATE(DMDATA_CNTL,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

403

REG_UPDATE(DMDATA_ADDRESS_HIGH,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

406

REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, 0);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

438

REG_UPDATE(DCN_DMDATA_VM_CNTL,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

623

REG_UPDATE(DCHUBP_CNTL, HUBP_TTU_DISABLE, 0);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

76

REG_UPDATE(DCSURF_FLIP_CONTROL,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

81

REG_UPDATE(VMID_SETTINGS_0,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

85

REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

86

REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x1);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

90

REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x0);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

91

REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x0);

drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c

46

REG_UPDATE(DCHUBP_CNTL, HUBP_UNBOUNDED_REQ_MODE, enable);

drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c

47

REG_UPDATE(CURSOR_CONTROL, CURSOR_REQ_MODE, 1);

drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c

54

REG_UPDATE(DCHUBP_CNTL, HUBP_SOFT_RESET, reset);

drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c

62

REG_UPDATE(BLANK_OFFSET_1, MIN_DST_Y_NEXT_START, min_dst_y_next_start_optimized);

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

144

REG_UPDATE(CURSOR_SURFACE_ADDRESS_HIGH,

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

146

REG_UPDATE(CURSOR_SURFACE_ADDRESS,

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

165

REG_UPDATE(DCHUBP_MALL_CONFIG, USE_MALL_FOR_CURSOR, use_mall_for_cursor);

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

188

REG_UPDATE(DCHUBP_CNTL, HUBP_TTU_DISABLE, 0);

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

71

REG_UPDATE(DCHUBP_VMPG_CONFIG, FORCE_ONE_ROW_FOR_FRAME, enable);

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

83

REG_UPDATE(CURSOR_CONTROL, CURSOR_REQ_MODE, enable);

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

92

REG_UPDATE(DCSURF_FLIP_CONTROL2, SURFACE_GSL_ENABLE, 0);

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

93

REG_UPDATE(DCHUBP_CNTL, HUBP_BLANK_EN, 1);

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

100

REG_UPDATE(DCSURF_SURFACE_CONFIG,

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

105

REG_UPDATE(DCSURF_SURFACE_CONFIG,

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

110

REG_UPDATE(DCSURF_SURFACE_CONFIG,

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

115

REG_UPDATE(DCSURF_SURFACE_CONFIG,

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

119

REG_UPDATE(DCSURF_SURFACE_CONFIG,

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

123

REG_UPDATE(DCSURF_SURFACE_CONFIG,

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

127

REG_UPDATE(DCSURF_SURFACE_CONFIG,

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

131

REG_UPDATE(DCSURF_SURFACE_CONFIG,

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

135

REG_UPDATE(DCSURF_SURFACE_CONFIG,

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

139

REG_UPDATE(DCSURF_SURFACE_CONFIG,

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

143

REG_UPDATE(DCSURF_SURFACE_CONFIG,

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

147

REG_UPDATE(DCSURF_SURFACE_CONFIG,

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

151

REG_UPDATE(DCSURF_SURFACE_CONFIG,

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

45

REG_UPDATE(HUBP_CLK_CNTL, HUBP_FGCG_REP_DIS, !enable);

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

85

REG_UPDATE(DCSURF_SURFACE_CONFIG,

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

89

REG_UPDATE(DCSURF_SURFACE_CONFIG,

drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c

94

REG_UPDATE(DCSURF_SURFACE_CONFIG,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

1018

REG_UPDATE(DCHUBP_CNTL, HUBP_UNBOUNDED_REQ_MODE, enable);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

1026

REG_UPDATE(CURSOR_CONTROL, CURSOR_REQ_MODE, 1);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

120

REG_UPDATE(_3DLUT_FL_CONFIG, HUBP0_3DLUT_FL_MODE, mode);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

127

REG_UPDATE(_3DLUT_FL_CONFIG, HUBP0_3DLUT_FL_FORMAT, format);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

150

REG_UPDATE(HUBP_3DLUT_ADDRESS_HIGH,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

152

REG_UPDATE(HUBP_3DLUT_ADDRESS_LOW,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

217

REG_UPDATE(DCHUBP_CNTL, HUBP_VREADY_AT_OR_AFTER_VSYNC, reg_value);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

226

REG_UPDATE(HUBPRET_CONTROL,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

342

REG_UPDATE(DCN_DMDATA_VM_CNTL,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

417

REG_UPDATE(DCSURF_FLIP_CONTROL,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

422

REG_UPDATE(VMID_SETTINGS_0,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

426

REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

427

REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x1);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

431

REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x0);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

432

REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x0);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

445

REG_UPDATE(DCSURF_SURFACE_CONTROL,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

48

REG_UPDATE(HUBP_3DLUT_ADDRESS_HIGH, HUBP_3DLUT_ADDRESS_HIGH, address.lut3d.addr.high_part);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

56

REG_UPDATE(HUBP_3DLUT_DLG_PARAM, REFCYC_PER_3DLUT_GROUP, refcyc_per_3dlut_group);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

564

REG_UPDATE(DCHUBP_REQ_SIZE_CONFIG, SWATH_HEIGHT, 0);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

565

REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, DC_SW_LINEAR);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

592

REG_UPDATE(DCSURF_TILING_CONFIG, SW_MODE, info->gfx_addr3.swizzle);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

623

REG_UPDATE(DCSURF_SURFACE_PITCH, PITCH, pitch);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

626

REG_UPDATE(DCSURF_SURFACE_PITCH_C, PITCH_C, pitch_c);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

63

REG_UPDATE(HUBP_3DLUT_CONTROL, HUBP_3DLUT_ENABLE, enable ? 1 : 0);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

714

REG_UPDATE(DCSURF_SURFACE_FLIP_INTERRUPT,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

785

REG_UPDATE(CURSOR_CONTROL,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

79

REG_UPDATE(HUBP_3DLUT_CONTROL, HUBP_3DLUT_ADDRESSING_MODE, addr_mode);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

86

REG_UPDATE(HUBP_3DLUT_CONTROL, HUBP_3DLUT_WIDTH, width);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

93

REG_UPDATE(HUBP_3DLUT_CONTROL, HUBP_3DLUT_TMZ, protection_bits);

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.c

126

REG_UPDATE(BLND_CONTROL[blnd_inst],

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.c

141

REG_UPDATE(DC_MEM_GLOBAL_PWR_REQ_CNTL,

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.c

149

REG_UPDATE(DCFEV_CLOCK_CONTROL,

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.c

180

REG_UPDATE(PIXEL_RATE_CNTL[tg_inst],

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.c

190

REG_UPDATE(PIXEL_RATE_CNTL[tg_inst],

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.c

201

REG_UPDATE(PHYPLL_PIXEL_RATE_CNTL[tg_inst],

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.c

43

REG_UPDATE(DCFE_CLOCK_CONTROL[fe_inst],

drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c

206

REG_UPDATE(DCHUB_AGP_BASE,

drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c

209

REG_UPDATE(DCHUB_AGP_BOT,

drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c

212

REG_UPDATE(DCHUB_AGP_TOP,

drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c

217

REG_UPDATE(DCHUB_AGP_BASE,

drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c

220

REG_UPDATE(DCHUB_AGP_BOT,

drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c

223

REG_UPDATE(DCHUB_AGP_TOP,

drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c

228

REG_UPDATE(DCHUB_AGP_BASE,

drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c

231

REG_UPDATE(DCHUB_AGP_BOT,

drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c

234

REG_UPDATE(DCHUB_AGP_TOP,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1893

REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

841

REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

842

REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

843

REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

844

REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

847

REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

848

REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

849

REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

850

REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

882

REG_UPDATE(VGA_TEST_CONTROL, VGA_TEST_ENABLE, 1);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

883

REG_UPDATE(VGA_TEST_CONTROL, VGA_TEST_RENDER_START, 1);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

910

REG_UPDATE(DOMAIN1_PG_CONFIG,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

918

REG_UPDATE(DOMAIN3_PG_CONFIG,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

926

REG_UPDATE(DOMAIN5_PG_CONFIG,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

934

REG_UPDATE(DOMAIN7_PG_CONFIG,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

971

REG_UPDATE(DOMAIN0_PG_CONFIG,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

979

REG_UPDATE(DOMAIN2_PG_CONFIG,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

987

REG_UPDATE(DOMAIN4_PG_CONFIG,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

995

REG_UPDATE(DOMAIN6_PG_CONFIG,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

323

REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

324

REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

325

REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

326

REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

328

REG_UPDATE(DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

330

REG_UPDATE(DOMAIN10_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

333

REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

334

REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

335

REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

336

REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

338

REG_UPDATE(DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

340

REG_UPDATE(DOMAIN11_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

343

REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, force_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

344

REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, force_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

345

REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, force_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

347

REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, force_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

349

REG_UPDATE(DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, force_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

351

REG_UPDATE(DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, force_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

480

REG_UPDATE(DOMAIN16_PG_CONFIG,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

488

REG_UPDATE(DOMAIN17_PG_CONFIG,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

496

REG_UPDATE(DOMAIN18_PG_CONFIG,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

504

REG_UPDATE(DOMAIN19_PG_CONFIG,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

512

REG_UPDATE(DOMAIN20_PG_CONFIG,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

520

REG_UPDATE(DOMAIN21_PG_CONFIG,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

551

REG_UPDATE(DOMAIN1_PG_CONFIG,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

559

REG_UPDATE(DOMAIN3_PG_CONFIG,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

567

REG_UPDATE(DOMAIN5_PG_CONFIG,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

575

REG_UPDATE(DOMAIN7_PG_CONFIG,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

583

REG_UPDATE(DOMAIN9_PG_CONFIG,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

633

REG_UPDATE(DOMAIN0_PG_CONFIG,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

641

REG_UPDATE(DOMAIN2_PG_CONFIG,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

649

REG_UPDATE(DOMAIN4_PG_CONFIG,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

657

REG_UPDATE(DOMAIN6_PG_CONFIG,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

665

REG_UPDATE(DOMAIN8_PG_CONFIG,

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

373

REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

667

REG_UPDATE(DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, 3);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

679

REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

807

REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c

114

REG_UPDATE(DOMAIN0_PG_CONFIG,

drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c

122

REG_UPDATE(DOMAIN2_PG_CONFIG,

drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c

130

REG_UPDATE(DOMAIN4_PG_CONFIG,

drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c

138

REG_UPDATE(DOMAIN6_PG_CONFIG,

drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c

146

REG_UPDATE(DOMAIN8_PG_CONFIG,

drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c

177

REG_UPDATE(DOMAIN16_PG_CONFIG,

drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c

185

REG_UPDATE(DOMAIN17_PG_CONFIG,

drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c

193

REG_UPDATE(DOMAIN18_PG_CONFIG,

drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c

201

REG_UPDATE(DOMAIN19_PG_CONFIG,

drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c

209

REG_UPDATE(DOMAIN20_PG_CONFIG,

drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c

57

REG_UPDATE(DOMAIN1_PG_CONFIG,

drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c

65

REG_UPDATE(DOMAIN3_PG_CONFIG,

drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c

73

REG_UPDATE(DOMAIN5_PG_CONFIG,

drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c

81

REG_UPDATE(DOMAIN7_PG_CONFIG,

drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c

89

REG_UPDATE(DOMAIN9_PG_CONFIG,

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

253

REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

303

REG_UPDATE(DOMAIN16_PG_CONFIG,

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

311

REG_UPDATE(DOMAIN17_PG_CONFIG,

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

319

REG_UPDATE(DOMAIN18_PG_CONFIG,

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

357

REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

358

REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

360

REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

361

REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

368

REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

369

REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

370

REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

661

REG_UPDATE(HPO_TOP_HW_CONTROL, HPO_IO_EN, !!enable);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

80

REG_UPDATE(DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, 3);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

92

REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

249

REG_UPDATE(DOMAIN16_PG_CONFIG,

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

257

REG_UPDATE(DOMAIN17_PG_CONFIG,

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

265

REG_UPDATE(DOMAIN18_PG_CONFIG,

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

273

REG_UPDATE(DOMAIN19_PG_CONFIG,

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

308

REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

309

REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

311

REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

312

REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

319

REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

320

REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

321

REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

322

REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

568

REG_UPDATE(DOMAIN1_PG_CONFIG,

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

576

REG_UPDATE(DOMAIN3_PG_CONFIG,

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

584

REG_UPDATE(DOMAIN5_PG_CONFIG,

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

592

REG_UPDATE(DOMAIN7_PG_CONFIG,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

104

REG_UPDATE(DOMAIN17_PG_CONFIG,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

112

REG_UPDATE(DOMAIN18_PG_CONFIG,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

120

REG_UPDATE(DOMAIN19_PG_CONFIG,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

152

REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

153

REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

154

REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

155

REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

158

REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

159

REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

160

REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

161

REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

816

REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

96

REG_UPDATE(DOMAIN16_PG_CONFIG,

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

969

REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

137

REG_UPDATE(HPO_TOP_HW_CONTROL, HPO_IO_EN, !!enable);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

285

REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

86

REG_UPDATE(DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, 3);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

98

REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1015

REG_UPDATE(HPO_TOP_HW_CONTROL, HPO_IO_EN, enable);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

178

REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

337

REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

383

{ uint32_t val = REG_UPDATE(reg, f1, v1); \

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

387

{ uint32_t val = REG_UPDATE(reg, f1, v1); \

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c

101

REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y_OFFSET, MCIF_WB_BUF_2_ADDR_Y_OFFSET, 0);

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c

104

REG_UPDATE(MCIF_WB_BUF_2_ADDR_C, MCIF_WB_BUF_2_ADDR_C, MCIF_ADDR(params->chroma_address[1]));

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c

105

REG_UPDATE(MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_address[1]));

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c

107

REG_UPDATE(MCIF_WB_BUF_2_ADDR_C_OFFSET, MCIF_WB_BUF_2_ADDR_C_OFFSET, 0);

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c

110

REG_UPDATE(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB_BUF_3_ADDR_Y, MCIF_ADDR(params->luma_address[2]));

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c

111

REG_UPDATE(MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_address[2]));

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c

113

REG_UPDATE(MCIF_WB_BUF_3_ADDR_Y_OFFSET, MCIF_WB_BUF_3_ADDR_Y_OFFSET, 0);

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c

116

REG_UPDATE(MCIF_WB_BUF_3_ADDR_C, MCIF_WB_BUF_3_ADDR_C, MCIF_ADDR(params->chroma_address[2]));

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c

117

REG_UPDATE(MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_address[2]));

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c

119

REG_UPDATE(MCIF_WB_BUF_3_ADDR_C_OFFSET, MCIF_WB_BUF_3_ADDR_C_OFFSET, 0);

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c

122

REG_UPDATE(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB_BUF_4_ADDR_Y, MCIF_ADDR(params->luma_address[3]));

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c

123

REG_UPDATE(MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_address[3]));

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c

125

REG_UPDATE(MCIF_WB_BUF_4_ADDR_Y_OFFSET, MCIF_WB_BUF_4_ADDR_Y_OFFSET, 0);

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c

128

REG_UPDATE(MCIF_WB_BUF_4_ADDR_C, MCIF_WB_BUF_4_ADDR_C, MCIF_ADDR(params->chroma_address[3]));

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c

129

REG_UPDATE(MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_address[3]));

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c

131

REG_UPDATE(MCIF_WB_BUF_4_ADDR_C_OFFSET, MCIF_WB_BUF_4_ADDR_C_OFFSET, 0);

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c

137

REG_UPDATE(MCIF_WB_BUF_LUMA_SIZE, MCIF_WB_BUF_LUMA_SIZE, (params->luma_pitch>>8) * dest_height);

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c

138

REG_UPDATE(MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB_BUF_CHROMA_SIZE, (params->chroma_pitch>>8) * dest_height);

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c

141

REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, 1);

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c

150

REG_UPDATE(MCIF_WB_WARM_UP_CNTL, MCIF_WB_PITCH_SIZE_WARMUP, params->warmup_pitch);

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c

159

REG_UPDATE(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_TIME_PER_PIXEL, params->time_per_pixel);

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c

164

REG_UPDATE(MCIF_WB_SCLK_CHANGE, MCIF_WB_CLI_WATERMARK_MASK, 0x0);

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c

166

REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, params->cli_watermark[0]);

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c

167

REG_UPDATE(MCIF_WB_SCLK_CHANGE, MCIF_WB_CLI_WATERMARK_MASK, 0x1);

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c

169

REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, params->cli_watermark[1]);

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c

170

REG_UPDATE(MCIF_WB_SCLK_CHANGE, MCIF_WB_CLI_WATERMARK_MASK, 0x2);

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c

172

REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, params->cli_watermark[2]);

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c

173

REG_UPDATE(MCIF_WB_SCLK_CHANGE, MCIF_WB_CLI_WATERMARK_MASK, 0x3);

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c

175

REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, params->cli_watermark[3]);

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c

179

REG_UPDATE(MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x0);

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c

180

REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK,

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c

183

REG_UPDATE(MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x1);

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c

184

REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK,

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c

187

REG_UPDATE(MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x2);

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c

188

REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK,

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c

191

REG_UPDATE(MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x3);

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c

192

REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK,

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c

196

REG_UPDATE(MULTI_LEVEL_QOS_CTRL, MAX_SCALED_TIME_TO_URGENT, params->max_scaled_time);

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c

199

REG_UPDATE(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_SLICE_SIZE, params->slice_lines-1);

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c

204

REG_UPDATE(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_CLIENT_ARBITRATION_SLICE, params->arbitration_slice);

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c

213

REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_EN, params->sw_int_en);

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c

214

REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_SLICE_INT_EN, params->sw_slice_int_en);

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c

215

REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN, params->sw_overrun_int_en);

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c

217

REG_UPDATE(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_INT_EN, params->vce_int_en);

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c

219

REG_UPDATE(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_SLICE_INT_EN, params->vce_slice_int_en);

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c

227

REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, 1);

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c

235

REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, 0);

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c

285

REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, 0xf);

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c

290

REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, 0x0);

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c

83

REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, params->swlock);

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c

86

REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, MCIF_ADDR(params->luma_address[0]));

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c

87

REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_address[0]));

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c

89

REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y_OFFSET, MCIF_WB_BUF_1_ADDR_Y_OFFSET, 0);

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c

92

REG_UPDATE(MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, MCIF_ADDR(params->chroma_address[0]));

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c

93

REG_UPDATE(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_address[0]));

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c

95

REG_UPDATE(MCIF_WB_BUF_1_ADDR_C_OFFSET, MCIF_WB_BUF_1_ADDR_C_OFFSET, 0);

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c

98

REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB_BUF_2_ADDR_Y, MCIF_ADDR(params->luma_address[1]));

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c

99

REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_address[1]));

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c

100

REG_UPDATE(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_EN, false);

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c

110

REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, MCIF_ADDR(params->luma_address[0]));

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c

111

REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_address[0]));

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c

114

REG_UPDATE(MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, MCIF_ADDR(params->chroma_address[0]));

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c

115

REG_UPDATE(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_address[0]));

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c

118

REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB_BUF_2_ADDR_Y, MCIF_ADDR(params->luma_address[1]));

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c

119

REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_address[1]));

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c

122

REG_UPDATE(MCIF_WB_BUF_2_ADDR_C, MCIF_WB_BUF_2_ADDR_C, MCIF_ADDR(params->chroma_address[1]));

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c

123

REG_UPDATE(MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_address[1]));

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c

126

REG_UPDATE(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB_BUF_3_ADDR_Y, MCIF_ADDR(params->luma_address[2]));

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c

127

REG_UPDATE(MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_address[2]));

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c

130

REG_UPDATE(MCIF_WB_BUF_3_ADDR_C, MCIF_WB_BUF_3_ADDR_C, MCIF_ADDR(params->chroma_address[2]));

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c

131

REG_UPDATE(MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_address[2]));

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c

134

REG_UPDATE(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB_BUF_4_ADDR_Y, MCIF_ADDR(params->luma_address[3]));

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c

135

REG_UPDATE(MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_address[3]));

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c

138

REG_UPDATE(MCIF_WB_BUF_4_ADDR_C, MCIF_WB_BUF_4_ADDR_C, MCIF_ADDR(params->chroma_address[3]));

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c

139

REG_UPDATE(MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_address[3]));

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c

145

REG_UPDATE(MCIF_WB_BUF_LUMA_SIZE, MCIF_WB_BUF_LUMA_SIZE, (params->luma_pitch>>8) * dest_height);

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c

146

REG_UPDATE(MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB_BUF_CHROMA_SIZE, (params->chroma_pitch>>8) * dest_height);

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c

149

REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, 1);

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c

162

REG_UPDATE(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_TIME_PER_PIXEL, params->time_per_pixel);

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c

167

REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK_MASK, 0x0);

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c

169

REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, params->cli_watermark[0]);

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c

170

REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK_MASK, 0x1);

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c

172

REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, params->cli_watermark[1]);

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c

173

REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK_MASK, 0x2);

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c

175

REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, params->cli_watermark[2]);

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c

176

REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK_MASK, 0x3);

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c

178

REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, params->cli_watermark[3]);

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c

182

REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x0);

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c

183

REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK,

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c

186

REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x1);

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c

187

REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK,

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c

190

REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x2);

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c

191

REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK,

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c

194

REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x3);

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c

195

REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK,

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c

203

REG_UPDATE(MULTI_LEVEL_QOS_CTRL, MAX_SCALED_TIME_TO_URGENT, params->max_scaled_time);

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c

206

REG_UPDATE(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_SLICE_SIZE, params->slice_lines-1);

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c

211

REG_UPDATE(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_CLIENT_ARBITRATION_SLICE, params->arbitration_slice);

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c

97

REG_UPDATE(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_SW_INT_ACK, 1);

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn35/dcn35_mmhubbub.c

58

REG_UPDATE(MMHUBBUB_CLOCK_CNTL, MMHUBBUB_FGCG_REP_DIS, !enabled);

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

214

REG_UPDATE(MPCC_CONTROL[mpcc_id], MPCC_MODE, MPCC_BLEND_MODE_TOP_BOT_BLENDING);

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

218

REG_UPDATE(MPCC_CONTROL[mpcc_id], MPCC_MODE, MPCC_BLEND_MODE_TOP_LAYER_ONLY);

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

230

REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

241

REG_UPDATE(MPCC_CONTROL[temp_mpcc->mpcc_id],

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

286

REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, tree->opp_list->mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

290

REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, 0xf);

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

310

REG_UPDATE(MPCC_CONTROL[temp_mpcc->mpcc_id],

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

373

REG_UPDATE(MUX[opp_id], MPC_OUT_MUX, 0xf);

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

392

REG_UPDATE(MUX[opp_id], MPC_OUT_MUX, 0xf);

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

107

REG_UPDATE(DENORM_CONTROL[opp_id],

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1394

REG_UPDATE(MPC_RMU_CONTROL, MPC_RMU0_MUX, value);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1396

REG_UPDATE(MPC_RMU_CONTROL, MPC_RMU1_MUX, value);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1460

REG_UPDATE(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_MEM_LOW_PWR_MODE, 3);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1461

REG_UPDATE(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_MEM_LOW_PWR_MODE, 3);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1466

REG_UPDATE(MPCC_MEM_PWR_CTRL[mpcc_id], MPCC_OGAM_MEM_LOW_PWR_MODE, 3);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

180

REG_UPDATE(MPCC_MEM_PWR_CTRL[mpcc_id],

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

315

REG_UPDATE(MPCC_OGAM_LUT_CONTROL[mpcc_id],

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

323

REG_UPDATE(MPCC_OGAM_LUT_CONTROL[mpcc_id],

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

331

REG_UPDATE(MPCC_OGAM_LUT_CONTROL[mpcc_id],

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

382

REG_UPDATE(MPCC_OGAM_CONTROL[mpcc_id],

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

424

REG_UPDATE(DENORM_CONTROL[opp_id],

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

480

REG_UPDATE(SHAPER_LUT_WRITE_EN_MASK[rmu_idx],

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

482

REG_UPDATE(SHAPER_LUT_WRITE_EN_MASK[rmu_idx],

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

991

REG_UPDATE(RMU_3DLUT_READ_WRITE_CONTROL[rmu_idx], MPC_RMU_3DLUT_WRITE_EN_MASK,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

242

REG_UPDATE(MPCC_MCM_1DLUT_LUT_CONTROL[mpcc_id], MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK, 4);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

248

REG_UPDATE(MPCC_MCM_1DLUT_LUT_CONTROL[mpcc_id], MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK, 2);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

254

REG_UPDATE(MPCC_MCM_1DLUT_LUT_CONTROL[mpcc_id], MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK, 1);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

335

REG_UPDATE(MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK[mpcc_id],

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

337

REG_UPDATE(MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK[mpcc_id],

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

55

REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE, 3);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

56

REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE, 3);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

57

REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE, 3);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

62

REG_UPDATE(MPCC_MEM_PWR_CTRL[mpcc_id], MPCC_OGAM_MEM_LOW_PWR_MODE, 3);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

78

REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_1DLUT_MEM_PWR_FORCE, 0);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

820

REG_UPDATE(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], MPCC_MCM_3DLUT_WRITE_EN_MASK,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

892

REG_UPDATE(MPCC_MOVABLE_CM_LOCATION_CONTROL[mpcc_id], MPCC_MOVABLE_CM_LOCATION_CNTL, 0);

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

238

REG_UPDATE(MPCC_MCM_3DLUT_MODE[mpcc_id], MPCC_MCM_3DLUT_MODE, 0);

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

241

REG_UPDATE(MPCC_MCM_3DLUT_MODE[mpcc_id], MPCC_MCM_3DLUT_MODE, lut_bank_a ? 1 : 2);

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

248

REG_UPDATE(MPCC_MCM_SHAPER_CONTROL[mpcc_id], MPCC_MCM_SHAPER_LUT_MODE, 0);

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

251

REG_UPDATE(MPCC_MCM_SHAPER_CONTROL[mpcc_id], MPCC_MCM_SHAPER_LUT_MODE, lut_bank_a ? 1 : 2);

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

258

REG_UPDATE(MPCC_MCM_1DLUT_CONTROL[mpcc_id],

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

262

REG_UPDATE(MPCC_MCM_1DLUT_CONTROL[mpcc_id],

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

266

REG_UPDATE(MPCC_MCM_1DLUT_CONTROL[mpcc_id],

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

279

REG_UPDATE(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], MPCC_MCM_3DLUT_RAM_SEL, lut_bank_a ? 0 : 1);

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

56

REG_UPDATE(MPCC_MOVABLE_CM_LOCATION_CONTROL[mpcc_id],

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

60

REG_UPDATE(MPCC_MOVABLE_CM_LOCATION_CONTROL[mpcc_id],

drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.c

175

REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 0);

drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.c

194

REG_UPDATE(FMT_CONTROL, FMT_SUBSAMPLING_MODE, 0);

drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.c

308

REG_UPDATE(FMT_MAP420_MEMORY_CONTROL, FMT_MAP420MEM_PWR_FORCE, 0);

drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.c

342

REG_UPDATE(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, 0);

drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.c

344

REG_UPDATE(OPPBUF_CONTROL, OPPBUF_ACTIVE_WIDTH, active_width);

drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.c

352

REG_UPDATE(OPPBUF_3D_PARAMETERS_0, OPPBUF_3D_VACT_SPACE2_SIZE, space2_size);

drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.c

354

REG_UPDATE(OPPBUF_3D_PARAMETERS_0, OPPBUF_3D_VACT_SPACE1_SIZE, space1_size);

drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.c

372

REG_UPDATE(OPP_PIPE_CONTROL, OPP_PIPE_CLOCK_EN, regval);

drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c

366

REG_UPDATE(FMT_422_CONTROL, FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT, count);

drivers/gpu/drm/amd/display/dc/opp/dcn35/dcn35_opp.c

52

REG_UPDATE(OPP_TOP_CLK_CONTROL, OPP_FGCG_REP_DIS, !enable);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1265

REG_UPDATE(OTG_STEREO_CONTROL,

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1270

REG_UPDATE(OTG_STEREO_CONTROL,

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1433

REG_UPDATE(OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, 1);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

218

REG_UPDATE(OTG_H_SYNC_A_CNTL,

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

256

REG_UPDATE(OTG_V_SYNC_A_CNTL,

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

270

REG_UPDATE(OTG_INTERLACE_CONTROL,

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

273

REG_UPDATE(OTG_INTERLACE_CONTROL,

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

278

REG_UPDATE(CONTROL,

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

316

REG_UPDATE(OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, data_fmt);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

323

REG_UPDATE(OTG_H_TIMING_CNTL,

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

326

REG_UPDATE(OTG_H_TIMING_CNTL,

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

387

REG_UPDATE(CONTROL, VTG0_VCOUNT_INIT, v_init);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

396

REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL,

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

416

REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL,

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

534

REG_UPDATE(OPTC_DATA_SOURCE_SELECT,

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

538

REG_UPDATE(CONTROL,

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

566

REG_UPDATE(CONTROL,

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

114

REG_UPDATE(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, gsl_ready_signal);

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

117

REG_UPDATE(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, gsl_ready_signal);

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

120

REG_UPDATE(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, gsl_ready_signal);

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

139

REG_UPDATE(OPTC_DATA_FORMAT_CONTROL,

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

145

REG_UPDATE(OPTC_WIDTH_CONTROL,

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

174

REG_UPDATE(OTG_H_TIMING_CNTL,

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

213

REG_UPDATE(OPTC_WIDTH_CONTROL,

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

249

REG_UPDATE(DWB_SOURCE_SELECT,

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

252

REG_UPDATE(DWB_SOURCE_SELECT,

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

275

REG_UPDATE(OTG_CONTROL, OTG_MASTER_EN, 0);

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

313

REG_UPDATE(OTG_GLOBAL_CONTROL1,

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

334

REG_UPDATE(OTG_CONTROL,

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

359

REG_UPDATE(OTG_GLOBAL_CONTROL1,

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

415

REG_UPDATE(OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_EN, 1);

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

449

REG_UPDATE(OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_EN, 0);

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

59

REG_UPDATE(OPTC_DATA_SOURCE_SELECT,

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

63

REG_UPDATE(CONTROL,

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

113

REG_UPDATE(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 0);

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

114

REG_UPDATE(OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_EN, 0);

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

123

REG_UPDATE(OTG_GLOBAL_CONTROL2,

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

139

REG_UPDATE(OTG_CONTROL, OTG_OUT_MUX, dest);

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

192

REG_UPDATE(OTG_V_SYNC_A_CNTL, OTG_V_SYNC_MODE, 0);

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

210

REG_UPDATE(OTG_H_TIMING_CNTL,

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

267

REG_UPDATE(OPTC_WIDTH_CONTROL,

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

332

REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL,

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

49

REG_UPDATE(OTG_GLOBAL_CONTROL2,

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

92

REG_UPDATE(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 1);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

100

REG_UPDATE(OPTC_DATA_SOURCE_SELECT,

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

104

REG_UPDATE(CONTROL,

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

132

REG_UPDATE(OPTC_MEMORY_CONFIG,

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

138

REG_UPDATE(OTG_CONTROL,

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

141

REG_UPDATE(CONTROL,

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

163

REG_UPDATE(CONTROL,

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

85

REG_UPDATE(OPTC_WIDTH_CONTROL,

drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c

100

REG_UPDATE(OTG_H_TIMING_CNTL,

drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c

110

REG_UPDATE(OPTC_DATA_SOURCE_SELECT,

drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c

114

REG_UPDATE(CONTROL,

drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c

138

REG_UPDATE(OTG_CONTROL,

drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c

141

REG_UPDATE(CONTROL,

drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c

178

REG_UPDATE(OTG_H_TIMING_CNTL,

drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c

190

REG_UPDATE(OTG_H_TIMING_CNTL,

drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c

97

REG_UPDATE(OPTC_WIDTH_CONTROL,

drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

135

REG_UPDATE(OTG_H_TIMING_CNTL,

drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

150

REG_UPDATE(OPTC_DATA_SOURCE_SELECT,

drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

154

REG_UPDATE(CONTROL,

drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

182

REG_UPDATE(OPTC_MEMORY_CONFIG,

drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

188

REG_UPDATE(OTG_CONTROL,

drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

191

REG_UPDATE(CONTROL,

drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

224

REG_UPDATE(OTG_CONTROL, OTG_MASTER_EN, 0);

drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

242

REG_UPDATE(OTG_H_TIMING_CNTL,

drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

92

REG_UPDATE(OPTC_WIDTH_CONTROL,

drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

95

REG_UPDATE(OTG_H_TIMING_CNTL,

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

105

REG_UPDATE(OPTC_WIDTH_CONTROL,

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

108

REG_UPDATE(OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, opp_cnt - 1);

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

117

REG_UPDATE(OPTC_DATA_SOURCE_SELECT,

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

121

REG_UPDATE(CONTROL,

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

149

REG_UPDATE(OPTC_MEMORY_CONFIG,

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

155

REG_UPDATE(OTG_CONTROL,

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

158

REG_UPDATE(CONTROL,

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

360

REG_UPDATE(OTG_CRC_CNTL,

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

631

REG_UPDATE(OPTC_CLOCK_CONTROL, OPTC_FGCG_REP_DIS, !enable);

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

121

REG_UPDATE(OPTC_WIDTH_CONTROL,

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

124

REG_UPDATE(OTG_H_TIMING_CNTL,

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

133

REG_UPDATE(OPTC_WIDTH_CONTROL,

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

135

REG_UPDATE(OPTC_WIDTH_CONTROL2,

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

143

REG_UPDATE(OTG_H_TIMING_CNTL,

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

153

REG_UPDATE(OPTC_WIDTH_CONTROL,

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

155

REG_UPDATE(OTG_H_TIMING_CNTL,

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

169

REG_UPDATE(OTG_H_TIMING_CNTL,

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

185

REG_UPDATE(OPTC_DATA_SOURCE_SELECT,

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

189

REG_UPDATE(CONTROL,

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

217

REG_UPDATE(OPTC_MEMORY_CONFIG,

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

223

REG_UPDATE(OTG_CONTROL,

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

226

REG_UPDATE(CONTROL,

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

264

REG_UPDATE(OTG_CONTROL, OTG_MASTER_EN, 0);

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

282

REG_UPDATE(OTG_H_TIMING_CNTL,

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

381

REG_UPDATE(OTG_CONTROL, OTG_OUT_MUX, dest);

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

435

REG_UPDATE(OTG_PSTATE_REGISTER, OTG_PSTATE_KEEPOUT_START, pstate_keepout);

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

105

REG_UPDATE(DOMAIN16_PG_CONFIG,

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

113

REG_UPDATE(DOMAIN17_PG_CONFIG,

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

121

REG_UPDATE(DOMAIN18_PG_CONFIG,

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

129

REG_UPDATE(DOMAIN19_PG_CONFIG,

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

206

REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, power_gate);

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

211

REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, power_gate);

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

216

REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, power_gate);

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

221

REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, power_gate);

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

280

REG_UPDATE(DOMAIN25_PG_CONFIG, DOMAIN_POWER_GATE, power_gate);

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

328

REG_UPDATE(DOMAIN22_PG_CONFIG, DOMAIN_POWER_GATE, power_gate);

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

431

REG_UPDATE(DOMAIN24_PG_CONFIG, DOMAIN_POWER_GATE, power_gate);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

136

REG_UPDATE(DMCUB_CNTL, DMCUB_SOFT_RESET, 1);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

137

REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

138

REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 1);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

148

REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

151

REG_UPDATE(DMCUB_CNTL, DMCUB_SOFT_RESET, 0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

163

REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c

96

REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

131

REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 1);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

132

REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 1);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

133

REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

151

REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

154

REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

166

REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

342

REG_UPDATE(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN, 0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

345

REG_UPDATE(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK, 1);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

346

REG_UPDATE(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK, 0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

348

REG_UPDATE(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN, 1);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

127

REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 1);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

129

REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

137

REG_UPDATE(DMCUB_REGION3_CW2_TOP_ADDRESS, DMCUB_REGION3_CW2_ENABLE, 0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

138

REG_UPDATE(DMCUB_REGION3_CW3_TOP_ADDRESS, DMCUB_REGION3_CW3_ENABLE, 0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

139

REG_UPDATE(DMCUB_REGION3_CW4_TOP_ADDRESS, DMCUB_REGION3_CW4_ENABLE, 0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

140

REG_UPDATE(DMCUB_REGION3_CW5_TOP_ADDRESS, DMCUB_REGION3_CW5_ENABLE, 0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

141

REG_UPDATE(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, 0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

142

REG_UPDATE(DMCUB_REGION3_CW7_TOP_ADDRESS, DMCUB_REGION3_CW7_ENABLE, 0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

159

REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

162

REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

175

REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

176

REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

207

REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

208

REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

379

REG_UPDATE(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN, 0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

382

REG_UPDATE(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK, 1);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

383

REG_UPDATE(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK, 0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

385

REG_UPDATE(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN, 1);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

130

REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 1);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

132

REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

158

REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

159

REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

190

REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

199

REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

373

REG_UPDATE(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN, 0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

376

REG_UPDATE(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK, 1);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

377

REG_UPDATE(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK, 0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

379

REG_UPDATE(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN, 1);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

101

REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 1);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

103

REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

111

REG_UPDATE(DMCUB_REGION3_CW2_TOP_ADDRESS, DMCUB_REGION3_CW2_ENABLE, 0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

112

REG_UPDATE(DMCUB_REGION3_CW3_TOP_ADDRESS, DMCUB_REGION3_CW3_ENABLE, 0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

113

REG_UPDATE(DMCUB_REGION3_CW4_TOP_ADDRESS, DMCUB_REGION3_CW4_ENABLE, 0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

114

REG_UPDATE(DMCUB_REGION3_CW5_TOP_ADDRESS, DMCUB_REGION3_CW5_ENABLE, 0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

115

REG_UPDATE(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, 0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

116

REG_UPDATE(DMCUB_REGION3_CW7_TOP_ADDRESS, DMCUB_REGION3_CW7_ENABLE, 0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

133

REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

136

REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

149

REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

150

REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

182

REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

183

REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

364

REG_UPDATE(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN, 0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

367

REG_UPDATE(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK, 1);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

368

REG_UPDATE(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK, 0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

370

REG_UPDATE(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN, 1);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

630

REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_ACK, 1);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

635

REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_ACK, 0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

640

REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_EN, enable ? 1:0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

645

REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_ACK, 1);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

646

REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_ACK, 0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

669

REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_EN, enable ? 1:0);