REG_BIT8
#define C10_PLL0_SSC_EN REG_BIT8(0)
#define C10_PLL0_DIVCLK_EN REG_BIT8(1)
#define C10_PLL0_DIV5CLK_EN REG_BIT8(2)
#define C10_PLL0_WORDDIV2_EN REG_BIT8(3)
#define C10_PLL0_FRACEN REG_BIT8(4)
#define C10_PLL0_PMIX_EN REG_BIT8(5)
#define C10_PLL8_SSC_UP_SPREAD REG_BIT8(5)
#define C10_PLL16_ANA_CPINTGS_L REG_BIT8(7)
#define C10_VDR_CTRL_MSGBUS_ACCESS REG_BIT8(2)
#define C10_VDR_CTRL_MASTER_LANE REG_BIT8(1)
#define C10_VDR_CTRL_UPDATE_CFG REG_BIT8(0)
#define PHY_C10_VDR_OVRD_TX1 REG_BIT8(0)
#define PHY_C10_VDR_OVRD_TX2 REG_BIT8(2)
#define PHY_C20_IS_HDMI_FRL REG_BIT8(7)
#define PHY_C20_IS_DP REG_BIT8(6)
#define PHY_C20_CONTEXT_TOGGLE REG_BIT8(0)
transmitter_mask = lane_reversal ? REG_BIT8(3) : REG_BIT8(0);
transmitter_mask = REG_BIT8(0);
transmitter_mask = REG_BIT8(1);
#define LT_PHY_PCLKIN_GATE REG_BIT8(0)
#define LT_PHY_TX_SWING_MASK REG_BIT8(3)
#define LT_PHY_TX_LANE_ENABLE REG_BIT8(0)
#define LT_PHY_RATE_CONTROL_VDR_UPDATE REG_BIT8(0)