REG_BASE_ADDR
pci_write_config_dword(pcidev, PCI_CONF_MBAR0_SWA, REG_BASE_ADDR);
asd_ha->io_handle[0].swa_base = REG_BASE_ADDR;
#define CHIMINTEN (REG_BASE_ADDR + 0x1C)
#define OVLYDMACTL (REG_BASE_ADDR + 0x20)
#define OVLYDMACNT (REG_BASE_ADDR + 0x24)
#define OVLYDMAADR (REG_BASE_ADDR + 0x28)
#define DMAERR (REG_BASE_ADDR + 0x30)
#define SPIODATA (REG_BASE_ADDR + 0x34)
#define T1CNTRLR (REG_BASE_ADDR + 0x40)
#define T1CMPR (REG_BASE_ADDR + 0x44)
#define T1CNTR (REG_BASE_ADDR + 0x48)
#define T2CNTRLR (REG_BASE_ADDR + 0x4C)
#define T2CMPR (REG_BASE_ADDR + 0x50)
#define T2CNTR (REG_BASE_ADDR + 0x54)
#define CMDCTXBASE (REG_BASE_ADDR + 0x800)
#define DEVCTXBASE (REG_BASE_ADDR + 0x808)
#define CTXDOMAIN (REG_BASE_ADDR + 0x810)
#define DCHCTL (REG_BASE_ADDR + 0x814)
#define DCHREVISION (REG_BASE_ADDR + 0x818)
#define DCHSTATUS (REG_BASE_ADDR + 0x81C)
#define DCHDFIFDEBUG (REG_BASE_ADDR + 0x820)
#define ATOMICSTATCTL (REG_BASE_ADDR + 0x824)
#define ALTCIOADR (REG_BASE_ADDR + 0x828)
#define ASCBPTR (REG_BASE_ADDR + 0x82C)
#define ADDBPTR (REG_BASE_ADDR + 0x82E)
#define ANEWDATA (REG_BASE_ADDR + 0x830)
#define AOLDDATA (REG_BASE_ADDR + 0x834)
#define CTXACCESS (REG_BASE_ADDR + 0x838)
#define COMBIST (REG_BASE_ADDR + 0x00)
#define COMSTAT (REG_BASE_ADDR + 0x04)
#define COMSTATEN (REG_BASE_ADDR + 0x08)
#define SCBPRO (REG_BASE_ADDR + 0x0C)
#define CHIMREQMBX (REG_BASE_ADDR + 0x10)
#define CHIMRSPMBX (REG_BASE_ADDR + 0x14)
#define CHIMINT (REG_BASE_ADDR + 0x18)