arch/mips/kernel/cevt-sb1250.c

130

IOADDR(A_IMR_REGISTER(cpu, R_IMR_INTERRUPT_MAP_BASE) +

arch/mips/sibyte/common/sb_tbprof.c

299

IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +

arch/mips/sibyte/common/sb_tbprof.c

351

IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_TRACE)));

arch/mips/sibyte/sb1250/irq.c

139

pending = __raw_readq(IOADDR(A_IMR_REGISTER(sb1250_irq_owner[irq],

arch/mips/sibyte/sb1250/irq.c

156

IOADDR(A_IMR_REGISTER(cpu,

arch/mips/sibyte/sb1250/irq.c

231

IOADDR(A_IMR_REGISTER(0,

arch/mips/sibyte/sb1250/irq.c

235

IOADDR(A_IMR_REGISTER(1,

arch/mips/sibyte/sb1250/irq.c

248

IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +

arch/mips/sibyte/sb1250/irq.c

251

IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) +

arch/mips/sibyte/sb1250/irq.c

256

IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU)));

arch/mips/sibyte/sb1250/irq.c

258

IOADDR(A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU)));

arch/mips/sibyte/sb1250/irq.c

262

__raw_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK)));

arch/mips/sibyte/sb1250/irq.c

263

__raw_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK)));

arch/mips/sibyte/sb1250/irq.c

281

mask = __raw_readq(IOADDR(A_IMR_REGISTER(cpu,