Symbol: A_IMR_CPU1_BASE
arch/mips/sibyte/sb1250/smp.c
22
IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_SET_CPU)
arch/mips/sibyte/sb1250/smp.c
27
IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_CLR_CPU)
arch/mips/sibyte/sb1250/smp.c
32
IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_CPU)