drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

181

REG_STRUCT[base + reg_num].enable_reg = SRI(reg1, block, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

182

REG_STRUCT[base + reg_num].enable_mask = \

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

184

REG_STRUCT[base + reg_num].enable_value[0] = \

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

186

REG_STRUCT[base + reg_num].enable_value[1] = \

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

188

REG_STRUCT[base + reg_num].ack_reg = SRI(reg2, block, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

189

REG_STRUCT[base + reg_num].ack_mask = \

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

191

REG_STRUCT[base + reg_num].ack_value = \

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

195

REG_STRUCT[base].enable_reg = SRI_DMUB(reg1),\

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

196

REG_STRUCT[base].enable_mask = \

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

198

REG_STRUCT[base].enable_value[0] = \

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

200

REG_STRUCT[base].enable_value[1] = \

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

202

REG_STRUCT[base].ack_reg = SRI_DMUB(reg2),\

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

203

REG_STRUCT[base].ack_mask = \

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

205

REG_STRUCT[base].ack_value = \

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

212

REG_STRUCT[DC_IRQ_SOURCE_HPD1 + reg_num].funcs = &hpd_irq_info_funcs;\

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

213

REG_STRUCT[DC_IRQ_SOURCE_HPD1 + reg_num].status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num);\

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

219

REG_STRUCT[DC_IRQ_SOURCE_HPD1RX + reg_num].status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num);\

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

220

REG_STRUCT[DC_IRQ_SOURCE_HPD1RX + reg_num].funcs = &hpd_rx_irq_info_funcs;\

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

226

REG_STRUCT[DC_IRQ_SOURCE_PFLIP1 + reg_num].funcs = &pflip_irq_info_funcs\

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

235

REG_STRUCT[DC_IRQ_SOURCE_VUPDATE1 + reg_num].funcs = &vupdate_no_lock_irq_info_funcs\

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

241

REG_STRUCT[DC_IRQ_SOURCE_VBLANK1 + reg_num].funcs = &vblank_irq_info_funcs\

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

247

REG_STRUCT[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num].funcs = &vline0_irq_info_funcs\

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

253

REG_STRUCT[DC_IRQ_SOURCE_DMCUB_OUTBOX].funcs = &outbox_irq_info_funcs

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

256

REG_STRUCT[irqno].funcs = &dummy_irq_info_funcs\

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

160

REG_STRUCT[base + reg_num].enable_reg = SRI(reg1, block, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

161

REG_STRUCT[base + reg_num].enable_mask = \

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

163

REG_STRUCT[base + reg_num].enable_value[0] = \

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

165

REG_STRUCT[base + reg_num].enable_value[1] = \

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

167

REG_STRUCT[base + reg_num].ack_reg = SRI(reg2, block, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

168

REG_STRUCT[base + reg_num].ack_mask = \

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

170

REG_STRUCT[base + reg_num].ack_value = \

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

174

REG_STRUCT[base].enable_reg = SRI_DMUB(reg1),\

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

175

REG_STRUCT[base].enable_mask = \

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

177

REG_STRUCT[base].enable_value[0] = \

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

179

REG_STRUCT[base].enable_value[1] = \

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

181

REG_STRUCT[base].ack_reg = SRI_DMUB(reg2),\

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

182

REG_STRUCT[base].ack_mask = \

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

184

REG_STRUCT[base].ack_value = \

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

191

REG_STRUCT[DC_IRQ_SOURCE_HPD1 + reg_num].funcs = &hpd_irq_info_funcs;\

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

192

REG_STRUCT[DC_IRQ_SOURCE_HPD1 + reg_num].status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num);\

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

198

REG_STRUCT[DC_IRQ_SOURCE_HPD1RX + reg_num].status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num);\

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

199

REG_STRUCT[DC_IRQ_SOURCE_HPD1RX + reg_num].funcs = &hpd_rx_irq_info_funcs;\

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

205

REG_STRUCT[DC_IRQ_SOURCE_PFLIP1 + reg_num].funcs = &pflip_irq_info_funcs\

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

214

REG_STRUCT[DC_IRQ_SOURCE_VUPDATE1 + reg_num].funcs = &vupdate_no_lock_irq_info_funcs\

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

220

REG_STRUCT[DC_IRQ_SOURCE_VBLANK1 + reg_num].funcs = &vblank_irq_info_funcs\

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

226

REG_STRUCT[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num].funcs = &vline0_irq_info_funcs\

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

232

REG_STRUCT[DC_IRQ_SOURCE_DMCUB_OUTBOX].funcs = &outbox_irq_info_funcs

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

235

REG_STRUCT[irqno].funcs = &dummy_irq_info_funcs\

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

159

REG_STRUCT[base + reg_num].enable_reg = SRI(reg1, block, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

160

REG_STRUCT[base + reg_num].enable_mask = \

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

162

REG_STRUCT[base + reg_num].enable_value[0] = \

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

164

REG_STRUCT[base + reg_num].enable_value[1] = \

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

166

REG_STRUCT[base + reg_num].ack_reg = SRI(reg2, block, reg_num),\

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

167

REG_STRUCT[base + reg_num].ack_mask = \

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

169

REG_STRUCT[base + reg_num].ack_value = \

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

173

REG_STRUCT[base].enable_reg = SRI_DMUB(reg1),\

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

174

REG_STRUCT[base].enable_mask = \

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

176

REG_STRUCT[base].enable_value[0] = \

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

178

REG_STRUCT[base].enable_value[1] = \

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

180

REG_STRUCT[base].ack_reg = SRI_DMUB(reg2),\

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

181

REG_STRUCT[base].ack_mask = \

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

183

REG_STRUCT[base].ack_value = \

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

190

REG_STRUCT[DC_IRQ_SOURCE_HPD1 + reg_num].funcs = &hpd_irq_info_funcs;\

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

191

REG_STRUCT[DC_IRQ_SOURCE_HPD1 + reg_num].status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num);\

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

197

REG_STRUCT[DC_IRQ_SOURCE_HPD1RX + reg_num].status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num);\

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

198

REG_STRUCT[DC_IRQ_SOURCE_HPD1RX + reg_num].funcs = &hpd_rx_irq_info_funcs;\

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

204

REG_STRUCT[DC_IRQ_SOURCE_PFLIP1 + reg_num].funcs = &pflip_irq_info_funcs\

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

213

REG_STRUCT[DC_IRQ_SOURCE_VUPDATE1 + reg_num].funcs = &vupdate_no_lock_irq_info_funcs\

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

219

REG_STRUCT[DC_IRQ_SOURCE_VBLANK1 + reg_num].funcs = &vblank_irq_info_funcs\

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

225

REG_STRUCT[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num].funcs = &vline0_irq_info_funcs\

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

231

REG_STRUCT[DC_IRQ_SOURCE_DMCUB_OUTBOX].funcs = &outbox_irq_info_funcs

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

234

REG_STRUCT[irqno].funcs = &dummy_irq_info_funcs\

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

119

REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

122

REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

125

REG_STRUCT[id].reg_name = value

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

128

REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

132

REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

136

REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

139

REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

143

REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

150

REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

158

REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

162

REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

170

REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

177

REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

181

REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

191

REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

194

REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

119

REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

122

REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

125

REG_STRUCT[id].reg_name = value

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

128

REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

132

REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

136

REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

139

REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

143

REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

150

REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

158

REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

162

REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

170

REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

174

REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

181

REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

191

REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

194

REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

133

REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

137

REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

140

REG_STRUCT[id].reg_name = value

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

143

REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

147

REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

151

REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

154

REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

158

REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

166

REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

174

REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

178

REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

186

REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

193

REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

197

REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

207

REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

211

REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

113

REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

117

REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

120

REG_STRUCT[id].reg_name = value

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

123

REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

127

REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

131

REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

134

REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

138

REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

146

REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

154

REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

158

REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

166

REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

173

REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

177

REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

187

REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

191

REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

118

REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

122

REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

125

REG_STRUCT[id].reg_name = value

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

128

REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

132

REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

136

REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

139

REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

143

REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

151

REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

159

REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

163

REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

171

REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

178

REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

182

REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

192

REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

196

REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

100

REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

103

REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

106

REG_STRUCT[id].reg_name = value

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

109

REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

113

REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

120

REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

123

REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

126

REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

130

REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

137

REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

145

REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

149

REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

157

REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

161

REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

168

REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

178

REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

181

REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

46

#define DMUB_SR(reg) REG_STRUCT->offset.reg = REG_OFFSET_EXP(reg);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

51

#define DMUB_SF(reg, field) REG_STRUCT->mask.reg##__##field = FD_MASK(reg, field);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

55

#define DMUB_SF(reg, field) REG_STRUCT->shift.reg##__##field = FD_SHIFT(reg, field);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

44

#define DMUB_SR(reg) REG_STRUCT->offset.reg = REG_OFFSET_EXP(reg);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

49

#define DMUB_SF(reg, field) REG_STRUCT->mask.reg##__##field = FD_MASK(reg, field);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

53

#define DMUB_SF(reg, field) REG_STRUCT->shift.reg##__##field = FD_SHIFT(reg, field);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn351.c

21

#define DMUB_SR(reg) REG_STRUCT->offset.reg = REG_OFFSET_EXP(reg);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn351.c

26

#define DMUB_SF(reg, field) REG_STRUCT->mask.reg##__##field = FD_MASK(reg, field);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn351.c

30

#define DMUB_SF(reg, field) REG_STRUCT->shift.reg##__##field = FD_SHIFT(reg, field);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn36.c

21

#define DMUB_SR(reg) REG_STRUCT->offset.reg = REG_OFFSET_EXP(reg);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn36.c

26

#define DMUB_SF(reg, field) REG_STRUCT->mask.reg##__##field = FD_MASK(reg, field);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn36.c

30

#define DMUB_SF(reg, field) REG_STRUCT->shift.reg##__##field = FD_SHIFT(reg, field);