REG_STATUS
*status = qce_read(qce, REG_STATUS);
qce_write(qce, REG_STATUS, 0);
status = lc824206xa_read_reg(data, REG_STATUS);
ret = regmap_read(state->regmap, REG_STATUS, ®val);
ret = regmap_read(state->regmap, REG_STATUS, ®val);
ret = regmap_read(state->regmap, REG_STATUS, ®val);
ret = regmap_read(state->regmap, REG_STATUS, ®val);
error = st1232_ts_read_data(ts, REG_STATUS, 1);
val = lgs8gl5_read_reg(state, REG_STATUS);
u8 flags = lgs8gl5_read_reg(state, REG_STATUS);
ret = s5c73m3_read(state, REG_STATUS, &status);
return s5c73m3_write(state, REG_STATUS, 0x0001);
gs_read_register(gs->pdev, REG_STATUS, ®_value);
ret = gs_read_register(gs->pdev, REG_STATUS, ®_value);
max2165_read_reg(priv, REG_STATUS, &status);
*status = readl(host->base + REG_STATUS);
if (readl(host->base + REG_STATUS) & CARD_DETECT) {
status = readl(host->base + REG_STATUS);
return !!(readl(host->base + REG_STATUS) & WRITE_PROT);
return spinand_read_reg_op(spinand, REG_STATUS, status);
REG_STATUS, spinand->scratchbuf);
while ((ether3_inw(REG_STATUS) & STAT_FIFOEMPTY) == 0) {
while (ether3_inw(REG_STATUS) & (STAT_RXON|STAT_TXON))
while (ether3_inw(REG_STATUS) & (STAT_RXON|STAT_TXON))
ether3_inw(REG_STATUS), ether3_inw(REG_CONFIG1), ether3_inw(REG_CONFIG2));
if (!(ether3_inw(REG_STATUS) & STAT_TXON)) {
status = ether3_inw(REG_STATUS);
if (!(ether3_inw(REG_STATUS) & STAT_RXON)) {
if ((retval = nc_register_read(dev, REG_STATUS, &vp)) < 0) {
retval = nc_register_read(dev, REG_STATUS, &vp);
ret = sbs_read_word_data(chip->client, sbs_data[REG_STATUS].addr);
[REG_STATUS] =
ret = sbs_read_word_data(client, sbs_data[REG_STATUS].addr);
while ((readl(vt8500->base + REG_STATUS) & mask) && --loops)
while (readl_relaxed(qspi->regs + REG_STATUS) & STATUS_RXFIFOEMPTY)
while (readl_relaxed(qspi->regs + REG_STATUS) & STATUS_RXFIFOEMPTY)
while (readl_relaxed(qspi->regs + REG_STATUS) & STATUS_TXFIFOFULL)
while (readl_relaxed(qspi->regs + REG_STATUS) & STATUS_TXFIFOFULL)
while (readl_relaxed(qspi->regs + REG_STATUS) & STATUS_TXFIFOFULL)
if (readl_relaxed(qspi->regs + REG_STATUS) & STATUS_RXAVAILABLE) {
while (readl_relaxed(qspi->regs + REG_STATUS) & STATUS_RXFIFOEMPTY)
while (readl_relaxed(qspi->regs + REG_STATUS) & STATUS_TXFIFOFULL)
while (readl_relaxed(qspi->regs + REG_STATUS) & STATUS_RXFIFOEMPTY)
int intfield = readl_relaxed(qspi->regs + REG_STATUS) & STATUS_MASK;
writel_relaxed(IEN_TXDONE, qspi->regs + REG_STATUS);
writel_relaxed(IEN_RXAVAILABLE, qspi->regs + REG_STATUS);
writel_relaxed(IEN_RXDONE, qspi->regs + REG_STATUS);
return readl_poll_timeout(qspi->regs + REG_STATUS, status,
while (mpfs_spi_read(spi, REG_STATUS) & STATUS_RXFIFO_EMPTY)
while ((i < fifo_max) && !(mpfs_spi_read(spi, REG_STATUS) & STATUS_TXFIFO_FULL)) {
REG_STATUS | REG_ERROR;
mca_modify(cl, REG_STATUS, STATUS_MCLK_EN, STATUS_MCLK_EN);
mca_modify(cl, REG_STATUS, STATUS_MCLK_EN, 0);