Symbol: REG_SIZE
arch/parisc/net/bpf_jit_comp32.c
1487
stack_adjust += NR_SAVED_REGISTERS * REG_SIZE;
arch/parisc/net/bpf_jit_comp32.c
1489
stack_adjust += BPF_JIT_SCRATCH_REGS * REG_SIZE;
arch/parisc/net/bpf_jit_comp32.c
1511
emit(hppa_stw(HPPA_REG_R1, -REG_SIZE, HPPA_REG_SP), ctx); // stw prev_sp,-0x04(sp)
arch/parisc/net/bpf_jit_comp32.c
1525
emit(hppa_stw(HPPA_R(i), -REG_SIZE * (8 + (i-3)), HPPA_REG_SP), ctx); // stw ri,-save_area(sp)
arch/parisc/net/bpf_jit_comp32.c
1602
emit(hppa_ldo(-REG_SIZE * (NR_SAVED_REGISTERS + BPF_JIT_SCRATCH_REGS),
arch/parisc/net/bpf_jit_comp32.c
209
emit(hppa_ldw(-REG_SIZE * (8 + (i-3)), HPPA_REG_SP, HPPA_R(i)), ctx);
arch/parisc/net/bpf_jit_comp32.c
228
emit(hppa_ldw(REG_SIZE * hi(reg) - offset_sp, HPPA_REG_SP, hi(tmp)), ctx);
arch/parisc/net/bpf_jit_comp32.c
229
emit(hppa_ldw(REG_SIZE * lo(reg) - offset_sp, HPPA_REG_SP, lo(tmp)), ctx);
arch/parisc/net/bpf_jit_comp32.c
251
emit(hppa_ldw(REG_SIZE * hi(reg), HPPA_REG_SP, hi(tmp)), ctx);
arch/parisc/net/bpf_jit_comp32.c
264
emit(hppa_stw(hi(src), REG_SIZE * hi(reg), HPPA_REG_SP), ctx);
arch/parisc/net/bpf_jit_comp32.c
265
emit(hppa_stw(lo(src), REG_SIZE * lo(reg), HPPA_REG_SP), ctx);
arch/parisc/net/bpf_jit_comp32.c
284
emit(hppa_ldw(REG_SIZE * lo(reg), HPPA_REG_SP, lo(tmp)), ctx);
arch/parisc/net/bpf_jit_comp32.c
309
emit(hppa_stw(lo(src), REG_SIZE * lo(reg), HPPA_REG_SP), ctx);
arch/parisc/net/bpf_jit_comp32.c
312
emit(hppa_stw(HPPA_REG_ZERO, REG_SIZE * hi(reg), HPPA_REG_SP), ctx);
arch/parisc/net/bpf_jit_comp64.c
1152
emit(hppa64_std_im5 (HPPA_REG_R1, -REG_SIZE, HPPA_REG_SP), ctx);
arch/parisc/net/bpf_jit_comp64.c
1153
emit(hppa64_std_im16(HPPA_REG_RP, -2*REG_SIZE, HPPA_REG_SP), ctx);
arch/parisc/net/bpf_jit_comp64.c
1159
emit(hppa64_std_im16(HPPA_R(i), -REG_SIZE * i, HPPA_REG_SP), ctx);
arch/parisc/net/bpf_jit_comp64.c
236
emit(hppa64_ldd_im16(-REG_SIZE * i, HPPA_REG_SP, HPPA_R(i)), ctx);
arch/parisc/net/bpf_jit_comp64.c
240
emit(hppa64_ldd_im16(-2*REG_SIZE, HPPA_REG_SP, HPPA_REG_RP), ctx);
arch/parisc/net/bpf_jit_comp64.c
243
emit(hppa64_ldd_im5(-REG_SIZE, HPPA_REG_SP, HPPA_REG_SP), ctx);
drivers/hwmon/ultra45_env.c
265
p->regs = of_ioremap(&op->resource[0], 0, REG_SIZE, "pic16f747");
drivers/hwmon/ultra45_env.c
289
of_iounmap(&op->resource[0], p->regs, REG_SIZE);
drivers/hwmon/ultra45_env.c
301
of_iounmap(&op->resource[0], p->regs, REG_SIZE);
drivers/irqchip/qcom-irq-combiner.c
186
(reg->bit_width > REG_SIZE)) {
drivers/irqchip/qcom-irq-combiner.c
192
vaddr = devm_ioremap(ctx->dev, reg->address, REG_SIZE);
drivers/irqchip/qcom-irq-combiner.c
41
return reg * REG_SIZE + bit;
drivers/irqchip/qcom-irq-combiner.c
82
struct combiner_reg *reg = combiner->regs + data->hwirq / REG_SIZE;
drivers/irqchip/qcom-irq-combiner.c
84
clear_bit(data->hwirq % REG_SIZE, &reg->enabled);
drivers/irqchip/qcom-irq-combiner.c
90
struct combiner_reg *reg = combiner->regs + data->hwirq / REG_SIZE;
drivers/irqchip/qcom-irq-combiner.c
92
set_bit(data->hwirq % REG_SIZE, &reg->enabled);
drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c
1437
sizeof(ram_line) / REG_SIZE);
drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c
1555
sizeof(ram_line) / REG_SIZE);
drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c
1563
sizeof(ram_line) / REG_SIZE);
drivers/pinctrl/qcom/pinctrl-glymur.c
20
.ctl_reg = REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-glymur.c
21
.io_reg = 0x4 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-glymur.c
22
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-glymur.c
23
.intr_status_reg = 0xc + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-glymur.c
24
.intr_target_reg = 0x8 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-ipq5018.c
31
.ctl_reg = REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-ipq5018.c
32
.io_reg = 0x4 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-ipq5018.c
33
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-ipq5018.c
34
.intr_status_reg = 0xc + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-ipq5018.c
35
.intr_target_reg = 0x8 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-ipq5332.c
31
.ctl_reg = REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-ipq5332.c
32
.io_reg = 0x4 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-ipq5332.c
33
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-ipq5332.c
34
.intr_status_reg = 0xc + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-ipq5332.c
35
.intr_target_reg = 0x8 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-ipq5424.c
32
.ctl_reg = REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-ipq5424.c
33
.io_reg = 0x4 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-ipq5424.c
34
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-ipq5424.c
35
.intr_status_reg = 0xc + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-ipq5424.c
36
.intr_target_reg = 0x8 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-ipq6018.c
31
.ctl_reg = REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-ipq6018.c
32
.io_reg = 0x4 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-ipq6018.c
33
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-ipq6018.c
34
.intr_status_reg = 0xc + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-ipq6018.c
35
.intr_target_reg = 0x8 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-ipq8074.c
31
.ctl_reg = REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-ipq8074.c
32
.io_reg = 0x4 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-ipq8074.c
33
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-ipq8074.c
34
.intr_status_reg = 0xc + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-ipq8074.c
35
.intr_target_reg = 0x8 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-ipq9574.c
31
.ctl_reg = REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-ipq9574.c
32
.io_reg = 0x4 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-ipq9574.c
33
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-ipq9574.c
34
.intr_status_reg = 0xc + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-ipq9574.c
35
.intr_target_reg = 0x8 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-kaanapali.c
33
.ctl_reg = REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-kaanapali.c
34
.io_reg = 0x4 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-kaanapali.c
35
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-kaanapali.c
36
.intr_status_reg = 0xc + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-kaanapali.c
37
.intr_target_reg = 0x8 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-milos.c
35
.ctl_reg = REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-milos.c
36
.io_reg = 0x4 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-milos.c
37
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-milos.c
38
.intr_status_reg = 0xc + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-milos.c
39
.intr_target_reg = 0x8 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-msm8909.c
32
.ctl_reg = REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-msm8909.c
33
.io_reg = 0x4 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-msm8909.c
34
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-msm8909.c
35
.intr_status_reg = 0xc + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-msm8909.c
36
.intr_target_reg = 0x8 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-msm8976.c
34
.ctl_reg = REG_BASE + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-msm8976.c
35
.io_reg = REG_BASE + 0x4 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-msm8976.c
36
.intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-msm8976.c
37
.intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-msm8976.c
38
.intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-msm8996.c
32
.ctl_reg = REG_BASE + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-msm8996.c
33
.io_reg = REG_BASE + 0x4 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-msm8996.c
34
.intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-msm8996.c
35
.intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-msm8996.c
36
.intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-qcm2290.c
32
.ctl_reg = REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-qcm2290.c
33
.io_reg = 0x4 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-qcm2290.c
34
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-qcm2290.c
35
.intr_status_reg = 0xc + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-qcm2290.c
36
.intr_target_reg = 0x8 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-qcs8300.c
33
.ctl_reg = REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-qcs8300.c
34
.io_reg = 0x4 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-qcs8300.c
35
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-qcs8300.c
36
.intr_status_reg = 0xc + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-qcs8300.c
37
.intr_target_reg = 0x8 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-qdu1000.c
34
.ctl_reg = REG_BASE + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-qdu1000.c
35
.io_reg = REG_BASE + 0x4 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-qdu1000.c
36
.intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-qdu1000.c
37
.intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-qdu1000.c
38
.intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sa8775p.c
33
.ctl_reg = REG_BASE + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sa8775p.c
34
.io_reg = REG_BASE + 0x4 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sa8775p.c
35
.intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sa8775p.c
36
.intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sa8775p.c
37
.intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sar2130p.c
33
.ctl_reg = REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sar2130p.c
34
.io_reg = 0x4 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sar2130p.c
35
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sar2130p.c
36
.intr_status_reg = 0xc + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sar2130p.c
37
.intr_target_reg = 0x8 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sc8180x.c
59
.ctl_reg = REG_SIZE * id + offset, \
drivers/pinctrl/qcom/pinctrl-sc8180x.c
60
.io_reg = REG_SIZE * id + 0x4 + offset, \
drivers/pinctrl/qcom/pinctrl-sc8180x.c
61
.intr_cfg_reg = REG_SIZE * id + 0x8 + offset, \
drivers/pinctrl/qcom/pinctrl-sc8180x.c
62
.intr_status_reg = REG_SIZE * id + 0xc + offset,\
drivers/pinctrl/qcom/pinctrl-sc8180x.c
63
.intr_target_reg = REG_SIZE * id + 0x8 + offset,\
drivers/pinctrl/qcom/pinctrl-sc8280xp.c
30
.ctl_reg = REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sc8280xp.c
31
.io_reg = 0x4 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sc8280xp.c
32
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sc8280xp.c
33
.intr_status_reg = 0xc + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sc8280xp.c
34
.intr_target_reg = 0x8 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sdm660.c
45
.ctl_reg = REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sdm660.c
46
.io_reg = 0x4 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sdm660.c
47
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sdm660.c
48
.intr_status_reg = 0xc + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sdm660.c
49
.intr_target_reg = 0x8 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sdm670.c
36
.ctl_reg = base + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sdm670.c
37
.io_reg = base + 0x4 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sdm670.c
38
.intr_cfg_reg = base + 0x8 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sdm670.c
39
.intr_status_reg = base + 0xc + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sdm670.c
40
.intr_target_reg = base + 0x8 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sdm845.c
36
.ctl_reg = base + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sdm845.c
37
.io_reg = base + 0x4 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sdm845.c
38
.intr_cfg_reg = base + 0x8 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sdm845.c
39
.intr_status_reg = base + 0xc + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sdm845.c
40
.intr_target_reg = base + 0x8 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sdx55.c
32
.ctl_reg = REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sdx55.c
33
.io_reg = 0x4 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sdx55.c
34
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sdx55.c
35
.intr_status_reg = 0xc + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sdx55.c
36
.intr_target_reg = 0x8 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sdx65.c
32
.ctl_reg = REG_BASE + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sdx65.c
33
.io_reg = REG_BASE + 0x4 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sdx65.c
34
.intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sdx65.c
35
.intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sdx65.c
36
.intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sdx75.c
18
.ctl_reg = REG_BASE + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sdx75.c
19
.io_reg = REG_BASE + 0x4 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sdx75.c
20
.intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sdx75.c
21
.intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sdx75.c
22
.intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sm4450.c
32
.ctl_reg = REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sm4450.c
33
.io_reg = 0x4 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sm4450.c
34
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sm4450.c
35
.intr_status_reg = 0xc + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sm4450.c
36
.intr_target_reg = 0x8 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sm6350.c
32
.ctl_reg = REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sm6350.c
33
.io_reg = 0x4 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sm6350.c
34
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sm6350.c
35
.intr_status_reg = 0xc + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sm6350.c
36
.intr_target_reg = 0x8 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sm6375.c
33
.ctl_reg = REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sm6375.c
34
.io_reg = REG_SIZE * id + 0x4, \
drivers/pinctrl/qcom/pinctrl-sm6375.c
35
.intr_cfg_reg = REG_SIZE * id + 0x8, \
drivers/pinctrl/qcom/pinctrl-sm6375.c
36
.intr_status_reg = REG_SIZE * id + 0xc, \
drivers/pinctrl/qcom/pinctrl-sm6375.c
37
.intr_target_reg = REG_SIZE * id + 0x8, \
drivers/pinctrl/qcom/pinctrl-sm7150.c
46
.ctl_reg = REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sm7150.c
47
.io_reg = 0x4 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sm7150.c
48
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sm7150.c
49
.intr_status_reg = 0xc + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sm7150.c
50
.intr_target_reg = 0x8 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sm8250.c
43
.ctl_reg = REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sm8250.c
44
.io_reg = REG_SIZE * id + 0x4, \
drivers/pinctrl/qcom/pinctrl-sm8250.c
45
.intr_cfg_reg = REG_SIZE * id + 0x8, \
drivers/pinctrl/qcom/pinctrl-sm8250.c
46
.intr_status_reg = REG_SIZE * id + 0xc, \
drivers/pinctrl/qcom/pinctrl-sm8250.c
47
.intr_target_reg = REG_SIZE * id + 0x8, \
drivers/pinctrl/qcom/pinctrl-sm8350.c
33
.ctl_reg = REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sm8350.c
34
.io_reg = REG_SIZE * id + 0x4, \
drivers/pinctrl/qcom/pinctrl-sm8350.c
35
.intr_cfg_reg = REG_SIZE * id + 0x8, \
drivers/pinctrl/qcom/pinctrl-sm8350.c
36
.intr_status_reg = REG_SIZE * id + 0xc, \
drivers/pinctrl/qcom/pinctrl-sm8350.c
37
.intr_target_reg = REG_SIZE * id + 0x8, \
drivers/pinctrl/qcom/pinctrl-sm8450.c
33
.ctl_reg = REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sm8450.c
34
.io_reg = 0x4 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sm8450.c
35
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sm8450.c
36
.intr_status_reg = 0xc + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sm8450.c
37
.intr_target_reg = 0x8 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sm8550.c
34
.ctl_reg = REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sm8550.c
35
.io_reg = 0x4 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sm8550.c
36
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sm8550.c
37
.intr_status_reg = 0xc + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sm8550.c
38
.intr_target_reg = 0x8 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sm8650.c
35
.ctl_reg = REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sm8650.c
36
.io_reg = 0x4 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sm8650.c
37
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sm8650.c
38
.intr_status_reg = 0xc + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sm8650.c
39
.intr_target_reg = 0x8 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sm8750.c
34
.ctl_reg = REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sm8750.c
35
.io_reg = 0x4 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sm8750.c
36
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sm8750.c
37
.intr_status_reg = 0xc + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-sm8750.c
38
.intr_target_reg = 0x8 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-x1e80100.c
32
.ctl_reg = REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-x1e80100.c
33
.io_reg = 0x4 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-x1e80100.c
34
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-x1e80100.c
35
.intr_status_reg = 0xc + REG_SIZE * id, \
drivers/pinctrl/qcom/pinctrl-x1e80100.c
36
.intr_target_reg = 0x8 + REG_SIZE * id, \
include/sound/emu10k1.h
62
#define REG_MASK0(r) ((1U << REG_SIZE(r)) - 1U)
sound/pci/emu10k1/io.c
640
const u32 quart = 1U << (REG_SIZE(WC_CURRENTCHANNEL) - 2);
sound/soc/tegra/tegra210_mvc.h
94
#define TEGRA210_MVC_REG_OFFSET(reg, i) (reg + (REG_SIZE * i))
sound/soc/tegra/tegra210_mvc.h
96
#define TEGRA210_MVC_GET_CHAN(reg, base) (((reg) - (base)) / REG_SIZE)