drivers/accel/ivpu/ivpu_hw_btrs.c

222

val = REG_SET_FLD_NUM(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD0, MIN_RATIO, wp->min, val);

drivers/accel/ivpu/ivpu_hw_btrs.c

223

val = REG_SET_FLD_NUM(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD0, MAX_RATIO, wp->max, val);

drivers/accel/ivpu/ivpu_hw_btrs.c

227

val = REG_SET_FLD_NUM(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD1, TARGET_RATIO, wp->target, val);

drivers/accel/ivpu/ivpu_hw_btrs.c

228

val = REG_SET_FLD_NUM(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD1, EPP, PLL_EPP_DEFAULT, val);

drivers/accel/ivpu/ivpu_hw_btrs.c

232

val = REG_SET_FLD_NUM(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD2, CONFIG, wp->cfg, val);

drivers/accel/ivpu/ivpu_hw_btrs.c

245

val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD0, MIN_RATIO, wp->min, val);

drivers/accel/ivpu/ivpu_hw_btrs.c

246

val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD0, MAX_RATIO, wp->max, val);

drivers/accel/ivpu/ivpu_hw_btrs.c

250

val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD1, TARGET_RATIO, wp->target, val);

drivers/accel/ivpu/ivpu_hw_btrs.c

251

val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD1, EPP, wp->epp, val);

drivers/accel/ivpu/ivpu_hw_btrs.c

255

val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD2, CONFIG, wp->cfg, val);

drivers/accel/ivpu/ivpu_hw_btrs.c

256

val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD2, CDYN, wp->cdyn, val);

drivers/accel/ivpu/ivpu_hw_btrs.c

776

val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_PCODE_MAILBOX_STATUS, CMD, DCT_REQ, val);

drivers/accel/ivpu/ivpu_hw_btrs.c

777

val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_PCODE_MAILBOX_STATUS, PARAM1, cmd, val);

drivers/accel/ivpu/ivpu_hw_btrs.c

778

val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_PCODE_MAILBOX_STATUS, PARAM2, active_percent, val);

drivers/accel/ivpu/ivpu_hw_ip.c

275

val = REG_SET_FLD_NUM(VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY, POST_DLY, post, val);

drivers/accel/ivpu/ivpu_hw_ip.c

276

val = REG_SET_FLD_NUM(VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY, POST1_DLY, post1, val);

drivers/accel/ivpu/ivpu_hw_ip.c

277

val = REG_SET_FLD_NUM(VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY, POST2_DLY, post2, val);

drivers/accel/ivpu/ivpu_hw_ip.c

281

val = REG_SET_FLD_NUM(VPU_50XX_HOST_SS_AON_PWR_ISLAND_STATUS_DLY, STATUS_DLY, status, val);