drivers/accel/ivpu/ivpu_hw_btrs.c

236

val = REG_SET_FLD(VPU_HW_BTRS_MTL_WP_REQ_CMD, SEND, val);

drivers/accel/ivpu/ivpu_hw_btrs.c

260

val = REG_SET_FLD(VPU_HW_BTRS_LNL_WP_REQ_CMD, SEND, val);

drivers/accel/ivpu/ivpu_hw_btrs.c

389

val = REG_SET_FLD(VPU_HW_BTRS_MTL_VPU_D0I3_CONTROL, I3, val);

drivers/accel/ivpu/ivpu_hw_btrs.c

414

val = REG_SET_FLD(VPU_HW_BTRS_LNL_D0I3_CONTROL, I3, val);

drivers/accel/ivpu/ivpu_hw_btrs.c

492

val = REG_SET_FLD(VPU_HW_BTRS_MTL_VPU_IP_RESET, TRIGGER, val);

drivers/accel/ivpu/ivpu_hw_btrs.c

516

val = REG_SET_FLD(VPU_HW_BTRS_LNL_IP_RESET, TRIGGER, val);

drivers/accel/ivpu/ivpu_hw_btrs.c

544

val = REG_SET_FLD(VPU_HW_BTRS_LNL_VPU_STATUS, PERF_CLK, val);

drivers/accel/ivpu/ivpu_hw_btrs.c

559

val = REG_SET_FLD(VPU_HW_BTRS_LNL_VPU_STATUS, DISABLE_CLK_RELINQUISH, val);

drivers/accel/ivpu/ivpu_hw_ip.c

234

val = REG_SET_FLD(VPU_37XX_HOST_SS_AON_VPU_IDLE_GEN, EN, val);

drivers/accel/ivpu/ivpu_hw_ip.c

246

val = REG_SET_FLD(VPU_40XX_HOST_SS_AON_IDLE_GEN, EN, val);

drivers/accel/ivpu/ivpu_hw_ip.c

290

val = REG_SET_FLD(VPU_37XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, MSS_CPU, val);

drivers/accel/ivpu/ivpu_hw_ip.c

302

val = REG_SET_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, CSS_CPU, val);

drivers/accel/ivpu/ivpu_hw_ip.c

314

val = REG_SET_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0, CSS_CPU, val);

drivers/accel/ivpu/ivpu_hw_ip.c

326

val = REG_SET_FLD(VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0, MSS_CPU, val);

drivers/accel/ivpu/ivpu_hw_ip.c

364

val = REG_SET_FLD(VPU_37XX_HOST_SS_AON_PWR_ISO_EN0, MSS_CPU, val);

drivers/accel/ivpu/ivpu_hw_ip.c

376

val = REG_SET_FLD(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0, CSS_CPU, val);

drivers/accel/ivpu/ivpu_hw_ip.c

401

val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, TOP_NOC, val);

drivers/accel/ivpu/ivpu_hw_ip.c

402

val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, DSS_MAS, val);

drivers/accel/ivpu/ivpu_hw_ip.c

403

val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, MSS_MAS, val);

drivers/accel/ivpu/ivpu_hw_ip.c

418

val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, TOP_NOC, val);

drivers/accel/ivpu/ivpu_hw_ip.c

419

val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, DSS_MAS, val);

drivers/accel/ivpu/ivpu_hw_ip.c

420

val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, CSS_MAS, val);

drivers/accel/ivpu/ivpu_hw_ip.c

448

val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, TOP_NOC, val);

drivers/accel/ivpu/ivpu_hw_ip.c

449

val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, DSS_MAS, val);

drivers/accel/ivpu/ivpu_hw_ip.c

450

val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, MSS_MAS, val);

drivers/accel/ivpu/ivpu_hw_ip.c

465

val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, TOP_NOC, val);

drivers/accel/ivpu/ivpu_hw_ip.c

466

val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, DSS_MAS, val);

drivers/accel/ivpu/ivpu_hw_ip.c

467

val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, CSS_MAS, val);

drivers/accel/ivpu/ivpu_hw_ip.c

495

val = REG_SET_FLD(VPU_37XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, val);

drivers/accel/ivpu/ivpu_hw_ip.c

506

val = REG_SET_FLD(VPU_40XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, val);

drivers/accel/ivpu/ivpu_hw_ip.c

544

val = REG_SET_FLD(VPU_40XX_TOP_NOC_QREQN, CPU_CTRL, val);

drivers/accel/ivpu/ivpu_hw_ip.c

545

val = REG_SET_FLD(VPU_40XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, val);

drivers/accel/ivpu/ivpu_hw_ip.c

559

val = REG_SET_FLD(VPU_37XX_TOP_NOC_QREQN, CPU_CTRL, val);

drivers/accel/ivpu/ivpu_hw_ip.c

560

val = REG_SET_FLD(VPU_37XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, val);

drivers/accel/ivpu/ivpu_hw_ip.c

671

val = REG_SET_FLD(VPU_37XX_HOST_SS_AON_DPU_ACTIVE, DPU_ACTIVE, val);

drivers/accel/ivpu/ivpu_hw_ip.c

752

val = REG_SET_FLD(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES, NOSNOOP_OVERRIDE_EN, val);

drivers/accel/ivpu/ivpu_hw_ip.c

758

val = REG_SET_FLD(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES, AR_NOSNOOP_OVERRIDE, val);

drivers/accel/ivpu/ivpu_hw_ip.c

76

val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_CLR, TOP_NOC, val);

drivers/accel/ivpu/ivpu_hw_ip.c

767

val = REG_SET_FLD(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, SNOOP_OVERRIDE_EN, val);

drivers/accel/ivpu/ivpu_hw_ip.c

768

val = REG_SET_FLD(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, AW_SNOOP_OVERRIDE, val);

drivers/accel/ivpu/ivpu_hw_ip.c

77

val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_CLR, DSS_MAS, val);

drivers/accel/ivpu/ivpu_hw_ip.c

771

val = REG_SET_FLD(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, AR_SNOOP_OVERRIDE, val);

drivers/accel/ivpu/ivpu_hw_ip.c

78

val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_CLR, MSS_MAS, val);

drivers/accel/ivpu/ivpu_hw_ip.c

790

val = REG_SET_FLD(VPU_37XX_HOST_IF_TBU_MMUSSIDV, TBU0_AWMMUSSIDV, val);

drivers/accel/ivpu/ivpu_hw_ip.c

791

val = REG_SET_FLD(VPU_37XX_HOST_IF_TBU_MMUSSIDV, TBU0_ARMMUSSIDV, val);

drivers/accel/ivpu/ivpu_hw_ip.c

792

val = REG_SET_FLD(VPU_37XX_HOST_IF_TBU_MMUSSIDV, TBU2_AWMMUSSIDV, val);

drivers/accel/ivpu/ivpu_hw_ip.c

793

val = REG_SET_FLD(VPU_37XX_HOST_IF_TBU_MMUSSIDV, TBU2_ARMMUSSIDV, val);

drivers/accel/ivpu/ivpu_hw_ip.c

802

val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU0_AWMMUSSIDV, val);

drivers/accel/ivpu/ivpu_hw_ip.c

803

val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU0_ARMMUSSIDV, val);

drivers/accel/ivpu/ivpu_hw_ip.c

804

val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU1_AWMMUSSIDV, val);

drivers/accel/ivpu/ivpu_hw_ip.c

805

val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU1_ARMMUSSIDV, val);

drivers/accel/ivpu/ivpu_hw_ip.c

806

val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU2_AWMMUSSIDV, val);

drivers/accel/ivpu/ivpu_hw_ip.c

807

val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU2_ARMMUSSIDV, val);

drivers/accel/ivpu/ivpu_hw_ip.c

833

val = REG_SET_FLD(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, IRQI_RSTRUN0, val);

drivers/accel/ivpu/ivpu_hw_ip.c

838

val = REG_SET_FLD(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, IRQI_RESUME0, val);

drivers/accel/ivpu/ivpu_hw_ip.c

847

val = REG_SET_FLD(VPU_37XX_HOST_SS_LOADING_ADDRESS_LO, DONE, val);

drivers/accel/ivpu/ivpu_hw_ip.c

878

val = REG_SET_FLD(VPU_40XX_CPU_SS_CPR_NOC_QREQN, TOP_MMIO, val);

drivers/accel/ivpu/ivpu_hw_ip.c

913

val = REG_SET_FLD(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO, DONE, val);

drivers/accel/ivpu/ivpu_mmu.c

599

val = REG_SET_FLD(IVPU_MMU_REG_CR0, CMDQEN, 0);

drivers/accel/ivpu/ivpu_mmu.c

620

val = REG_SET_FLD(IVPU_MMU_REG_CR0, EVTQEN, val);

drivers/accel/ivpu/ivpu_mmu.c

625

val = REG_SET_FLD(IVPU_MMU_REG_CR0, ATSCHK, val);

drivers/accel/ivpu/ivpu_mmu.c

634

val = REG_SET_FLD(IVPU_MMU_REG_CR0, SMMUEN, val);

drivers/accel/ivpu/ivpu_mmu.c

878

val = REG_SET_FLD(IVPU_MMU_REG_CR0, EVTQEN, val);