REG_SET_MASK
r = REG_SET_MASK(r, CCROC_THROT_PSKIP_RAMP_DURATION_MASK, 0xff);
r = REG_SET_MASK(r, CCROC_THROT_PSKIP_RAMP_STEP_MASK, 0xf);
r = REG_SET_MASK(r, CCROC_THROT_PSKIP_CTRL_ENB_MASK, 1);
r = REG_SET_MASK(r, CCROC_THROT_PSKIP_CTRL_DIVIDEND_MASK, dividend);
r = REG_SET_MASK(r, CCROC_THROT_PSKIP_CTRL_DIVISOR_MASK, 0xff);
r = REG_SET_MASK(r, THROT_PSKIP_CTRL_ENABLE_MASK, 1);
r = REG_SET_MASK(r, THROT_PSKIP_CTRL_VECT_CPU_MASK, throt_vect);
r = REG_SET_MASK(r, THROT_PSKIP_CTRL_VECT2_CPU_MASK, throt_vect);
r = REG_SET_MASK(0, THROT_PSKIP_RAMP_SEQ_BYPASS_MODE_MASK, 1);
r = REG_SET_MASK(r, THROT_PSKIP_CTRL_ENABLE_MASK, 1);
r = REG_SET_MASK(r, THROT_PSKIP_CTRL_DIVIDEND_MASK, dividend);
r = REG_SET_MASK(r, THROT_PSKIP_CTRL_DIVISOR_MASK, 0xff);
r = REG_SET_MASK(r, THROT_PSKIP_RAMP_DURATION_MASK, 0xff);
r = REG_SET_MASK(r, THROT_PSKIP_RAMP_STEP_MASK, 0xf);
r = REG_SET_MASK(r, THROT_PSKIP_CTRL_ENABLE_MASK, 1);
r = REG_SET_MASK(r, THROT_PSKIP_CTRL_VECT_GPU_MASK, throt_vect);
r = REG_SET_MASK(0, OC1_CFG_HW_RESTORE_MASK, 1);
r = REG_SET_MASK(r, OC1_CFG_THROTTLE_MODE_MASK, oc->mode);
r = REG_SET_MASK(r, OC1_CFG_ALARM_POLARITY_MASK, oc->active_low);
r = REG_SET_MASK(r, OC1_CFG_EN_THROTTLE_MASK, 1);
r = REG_SET_MASK(0, THROT_PRIORITY_LITE_PRIO_MASK, stc.priority);
r = REG_SET_MASK(0, THROT_DELAY_LITE_DELAY_MASK, 0);
r = REG_SET_MASK(0, THROT_PRIORITY_LOCK_PRIORITY_MASK,
v = REG_SET_MASK(0, THROT_GLOBAL_ENB_MASK, 1);
v = REG_SET_MASK(v, CDIVG_USE_THERM_CONTROLS_MASK, 1);
v = REG_SET_MASK(v, CDIVG_USE_THERM_CONTROLS_MASK, 1);
pdiv = REG_SET_MASK(pdiv, ttgs[i]->pdiv_mask,
hotspot = REG_SET_MASK(hotspot,
r = REG_SET_MASK(r, sg->thermtrip_threshold_mask, temp);
r = REG_SET_MASK(r, sg->thermtrip_enable_mask, 1);
r = REG_SET_MASK(r, sg->thermtrip_any_en_mask, 0);
r = REG_SET_MASK(r, sg->thermctl_lvl0_up_thresh_mask, temp);
r = REG_SET_MASK(r, sg->thermctl_lvl0_dn_thresh_mask, temp);
r = REG_SET_MASK(r, THERMCTL_LVL0_CPU0_CPU_THROT_MASK, cpu_throt);
r = REG_SET_MASK(r, THERMCTL_LVL0_CPU0_GPU_THROT_MASK, gpu_throt);
r = REG_SET_MASK(r, THERMCTL_LVL0_CPU0_EN_MASK, 1);
r = REG_SET_MASK(r, zn->sg->thermctl_isr_mask, TH_INTR_UP_DN_EN);
r = REG_SET_MASK(r, zn->sg->thermctl_isr_mask, 0);
r = REG_SET_MASK(r, THERMCTL_LVL0_CPU0_EN_MASK, 0);
r = REG_SET_MASK(r, zone->sg->thermctl_lvl0_up_thresh_mask, hi);
r = REG_SET_MASK(r, zone->sg->thermctl_lvl0_dn_thresh_mask, lo);
r = REG_SET_MASK(r, THERMCTL_LVL0_CPU0_EN_MASK, 1);
r = REG_SET_MASK(r, OC_INTR_OC1_MASK, 1);
r = REG_SET_MASK(r, OC_INTR_OC2_MASK, 1);
r = REG_SET_MASK(r, OC_INTR_OC3_MASK, 1);
r = REG_SET_MASK(r, OC_INTR_OC4_MASK, 1);