REG_SET_BIT
REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENA);
REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
REG_SET_BIT(ah, 0x9808, 1 << 27);
REG_SET_BIT(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC);
REG_SET_BIT(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1);
REG_SET_BIT(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I);
REG_SET_BIT(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF);
REG_SET_BIT(ah, AR9285_AN_RF2G6, 1 << 0);
REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
REG_SET_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
REG_SET_BIT(ah, AR_PHY_AGC_CONTROL(ah), AR_PHY_AGC_CONTROL_CAL);
REG_SET_BIT(ah, AR_PHY_AGC_CONTROL(ah), AR_PHY_AGC_CONTROL_FLTR_CAL);
REG_SET_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
REG_SET_BIT(ah, AR_PHY_AGC_CONTROL(ah), AR_PHY_AGC_CONTROL_CAL);
REG_SET_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
REG_SET_BIT(ah, AR_PHY_AGC_CONTROL(ah),
REG_SET_BIT(ah, AR_PHY_ADC_CTL,
REG_SET_BIT(ah, AR_PCIE_PM_CTRL(ah), AR_PCIE_PM_CTRL_ENA);
REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
REG_SET_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_FFT_ENA);
REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENABLE);
REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, repeat_bit);
REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN,
REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENABLE);
REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN,
REG_SET_BIT(ah, 0x9864, 0x7f000);
REG_SET_BIT(ah, 0x9924, 0x7f00fe);
REG_SET_BIT(ah, AR_QMISC(qnum), AR_Q_MISC_DCU_EARLY_TERM_REQ);
REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
REG_SET_BIT(ah, AR_PHY_AIC_CTRL_0_B1, AR_PHY_AIC_CAL_CH_VALID_RESET);
REG_SET_BIT(ah, AR_PHY_AIC_CTRL_0_B1, AR_PHY_AIC_CAL_ENABLE);
REG_SET_BIT(ah, AR_PHY_AIC_CTRL_0_B1,
REG_SET_BIT(ah, AR_PHY_AIC_CTRL_0_B1, AR_PHY_AIC_CAL_ENABLE);
REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL,
REG_SET_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0(ah),
REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
REG_SET_BIT(ah, AR_PHY_RX_IQCAL_CORR_B0,
REG_SET_BIT(ah, AR_PHY_AGC_CONTROL(ah),
REG_SET_BIT(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
REG_SET_BIT(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
REG_SET_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0(ah),
REG_SET_BIT(ah, AR_PHY_TIMING4, AR_PHY_TIMING4_DO_CAL);
REG_SET_BIT(ah, AR_PHY_GLB_CONTROL, AR_BTCOEX_CTRL_SPDT_ENABLE);
REG_SET_BIT(ah, AR_PHY_RESTART,
REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV,
REG_SET_BIT(ah, AR_PCIE_PM_CTRL(ah), AR_PCIE_PM_CTRL_ENA);
REG_SET_BIT(ah, AR_MCI_TX_CTRL,
REG_SET_BIT(ah, AR_MCI_TX_CTRL,
REG_SET_BIT(ah, AR_PHY_GLB_CONTROL,
REG_SET_BIT(ah, AR_PHY_GLB_CONTROL, AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL);
REG_SET_BIT(ah, AR_BTCOEX_RC, 0x1);
REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL(ah), AR_GPIO_JTAG_DISABLE);
REG_SET_BIT(ah, AR_GLB_GPIO_CONTROL, ATH_MCI_CONFIG_MCI_OBS_GPIO);
REG_SET_BIT(ah, AR_PHY_TIMING4,
REG_SET_BIT(ah, AR_MCI_TX_CTRL, AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE);
REG_SET_BIT(ah, AR_PHY_GLB_CONTROL,
REG_SET_BIT(ah, AR_BTCOEX_CTRL, AR_BTCOEX_CTRL_MCI_MODE_EN);
REG_SET_BIT(ah, AR_PHY_CHAN_INFO_MEMORY(ah),
REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL,
REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL,
REG_SET_BIT(ah, AR_PHY_CCK_DETECT,
REG_SET_BIT(ah, AR_PHY_RESTART,
REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV,
REG_SET_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_FFT_ENA);
REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENABLE);
REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN,
REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN,
REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN,
REG_SET_BIT(ah, AR_PHY_TEST(ah), PHY_AGC_CLR);
REG_SET_BIT(ah, AR_QMISC(qnum), AR_Q_MISC_DCU_EARLY_TERM_REQ);
REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
REG_SET_BIT(ah, AR_WOW_PATTERN, BIT(pattern_count));
REG_SET_BIT(ah, AR_MAC_PCU_WOW4, BIT(pattern_count - 8));
REG_SET_BIT(ah, AR_PCIE_PM_CTRL(ah), AR_PMCTRL_HOST_PME_EN |
REG_SET_BIT(ah, AR_WOW_PATTERN,
REG_SET_BIT(ah, AR_WOW_COUNT, AR_WOW_AIFS_CNT(AR_WOW_CNT_AIFS_CNT) |
REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
REG_SET_BIT(ah, AR_WOW_BCN_EN, AR_WOW_BEACON_FAIL_EN);
REG_SET_BIT(ah, AR_PCIE_PHY_REG3, BIT(13));
REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL(ah),
REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL(ah),
REG_SET_BIT(ah, AR_PHY_AGC_CONTROL(ah),
REG_SET_BIT(ah, AR_PHY_AGC_CONTROL(ah),
REG_SET_BIT(ah, AR_PHY_AGC_CONTROL(ah), AR_PHY_AGC_CONTROL_NF);
REG_SET_BIT(ah, AR_PHY_AGC_CONTROL(ah), AR_PHY_AGC_CONTROL_NF);
REG_SET_BIT(ah, AR_PHY_AGC_CONTROL(ah),
REG_SET_BIT(ah, AR_PHY_AGC_CONTROL(ah),
REG_SET_BIT(ah, AR_PHY_AGC_CONTROL(ah), AR_PHY_AGC_CONTROL_NF);
REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
REG_SET_BIT(ah, AR_CFG, AR_CFG_HALT_REQ);
REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL(ah), AR_GPIO_JTAG_DISABLE);
REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON);
REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
REG_SET_BIT(ah, AR_RTC_RESET(ah),
REG_SET_BIT(ah, AR_RTC_FORCE_WAKE(ah),
REG_SET_BIT(ah, AR_RTC_FORCE_WAKE(ah),
REG_SET_BIT(ah, AR_TXCFG,
REG_SET_BIT(ah, AR_TIMER_MODE, flags);
REG_SET_BIT(ah, AR_TIMER_MODE,
REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
REG_SET_BIT(ah, AR_DIRECT_CONNECT, AR_DC_AP_STA_EN);
REG_SET_BIT(ah, AR_RESET_TSF, AR_RESET_TSF2_ONCE);
REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
REG_SET_BIT(ah, AR_IMR_S5, mask);
REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
REG_SET_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF);
REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
REG_SET_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_FSP_CBR |
REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_RDYTIME_EXP_POLICY);
REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_POST_FR_BKOFF_DIS);
REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_FRAG_BKOFF_EN);
REG_SET_BIT(ah, AR_QMISC(q),
REG_SET_BIT(ah, AR_DMISC(q),
REG_SET_BIT(ah, AR_QMISC(q),
REG_SET_BIT(ah, AR_DMISC(q),
REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_CBR_INCR_DIS1);
REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_POST_FR_BKOFF_DIS);
REG_SET_BIT(ah, AR_DMISC(q),
REG_SET_BIT(ah, AR_DIAG_SW,
REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_ABORT | AR_DIAG_RX_DIS);