arch/arm/mach-imx/anatop.c

46

REG_SET : REG_CLR;

arch/arm/mach-imx/anatop.c

52

regmap_write(anatop, ANADIG_REG_CORE + (enable ? REG_SET : REG_CLR),

arch/arm/mach-imx/anatop.c

58

regmap_write(anatop, ANADIG_REG_2P5 + (enable ? REG_SET : REG_CLR),

arch/arm/mach-imx/anatop.c

64

regmap_write(anatop, ANADIG_ANA_MISC0 + (enable ? REG_SET : REG_CLR),

drivers/gpu/drm/amd/amdgpu/cikd.h

227

#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))

drivers/gpu/drm/amd/amdgpu/gfx_v12_1_pkt.h

46

#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))

drivers/gpu/drm/amd/amdgpu/nvd.h

46

#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))

drivers/gpu/drm/amd/amdgpu/sid.h

334

#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))

drivers/gpu/drm/amd/amdgpu/soc15d.h

48

#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))

drivers/gpu/drm/amd/amdgpu/vid.h

103

#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))

drivers/gpu/drm/amd/display/dc/dce/dce_audio.c

62

REG_SET(AZALIA_F0_CODEC_ENDPOINT_INDEX, 0,

drivers/gpu/drm/amd/display/dc/dce/dce_audio.c

66

REG_SET(AZALIA_F0_CODEC_ENDPOINT_DATA, 0,

drivers/gpu/drm/amd/display/dc/dce/dce_audio.c

77

REG_SET(AZALIA_F0_CODEC_ENDPOINT_INDEX, 0,

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

252

value = REG_SET(AUX_SW_DATA, value,

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

256

value = REG_SET(AUX_SW_DATA, value,

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

269

value = REG_SET(AUX_SW_DATA, value,

drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c

127

REG_SET(CUR_SURFACE_ADDRESS_HIGH, 0,

drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c

130

REG_SET(CUR_SURFACE_ADDRESS, 0,

drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c

178

REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c

181

REG_SET(DC_LUT_WRITE_EN_MASK, 0, DC_LUT_WRITE_EN_MASK, 0x7);

drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c

193

REG_SET(DC_LUT_RW_INDEX, 0,

drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c

197

REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR,

drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c

200

REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR,

drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c

203

REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR,

drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c

210

REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 0);

drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c

625

REG_SET(DP_CONFIG, 0,

drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c

639

REG_SET(DP_CONFIG, 0,

drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c

714

REG_SET(DP_DPHY_TRAINING_PATTERN_SEL, 0,

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c

506

REG_SET(GRPH_X_START, 0,

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c

509

REG_SET(GRPH_Y_START, 0,

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c

512

REG_SET(GRPH_X_END, 0,

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c

515

REG_SET(GRPH_Y_END, 0,

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c

518

REG_SET(GRPH_PITCH, 0,

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c

521

REG_SET(HW_ROTATION, 0,

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c

536

REG_SET(GRPH_X_START, 0,

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c

539

REG_SET(GRPH_Y_START, 0,

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c

542

REG_SET(GRPH_X_END, 0,

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c

545

REG_SET(GRPH_Y_END, 0,

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c

548

REG_SET(GRPH_PITCH, 0,

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c

760

REG_SET(DMIF_BUFFER_CONTROL, dmif_buffer_control,

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c

797

REG_SET(DMIF_BUFFER_CONTROL, dmif_buffer_control,

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c

819

REG_SET(GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0,

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c

833

REG_SET(GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0,

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c

837

REG_SET(GRPH_PRIMARY_SURFACE_ADDRESS, 0,

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

1249

REG_SET(AFMT_AUDIO_SRC_CONTROL, 0, AFMT_AUDIO_SRC_SELECT, az_inst);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

1349

REG_SET(DP_SEC_AUD_N, 0,

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

1353

REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE,

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

444

REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0);

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1101

REG_SET(GAMUT_REMAP_CONTROL, 0, GRPH_GAMUT_REMAP_MODE, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1103

REG_SET(GAMUT_REMAP_CONTROL, 0, GRPH_GAMUT_REMAP_MODE, 0);

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

120

REG_SET(SCL_BYPASS_CONTROL, 0, SCL_BYPASS_MODE, 0);

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1281

REG_SET(OUTPUT_CSC_CONTROL, 0,

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1286

REG_SET(OUTPUT_CSC_CONTROL, 0,

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1293

REG_SET(OUTPUT_CSC_CONTROL, 0,

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1298

REG_SET(OUTPUT_CSC_CONTROL, 0,

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1304

REG_SET(OUTPUT_CSC_CONTROL, 0,

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1310

REG_SET(OUTPUT_CSC_CONTROL, 0,

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1321

REG_SET(OUTPUT_CSC_CONTROL, 0,

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1326

REG_SET(OUTPUT_CSC_CONTROL, 0,

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1332

REG_SET(OUTPUT_CSC_CONTROL, 0,

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1338

REG_SET(OUTPUT_CSC_CONTROL, 0,

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1347

REG_SET(OUTPUT_CSC_CONTROL, 0,

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

144

REG_SET(SCL_CONTROL, 0, SCL_BOUNDARY_MODE, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1494

REG_SET(REGAMMA_CNTLA_SLOPE_CNTL, 0,

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1497

REG_SET(REGAMMA_CNTLA_END_CNTL1, 0,

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

154

REG_SET(SCL_BYPASS_CONTROL, 0, SCL_BYPASS_MODE, 0);

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

1597

REG_SET(REGAMMA_CONTROL, 0,

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

229

REG_SET(DCFE_MEM_PWR_CTRL, power_ctl, SCL_COEFF_MEM_PWR_DIS, 1);

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

347

REG_SET(SCL_HORZ_FILTER_SCALE_RATIO, 0,

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

350

REG_SET(SCL_VERT_FILTER_SCALE_RATIO, 0,

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

370

REG_SET(SCL_HORZ_FILTER_SCALE_RATIO, 0,

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

373

REG_SET(SCL_VERT_FILTER_SCALE_RATIO, 0,

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

448

REG_SET(SCL_VERT_FILTER_CONTROL, 0,

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

463

REG_SET(SCL_HORZ_FILTER_CONTROL, 0,

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

502

REG_SET(DC_LB_MEMORY_SPLIT, 0,

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

505

REG_SET(DC_LB_MEM_SIZE, 0,

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

713

REG_SET(OUT_ROUND_CONTROL, 0, OUT_ROUND_TRUNC_MODE, depth_bits);

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

980

REG_SET(DENORM_CONTROL, 0, DENORM_MODE, denorm_mode);

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c

103

REG_SET(reg->start_slope_cntl_b, 0,

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c

105

REG_SET(reg->start_slope_cntl_g, 0,

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c

107

REG_SET(reg->start_slope_cntl_r, 0,

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c

110

REG_SET(reg->start_end_cntl1_b, 0,

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c

116

REG_SET(reg->start_end_cntl1_g, 0,

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c

122

REG_SET(reg->start_end_cntl1_r, 0,

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.c

78

REG_SET(PAGE_TABLE_START_ADDR_HI32, 0,

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.c

80

REG_SET(PAGE_TABLE_START_ADDR_LO32, 0,

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.c

83

REG_SET(PAGE_TABLE_END_ADDR_HI32, 0,

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.c

85

REG_SET(PAGE_TABLE_END_ADDR_LO32, 0,

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.c

92

REG_SET(PAGE_TABLE_BASE_ADDR_HI32, 0,

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.c

95

REG_SET(PAGE_TABLE_BASE_ADDR_LO32, 0,

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_afmt.c

136

REG_SET(AFMT_AUDIO_SRC_CONTROL, 0, AFMT_AUDIO_SRC_SELECT, az_inst);

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c

61

REG_SET(reg->start_slope_cntl_b, 0, //linear slope at start of curve

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c

63

REG_SET(reg->start_slope_cntl_g, 0,

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c

65

REG_SET(reg->start_slope_cntl_r, 0,

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c

68

REG_SET(reg->start_end_cntl1_b, 0,

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c

70

REG_SET(reg->start_end_cntl1_g, 0,

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c

72

REG_SET(reg->start_end_cntl1_r, 0,

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c

83

REG_SET(MMHUBBUB_WARMUP_BASE_ADDR_HIGH, 0, MMHUBBUB_WARMUP_BASE_ADDR_HIGH, start_address_shift.high_part);

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c

84

REG_SET(MMHUBBUB_WARMUP_BASE_ADDR_LOW, 0, MMHUBBUB_WARMUP_BASE_ADDR_LOW, start_address_shift.low_part);

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c

85

REG_SET(MMHUBBUB_WARMUP_ADDR_REGION, 0, MMHUBBUB_WARMUP_ADDR_REGION, params->region_size >> 5);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

494

REG_SET(DP_CONFIG, 0,

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

547

REG_SET(DP_DPHY_TRAINING_PATTERN_SEL, 0,

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

1241

REG_SET(AFMT_AUDIO_SRC_CONTROL, 0, AFMT_AUDIO_SRC_SELECT, az_inst);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

1338

REG_SET(DP_SEC_AUD_N, 0,

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

1342

REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE,

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

412

REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0);

drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

291

REG_SET(DP_DSC_BYTES_PER_PIXEL, 0,

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

314

REG_SET(DP_DSC_BYTES_PER_PIXEL, 0,

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

738

REG_SET(DP_SEC_AUD_N, 0,

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

742

REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE,

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

653

REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

247

REG_SET(CM_RGAM_CONTROL, 0, CM_RGAM_LUT_MODE, re_mode);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

385

REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

100

REG_SET(CM_GAMUT_REMAP_CONTROL, 0,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

154

REG_SET(

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

269

REG_SET(CM_TEST_DEBUG_INDEX, 0,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

303

REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

391

REG_SET(CM_MEM_PWR_CTRL, 0,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

406

REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].red_reg);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

407

REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].green_reg);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

408

REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].blue_reg);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

410

REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].delta_red_reg);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

411

REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].delta_green_reg);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

412

REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].delta_blue_reg);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

429

REG_SET(CM_RGAM_LUT_INDEX, 0, CM_RGAM_LUT_INDEX, 0);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

504

REG_SET(CM_ICSC_CONTROL, 0, CM_ICSC_MODE, 0);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

527

REG_SET(CM_TEST_DEBUG_INDEX, 0,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

560

REG_SET(CM_ICSC_CONTROL, 0,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

648

REG_SET(CM_MEM_PWR_CTRL, 0,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

738

REG_SET(CM_DGAM_LUT_INDEX, 0, CM_DGAM_LUT_INDEX, 0);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

740

REG_SET(CM_DGAM_LUT_DATA, 0, CM_DGAM_LUT_DATA, rgb[i].red_reg);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

741

REG_SET(CM_DGAM_LUT_DATA, 0, CM_DGAM_LUT_DATA, rgb[i].green_reg);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

742

REG_SET(CM_DGAM_LUT_DATA, 0, CM_DGAM_LUT_DATA, rgb[i].blue_reg);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

744

REG_SET(CM_DGAM_LUT_DATA, 0,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

746

REG_SET(CM_DGAM_LUT_DATA, 0,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

748

REG_SET(CM_DGAM_LUT_DATA, 0,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

776

REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

787

REG_SET(CM_CONTROL, 0, CM_BYPASS_EN, 1);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

789

REG_SET(CM_CONTROL, 0, CM_BYPASS, 1);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

792

REG_SET(CM_DGAM_CONTROL, 0, CM_DGAM_LUT_MODE, 0);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

835

REG_SET(CM_MEM_PWR_CTRL, 0, SHARED_MEM_PWR_DIS, 1);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

858

REG_SET(CM_IGAM_LUT_SEQ_COLOR, 0, CM_IGAM_LUT_SEQ_COLOR,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

861

REG_SET(CM_IGAM_LUT_SEQ_COLOR, 0, CM_IGAM_LUT_SEQ_COLOR,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

864

REG_SET(CM_IGAM_LUT_SEQ_COLOR, 0, CM_IGAM_LUT_SEQ_COLOR,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

869

REG_SET(CM_MEM_PWR_CTRL, 0, SHARED_MEM_PWR_DIS, 0);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

516

REG_SET(SCL_HORZ_FILTER_SCALE_RATIO, 0,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

519

REG_SET(SCL_VERT_FILTER_SCALE_RATIO, 0,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

522

REG_SET(SCL_HORZ_FILTER_SCALE_RATIO_C, 0,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

525

REG_SET(SCL_VERT_FILTER_SCALE_RATIO_C, 0,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

642

REG_SET(DSCL_CONTROL, 0,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

227

REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

101

REG_SET(CM_DGAM_LUT_DATA, 0, CM_DGAM_LUT_DATA, rgb[i].red_reg);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

102

REG_SET(CM_DGAM_LUT_DATA, 0, CM_DGAM_LUT_DATA, rgb[i].green_reg);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

103

REG_SET(CM_DGAM_LUT_DATA, 0, CM_DGAM_LUT_DATA, rgb[i].blue_reg);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

105

REG_SET(CM_DGAM_LUT_DATA, 0,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

107

REG_SET(CM_DGAM_LUT_DATA, 0,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

109

REG_SET(CM_DGAM_LUT_DATA, 0,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

1098

REG_SET(CM_3DLUT_DATA_30BIT, 0, CM_3DLUT_DATA_30BIT, value);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

1112

REG_SET(CM_3DLUT_INDEX, 0, CM_3DLUT_INDEX, 0);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

170

REG_SET(CM_GAMUT_REMAP_CONTROL, 0,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

207

REG_SET(

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

307

REG_SET(CM_ICSC_CONTROL, 0, CM_ICSC_MODE, 0);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

361

REG_SET(CM_ICSC_CONTROL, 0,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

371

REG_SET(CM_MEM_PWR_CTRL, 0,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

386

REG_SET(CM_BLNDGAM_LUT_INDEX, 0, CM_BLNDGAM_LUT_INDEX, 0);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

398

REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].red_reg);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

399

REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].green_reg);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

400

REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].blue_reg);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

402

REG_SET(CM_BLNDGAM_LUT_DATA, 0,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

404

REG_SET(CM_BLNDGAM_LUT_DATA, 0,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

406

REG_SET(CM_BLNDGAM_LUT_DATA, 0,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

530

REG_SET(CM_BLNDGAM_CONTROL, 0, CM_BLNDGAM_LUT_MODE, 0);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

550

REG_SET(CM_BLNDGAM_CONTROL, 0, CM_BLNDGAM_LUT_MODE,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

582

REG_SET(CM_SHAPER_LUT_DATA, 0, CM_SHAPER_LUT_DATA, red_value);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

583

REG_SET(CM_SHAPER_LUT_DATA, 0, CM_SHAPER_LUT_DATA, green_value);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

584

REG_SET(CM_SHAPER_LUT_DATA, 0, CM_SHAPER_LUT_DATA, blue_value);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

625

REG_SET(CM_SHAPER_LUT_INDEX, 0, CM_SHAPER_LUT_INDEX, 0);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

941

REG_SET(CM_SHAPER_CONTROL, 0, CM_SHAPER_LUT_MODE, 0);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

961

REG_SET(CM_SHAPER_CONTROL, 0, CM_SHAPER_LUT_MODE, next_mode == LUT_RAM_A ? 1:2);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

99

REG_SET(CM_DGAM_LUT_INDEX, 0, CM_DGAM_LUT_INDEX, 0);

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

173

REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

119

REG_SET(CM_POST_CSC_CONTROL, 0, CM_POST_CSC_MODE, 0);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1222

REG_SET(CM_SHAPER_CONTROL, 0, CM_SHAPER_LUT_MODE, 0);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1247

REG_SET(CM_SHAPER_CONTROL, 0, CM_SHAPER_LUT_MODE, next_mode == LUT_RAM_A ? 1:2);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1385

REG_SET(CM_3DLUT_DATA_30BIT, 0, CM_3DLUT_DATA_30BIT, value);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1399

REG_SET(CM_3DLUT_INDEX, 0, CM_3DLUT_INDEX, 0);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

172

REG_SET(CM_POST_CSC_CONTROL, 0,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

648

REG_SET(CM_BLNDGAM_LUT_INDEX, 0, CM_BLNDGAM_LUT_INDEX, 0);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

664

REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].red_reg);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

665

REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_red);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

667

REG_SET(CM_BLNDGAM_LUT_INDEX, 0, CM_BLNDGAM_LUT_INDEX, 0);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

670

REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].red_reg);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

671

REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_red);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

673

REG_SET(CM_BLNDGAM_LUT_INDEX, 0, CM_BLNDGAM_LUT_INDEX, 0);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

676

REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].green_reg);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

677

REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_green);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

679

REG_SET(CM_BLNDGAM_LUT_INDEX, 0, CM_BLNDGAM_LUT_INDEX, 0);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

682

REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].blue_reg);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

683

REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_blue);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

809

REG_SET(CM_BLNDGAM_CONTROL, 0, CM_BLNDGAM_MODE, 0);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

864

REG_SET(CM_SHAPER_LUT_DATA, 0, CM_SHAPER_LUT_DATA, red_value);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

865

REG_SET(CM_SHAPER_LUT_DATA, 0, CM_SHAPER_LUT_DATA, green_value);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

866

REG_SET(CM_SHAPER_LUT_DATA, 0, CM_SHAPER_LUT_DATA, blue_value);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

907

REG_SET(CM_SHAPER_LUT_INDEX, 0, CM_SHAPER_LUT_INDEX, 0);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

102

REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, rgb[i].red_reg);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

104

REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, last_base_value_red);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

106

REG_SET(CM_GAMCOR_LUT_INDEX, 0, CM_GAMCOR_LUT_INDEX, 0);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

111

REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, rgb[i].green_reg);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

113

REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, last_base_value_green);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

115

REG_SET(CM_GAMCOR_LUT_INDEX, 0, CM_GAMCOR_LUT_INDEX, 0);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

120

REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, rgb[i].blue_reg);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

122

REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, last_base_value_blue);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

141

REG_SET(CM_MEM_PWR_CTRL, 0,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

162

REG_SET(CM_BIAS_CR_R, 0, CM_BIAS_CR_R, bias_params->cm_bias_cr_r);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

211

REG_SET(CM_GAMCOR_LUT_INDEX, 0, CM_GAMCOR_LUT_INDEX, 0);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

226

REG_SET(CM_GAMCOR_CONTROL, 0, CM_GAMCOR_MODE, 0);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

232

REG_SET(CM_GAMCOR_CONTROL, 0, CM_GAMCOR_MODE, 2);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

323

REG_SET(CM_GAMUT_REMAP_CONTROL, 0,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

368

REG_SET(

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

94

REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, rgb[i].red_reg);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

96

REG_SET(CM_GAMCOR_LUT_DATA, 0, CM_GAMCOR_LUT_DATA, last_base_value_red);

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

77

REG_SET(FCNV_FP_BIAS_R, 0, FCNV_FP_BIAS_R, 0);

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

78

REG_SET(FCNV_FP_BIAS_G, 0, FCNV_FP_BIAS_G, 0);

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

79

REG_SET(FCNV_FP_BIAS_B, 0, FCNV_FP_BIAS_B, 0);

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

81

REG_SET(FCNV_FP_SCALE_R, 0, FCNV_FP_SCALE_R, 0x1F000);

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

82

REG_SET(FCNV_FP_SCALE_G, 0, FCNV_FP_SCALE_G, 0x1F000);

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

83

REG_SET(FCNV_FP_SCALE_B, 0, FCNV_FP_SCALE_B, 0x1F000);

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

85

REG_SET(FCNV_FP_BIAS_R, 0, FCNV_FP_BIAS_R, params->bias_red);

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

86

REG_SET(FCNV_FP_BIAS_G, 0, FCNV_FP_BIAS_G, params->bias_green);

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

87

REG_SET(FCNV_FP_BIAS_B, 0, FCNV_FP_BIAS_B, params->bias_blue);

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

89

REG_SET(FCNV_FP_SCALE_R, 0, FCNV_FP_SCALE_R, params->scale_red);

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

90

REG_SET(FCNV_FP_SCALE_G, 0, FCNV_FP_SCALE_G, params->scale_green);

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

91

REG_SET(FCNV_FP_SCALE_B, 0, FCNV_FP_SCALE_B, params->scale_blue);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

182

REG_SET(CUR0_MATRIX_MODE, 0, CUR0_MATRIX_MODE, CUR_MATRIX_BYPASS);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

197

REG_SET(CUR0_MATRIX_MODE, 0, CUR0_MATRIX_MODE, CUR_MATRIX_BYPASS);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

231

REG_SET(CUR0_MATRIX_MODE, 0, CUR0_MATRIX_MODE, mode_select);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1112

REG_SET(DSCL_CONTROL, 0,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

522

REG_SET(SCL_HORZ_FILTER_SCALE_RATIO, 0,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

525

REG_SET(SCL_VERT_FILTER_SCALE_RATIO, 0,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

528

REG_SET(SCL_HORZ_FILTER_SCALE_RATIO_C, 0,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

531

REG_SET(SCL_VERT_FILTER_SCALE_RATIO_C, 0,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

563

REG_SET(SCL_HORZ_FILTER_SCALE_RATIO, 0,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

566

REG_SET(SCL_VERT_FILTER_SCALE_RATIO, 0,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

569

REG_SET(SCL_HORZ_FILTER_SCALE_RATIO_C, 0,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

572

REG_SET(SCL_VERT_FILTER_SCALE_RATIO_C, 0,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

931

REG_SET(ISHARP_DELTA_INDEX, 0,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

935

REG_SET(ISHARP_DELTA_DATA, 0,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

591

REG_SET(DSC_DEBUG_CONTROL, 0,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

620

REG_SET(DSCC_CONFIG1, 0,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

659

REG_SET(DSCC_PPS_CONFIG4, 0,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

205

REG_SET(DSC_DEBUG_CONTROL, 0,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

234

REG_SET(DSCC_CONFIG1, 0,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

273

REG_SET(DSCC_PPS_CONFIG4, 0,

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

183

REG_SET(DWB_OGAM_LUT_INDEX, 0, DWB_OGAM_LUT_INDEX, 0);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

198

REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, rgb[i].red_reg);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

200

REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, last_base_value_red);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

208

REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, rgb[i].red_reg);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

210

REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, last_base_value_red);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

212

REG_SET(DWB_OGAM_LUT_INDEX, 0, DWB_OGAM_LUT_INDEX, 0);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

218

REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, rgb[i].green_reg);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

220

REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, last_base_value_green);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

222

REG_SET(DWB_OGAM_LUT_INDEX, 0, DWB_OGAM_LUT_INDEX, 0);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

228

REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, rgb[i].blue_reg);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

230

REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, last_base_value_blue);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

242

REG_SET(DWB_OGAM_CONTROL, 0, DWB_OGAM_MODE, 0);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

249

REG_SET(DWB_OGAM_CONTROL, 0, DWB_OGAM_MODE, 2);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

311

REG_SET(DWB_GAMUT_REMAP_MODE, 0,

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

350

REG_SET(DWB_GAMUT_REMAP_MODE, 0,

drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c

118

REG_SET(gpio.MASK_reg, regval,

drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c

127

REG_SET(gpio.MASK_reg, regval,

drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c

163

REG_SET(gpio.MASK_reg, regval,

drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c

99

REG_SET(gpio.MASK_reg, regval, DC_GPIO_DDC1DATA_PD_EN, 1);

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

213

REG_SET(DP_DPHY_SYM32_TP_CUSTOM0, 0, TP_CUSTOM, tp_custom);

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

215

REG_SET(DP_DPHY_SYM32_TP_CUSTOM1, 0, TP_CUSTOM, tp_custom);

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

217

REG_SET(DP_DPHY_SYM32_TP_CUSTOM2, 0, TP_CUSTOM, tp_custom);

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

219

REG_SET(DP_DPHY_SYM32_TP_CUSTOM3, 0, TP_CUSTOM, tp_custom);

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

221

REG_SET(DP_DPHY_SYM32_TP_CUSTOM4, 0, TP_CUSTOM, tp_custom);

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

223

REG_SET(DP_DPHY_SYM32_TP_CUSTOM5, 0, TP_CUSTOM, tp_custom);

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

225

REG_SET(DP_DPHY_SYM32_TP_CUSTOM6, 0, TP_CUSTOM, tp_custom);

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

227

REG_SET(DP_DPHY_SYM32_TP_CUSTOM7, 0, TP_CUSTOM, tp_custom);

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

229

REG_SET(DP_DPHY_SYM32_TP_CUSTOM8, 0, TP_CUSTOM, tp_custom);

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

231

REG_SET(DP_DPHY_SYM32_TP_CUSTOM9, 0, TP_CUSTOM, tp_custom);

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

233

REG_SET(DP_DPHY_SYM32_TP_CUSTOM10, 0, TP_CUSTOM, tp_custom);

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_link_encoder.c

248

REG_SET(DP_DPHY_SYM32_TP_SQ_PULSE, 0,

drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c

736

REG_SET(DP_SYM32_ENC_HBLANK_CONTROL, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

259

REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

284

REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

309

REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

334

REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

375

REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

391

REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

408

REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

424

REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

441

REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

457

REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

474

REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

490

REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

520

REG_SET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

537

REG_SET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

554

REG_SET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

571

REG_SET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

400

REG_SET(DCN_VM_FB_LOCATION_BASE, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

402

REG_SET(DCN_VM_FB_LOCATION_TOP, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

404

REG_SET(DCN_VM_FB_OFFSET, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

406

REG_SET(DCN_VM_AGP_BOT, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

408

REG_SET(DCN_VM_AGP_TOP, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

410

REG_SET(DCN_VM_AGP_BASE, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

413

REG_SET(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

415

REG_SET(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

622

REG_SET(DCHUBBUB_ARB_SAT_LEVEL, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn201/dcn201_hubbub.c

68

REG_SET(DCHUBBUB_ARB_SAT_LEVEL, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

113

REG_SET(DCN_VM_FB_LOCATION_BASE, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

115

REG_SET(DCN_VM_FB_LOCATION_TOP, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

117

REG_SET(DCN_VM_FB_OFFSET, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

119

REG_SET(DCN_VM_AGP_BOT, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

121

REG_SET(DCN_VM_AGP_TOP, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

123

REG_SET(DCN_VM_AGP_BASE, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

172

REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

182

REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

192

REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

217

REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

227

REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

237

REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

262

REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

272

REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

282

REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

307

REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

317

REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

327

REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

605

REG_SET(DCHUBBUB_ARB_SAT_LEVEL, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

127

REG_SET(DCHUBBUB_ARB_SAT_LEVEL, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

70

REG_SET(DCN_VM_FB_LOCATION_BASE, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

72

REG_SET(DCN_VM_FB_LOCATION_TOP, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

74

REG_SET(DCN_VM_FB_OFFSET, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

76

REG_SET(DCN_VM_AGP_BOT, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

78

REG_SET(DCN_VM_AGP_TOP, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

80

REG_SET(DCN_VM_AGP_BASE, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

189

REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

203

REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

213

REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

223

REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

233

REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

247

REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

257

REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

267

REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

277

REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

291

REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

301

REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

311

REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

321

REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

335

REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

345

REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

355

REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

381

REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

397

REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

413

REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

429

REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

446

REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

462

REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

478

REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

494

REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

511

REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

527

REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

543

REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

559

REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

576

REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

592

REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

608

REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

624

REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

655

REG_SET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

672

REG_SET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

689

REG_SET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

706

REG_SET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

912

REG_SET(DCN_VM_FB_LOCATION_BASE, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

914

REG_SET(DCN_VM_FB_LOCATION_TOP, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

916

REG_SET(DCN_VM_FB_OFFSET, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

918

REG_SET(DCN_VM_AGP_BOT, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

920

REG_SET(DCN_VM_AGP_TOP, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

922

REG_SET(DCN_VM_AGP_BASE, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

193

REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

207

REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

217

REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

227

REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

237

REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

251

REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

261

REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

271

REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

281

REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

295

REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

305

REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

315

REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

325

REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

339

REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

349

REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

359

REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

385

REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

401

REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

418

REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

434

REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

451

REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

467

REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

484

REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

500

REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

533

REG_SET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

550

REG_SET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

567

REG_SET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

584

REG_SET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

602

REG_SET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

619

REG_SET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

636

REG_SET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

653

REG_SET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

684

REG_SET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

700

REG_SET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

717

REG_SET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

734

REG_SET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

974

REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

130

REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

146

REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

164

REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

180

REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

197

REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

213

REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

230

REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

246

REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

322

REG_SET(DCHUBBUB_ARB_SAT_LEVEL, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

101

REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

110

REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_MALL_A, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

117

REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

124

REG_SET(DCHUBBUB_ARB_REFCYC_PER_META_TRIP_A, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

133

REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

145

REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

154

REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

163

REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_MALL_B, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

170

REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

177

REG_SET(DCHUBBUB_ARB_REFCYC_PER_META_TRIP_B, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

199

REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

205

REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_A, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

207

REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_A, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

209

REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_A, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

220

REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

226

REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_A, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

228

REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_A, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

230

REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_A, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

242

REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

248

REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK1_B, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

250

REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK2_B, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

252

REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK3_B, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

263

REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

269

REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK1_B, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

271

REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK2_B, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

273

REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK3_B, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

299

REG_SET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

313

REG_SET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

327

REG_SET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_A, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

341

REG_SET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_B, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

356

REG_SET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

370

REG_SET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

384

REG_SET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_A, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

398

REG_SET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_B, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

424

REG_SET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

437

REG_SET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

63

REG_SET(COMPBUF_RESERVED_SPACE, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

80

REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, 0,

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

92

REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1286

REG_SET(CURSOR_DST_OFFSET, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

396

REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

400

REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

405

REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

409

REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

425

REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

429

REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

433

REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

437

REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

442

REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

446

REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

450

REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

454

REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

476

REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

480

REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

486

REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

490

REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

495

REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

499

REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

503

REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

507

REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

619

REG_SET(BLANK_OFFSET_1, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

622

REG_SET(DST_DIMENSIONS, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

629

REG_SET(REF_FREQ_TO_PIX_FREQ, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

633

REG_SET(VBLANK_PARAMETERS_1, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

637

REG_SET(NOM_PARAMETERS_0, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

641

REG_SET(NOM_PARAMETERS_1, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

644

REG_SET(NOM_PARAMETERS_4, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

647

REG_SET(NOM_PARAMETERS_5, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

654

REG_SET(VBLANK_PARAMETERS_2, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

658

REG_SET(NOM_PARAMETERS_2, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

662

REG_SET(NOM_PARAMETERS_3, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

665

REG_SET(NOM_PARAMETERS_6, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

668

REG_SET(NOM_PARAMETERS_7, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

721

REG_SET(PREFETCH_SETTINS_C, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

728

REG_SET(VBLANK_PARAMETERS_3, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

731

REG_SET(VBLANK_PARAMETERS_4, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

738

REG_SET(DCN_SURF0_TTU_CNTL1, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

741

REG_SET(DCN_SURF1_TTU_CNTL1, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

744

REG_SET(DCN_CUR0_TTU_CNTL1, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

798

REG_SET(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

801

REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

803

REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

806

REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

808

REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

817

REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

819

REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

823

REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

825

REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

829

REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

831

REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

838

REG_SET(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

103

REG_SET(REF_FREQ_TO_PIX_FREQ, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

107

REG_SET(VBLANK_PARAMETERS_1, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1082

REG_SET(CURSOR_DST_OFFSET, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

111

REG_SET(NOM_PARAMETERS_0, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

115

REG_SET(NOM_PARAMETERS_1, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

118

REG_SET(NOM_PARAMETERS_4, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

121

REG_SET(NOM_PARAMETERS_5, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

128

REG_SET(VBLANK_PARAMETERS_2, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

132

REG_SET(NOM_PARAMETERS_2, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

136

REG_SET(NOM_PARAMETERS_3, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

139

REG_SET(NOM_PARAMETERS_6, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

142

REG_SET(NOM_PARAMETERS_7, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

168

REG_SET(FLIP_PARAMETERS_1, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

257

REG_SET(PREFETCH_SETTINGS_C, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

268

REG_SET(VBLANK_PARAMETERS_3, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

271

REG_SET(VBLANK_PARAMETERS_4, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

274

REG_SET(FLIP_PARAMETERS_2, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

281

REG_SET(DCN_SURF0_TTU_CNTL1, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

284

REG_SET(DCN_SURF1_TTU_CNTL1, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

287

REG_SET(DCN_CUR0_TTU_CNTL1, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

289

REG_SET(DCN_CUR1_TTU_CNTL1, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

67

REG_SET(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

686

REG_SET(DMDATA_CNTL, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

70

REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

73

REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

766

REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

770

REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

775

REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

779

REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

795

REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

799

REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

803

REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

807

REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

812

REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

816

REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

820

REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

824

REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

846

REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

850

REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

856

REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

860

REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

865

REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

869

REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

873

REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

877

REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

93

REG_SET(BLANK_OFFSET_1, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

96

REG_SET(DST_DIMENSIONS, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

101

REG_SET(VBLANK_PARAMETERS_6, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

109

REG_SET(FLIP_PARAMETERS_3, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

117

REG_SET(FLIP_PARAMETERS_4, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

120

REG_SET(FLIP_PARAMETERS_5, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

123

REG_SET(FLIP_PARAMETERS_6, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

240

REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

243

REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

616

REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

620

REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

624

REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

628

REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

632

REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

636

REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

641

REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

645

REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

650

REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

654

REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

658

REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

662

REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

93

REG_SET(VBLANK_PARAMETERS_5, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

116

REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

120

REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

125

REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

129

REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

145

REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

149

REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

153

REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

157

REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

162

REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

166

REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

170

REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

174

REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

196

REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

200

REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_C, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

204

REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

208

REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

214

REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

218

REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

222

REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

226

REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

231

REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

235

REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_C, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

239

REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

243

REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

247

REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

251

REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

255

REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

259

REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

276

REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

280

REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

284

REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

288

REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

293

REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

297

REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

301

REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

305

REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

57

REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

60

REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

263

REG_SET(BLANK_OFFSET_1, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

266

REG_SET(DST_DIMENSIONS, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

273

REG_SET(REF_FREQ_TO_PIX_FREQ, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

277

REG_SET(VBLANK_PARAMETERS_1, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

281

REG_SET(NOM_PARAMETERS_0, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

285

REG_SET(NOM_PARAMETERS_1, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

288

REG_SET(NOM_PARAMETERS_4, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

291

REG_SET(NOM_PARAMETERS_5, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

298

REG_SET(VBLANK_PARAMETERS_2, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

302

REG_SET(NOM_PARAMETERS_2, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

306

REG_SET(NOM_PARAMETERS_3, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

309

REG_SET(NOM_PARAMETERS_6, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

312

REG_SET(NOM_PARAMETERS_7, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

338

REG_SET(FLIP_PARAMETERS_1, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

340

REG_SET(HUBP_3DLUT_DLG_PARAM, 0, REFCYC_PER_3DLUT_GROUP, dlg_attr->refcyc_per_tdlut_group);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

370

REG_SET(PREFETCH_SETTINGS_C, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

381

REG_SET(VBLANK_PARAMETERS_3, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

384

REG_SET(VBLANK_PARAMETERS_4, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

387

REG_SET(FLIP_PARAMETERS_2, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

394

REG_SET(DCN_SURF0_TTU_CNTL1, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

397

REG_SET(DCN_SURF1_TTU_CNTL1, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

400

REG_SET(DCN_CUR0_TTU_CNTL1, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

448

REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

452

REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

465

REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

469

REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

473

REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

477

REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

493

REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

497

REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_C, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

501

REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

505

REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

509

REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

513

REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

517

REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

521

REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

534

REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

538

REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

542

REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

546

REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

798

REG_SET(CURSOR_DST_OFFSET, 0,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1018

REG_SET(DC_IP_REQUEST_CNTL, 0,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1027

REG_SET(DC_IP_REQUEST_CNTL, 0,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1044

REG_SET(DC_IP_REQUEST_CNTL, 0,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1048

REG_SET(DC_IP_REQUEST_CNTL, 0,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1073

REG_SET(DC_IP_REQUEST_CNTL, 0,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1077

REG_SET(DC_IP_REQUEST_CNTL, 0,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1496

REG_SET(DC_IP_REQUEST_CNTL, 0,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1508

REG_SET(DC_IP_REQUEST_CNTL, 0,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1279

REG_SET(DC_IP_REQUEST_CNTL, 0,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1289

REG_SET(DC_IP_REQUEST_CNTL, 0,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

320

REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

354

REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

476

REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

533

REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c

173

REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);

drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c

222

REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

299

REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

332

REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

355

REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

373

REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

458

REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

462

REG_SET(DOMAIN0_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

466

REG_SET(DOMAIN1_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

470

REG_SET(DOMAIN2_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

474

REG_SET(DOMAIN3_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

482

REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

245

REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

286

REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

306

REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

325

REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

133

REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

149

REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

164

REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

183

REG_SET(DOMAIN0_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

187

REG_SET(DOMAIN1_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

191

REG_SET(DOMAIN2_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

195

REG_SET(DOMAIN3_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

91

REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2962

REG_SET(DC_IP_REQUEST_CNTL, 0,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2976

REG_SET(DC_IP_REQUEST_CNTL, 0,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3522

REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, enable ? 1 : 0);

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

384

REG_SET(reg, val, f2, v2); }

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

388

val = REG_SET(reg, val, f2, v2); \

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

389

REG_SET(reg, val, f3, v3); }

drivers/gpu/drm/amd/display/dc/inc/reg_helper.h

45

#ifdef REG_SET

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c

83

REG_SET(MMHUBBUB_WARMUP_BASE_ADDR_HIGH, 0, MMHUBBUB_WARMUP_BASE_ADDR_HIGH, start_address_shift.high_part);

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c

84

REG_SET(MMHUBBUB_WARMUP_BASE_ADDR_LOW, 0, MMHUBBUB_WARMUP_BASE_ADDR_LOW, start_address_shift.low_part);

drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c

85

REG_SET(MMHUBBUB_WARMUP_ADDR_REGION, 0, MMHUBBUB_WARMUP_ADDR_REGION, params->region_size >> 5);

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

213

REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, insert_above_mpcc->mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

217

REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

220

REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, dpp_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

221

REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, tree->opp_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

224

REG_SET(MPCC_UPDATE_LOCK_SEL[mpcc_id], 0, MPCC_UPDATE_LOCK_SEL, tree->opp_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

238

REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0, MPCC_BOT_SEL, mpcc_id);

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

304

REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0,

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

308

REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0,

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

318

REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf);

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

319

REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

320

REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, 0xf);

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

321

REG_SET(MPCC_UPDATE_LOCK_SEL[mpcc_id], 0, MPCC_UPDATE_LOCK_SEL, 0xf);

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

329

REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf);

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

330

REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

331

REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, 0xf);

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

332

REG_SET(MPCC_UPDATE_LOCK_SEL[mpcc_id], 0, MPCC_UPDATE_LOCK_SEL, 0xf);

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

363

REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf);

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

364

REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

365

REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, 0xf);

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

366

REG_SET(MPCC_UPDATE_LOCK_SEL[mpcc_id], 0, MPCC_UPDATE_LOCK_SEL, 0xf);

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

384

REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf);

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

385

REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

386

REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, 0xf);

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

387

REG_SET(MPCC_UPDATE_LOCK_SEL[mpcc_id], 0, MPCC_UPDATE_LOCK_SEL, 0xf);

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

464

REG_SET(CUR[opp_id], 0, CUR_VUPDATE_LOCK_SET, lock ? 1 : 0);

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

68

REG_SET(MPCC_BG_R_CR[bottommost_mpcc->mpcc_id], 0,

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

70

REG_SET(MPCC_BG_G_Y[bottommost_mpcc->mpcc_id], 0,

drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c

72

REG_SET(MPCC_BG_B_CB[bottommost_mpcc->mpcc_id], 0,

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

142

REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode);

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

182

REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode);

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

198

REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode);

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

241

REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode);

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

278

REG_SET(MPCC_MEM_PWR_CTRL[mpcc_id], 0,

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

293

REG_SET(MPCC_OGAM_LUT_INDEX[mpcc_id], 0, MPCC_OGAM_LUT_INDEX, 0);

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

388

REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, MPCC_OGAM_LUT_DATA, rgb[i].red_reg);

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

389

REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, MPCC_OGAM_LUT_DATA, rgb[i].green_reg);

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

390

REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, MPCC_OGAM_LUT_DATA, rgb[i].blue_reg);

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

392

REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0,

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

394

REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0,

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

396

REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0,

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

413

REG_SET(MPCC_OGAM_MODE[mpcc_id], 0, MPCC_OGAM_MODE, 0);

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

426

REG_SET(MPCC_OGAM_MODE[mpcc_id], 0, MPCC_OGAM_MODE,

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

440

REG_SET(MPCC_OGAM_MODE[mpcc_id], 0, MPCC_OGAM_MODE, 0);

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

445

REG_SET(MPCC_OGAM_MODE[mpcc_id], 0, MPCC_OGAM_MODE, 0);

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

468

REG_SET(MPCC_OGAM_MODE[mpcc_id], 0, MPCC_OGAM_MODE,

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

66

REG_SET(MPCC_TOP_GAIN[mpcc_id], 0, MPCC_TOP_GAIN, blnd_cfg->top_gain);

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

67

REG_SET(MPCC_BOT_GAIN_INSIDE[mpcc_id], 0, MPCC_BOT_GAIN_INSIDE, blnd_cfg->bottom_inside_gain);

drivers/gpu/drm/amd/display/dc/mpc/dcn20/dcn20_mpc.c

68

REG_SET(MPCC_BOT_GAIN_OUTSIDE[mpcc_id], 0, MPCC_BOT_GAIN_OUTSIDE, blnd_cfg->bottom_outside_gain);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1043

REG_SET(RMU_3DLUT_DATA_30BIT[rmu_idx], 0, MPC_RMU_3DLUT_DATA_30BIT, value);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1076

REG_SET(MPCC_GAMUT_REMAP_MODE[mpcc_id], 0,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

109

REG_SET(DWB_MUX[dwb_id], 0,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1121

REG_SET(MPCC_GAMUT_REMAP_MODE[mpcc_id], 0,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1314

REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1355

REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

198

REG_SET(MPCC_OGAM_LUT_INDEX[mpcc_id], 0, MPCC_OGAM_LUT_INDEX, 0);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

312

REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, MPCC_OGAM_LUT_DATA, rgb[i].red_reg);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

319

REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, MPCC_OGAM_LUT_DATA, rgb[i].red_reg);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

321

REG_SET(MPCC_OGAM_LUT_INDEX[mpcc_id], 0, MPCC_OGAM_LUT_INDEX, 0);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

327

REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, MPCC_OGAM_LUT_DATA, rgb[i].green_reg);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

329

REG_SET(MPCC_OGAM_LUT_INDEX[mpcc_id], 0, MPCC_OGAM_LUT_INDEX, 0);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

335

REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, MPCC_OGAM_LUT_DATA, rgb[i].blue_reg);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

351

REG_SET(MPCC_OGAM_MODE[mpcc_id], 0, MPCC_OGAM_MODE, 0);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

356

REG_SET(MPCC_OGAM_CONTROL[mpcc_id], 0, MPCC_OGAM_MODE, 0);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

360

REG_SET(MPCC_OGAM_CONTROL[mpcc_id], 0, MPCC_OGAM_MODE, 2);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

484

REG_SET(SHAPER_LUT_INDEX[rmu_idx], 0, MPC_RMU_SHAPER_LUT_INDEX, 0);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

813

REG_SET(SHAPER_LUT_DATA[rmu_idx], 0, MPC_RMU_SHAPER_LUT_DATA, red_value);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

814

REG_SET(SHAPER_LUT_DATA[rmu_idx], 0, MPC_RMU_SHAPER_LUT_DATA, green_value);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

815

REG_SET(SHAPER_LUT_DATA[rmu_idx], 0, MPC_RMU_SHAPER_LUT_DATA, blue_value);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

831

REG_SET(MPC_RMU_MEM_PWR_CTRL, 0,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

843

REG_SET(MPC_RMU_MEM_PWR_CTRL, 0,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

874

REG_SET(SHAPER_CONTROL[rmu_idx], 0, MPC_RMU_SHAPER_LUT_MODE, 0);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

898

REG_SET(SHAPER_CONTROL[rmu_idx], 0, MPC_RMU_SHAPER_LUT_MODE, next_mode == LUT_RAM_A ? 1:2);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

99

REG_SET(DWB_MUX[dwb_id], 0,

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

993

REG_SET(RMU_3DLUT_INDEX[rmu_idx], 0, MPC_RMU_3DLUT_INDEX, 0);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

136

REG_SET(MPCC_MCM_1DLUT_LUT_INDEX[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_INDEX, 0);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

238

REG_SET(MPCC_MCM_1DLUT_LUT_DATA[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_DATA, rgb[i].red_reg);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

239

REG_SET(MPCC_MCM_1DLUT_LUT_DATA[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_DATA, last_base_value_red);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

241

REG_SET(MPCC_MCM_1DLUT_LUT_INDEX[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_INDEX, 0);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

244

REG_SET(MPCC_MCM_1DLUT_LUT_DATA[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_DATA, rgb[i].red_reg);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

245

REG_SET(MPCC_MCM_1DLUT_LUT_DATA[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_DATA, last_base_value_red);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

247

REG_SET(MPCC_MCM_1DLUT_LUT_INDEX[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_INDEX, 0);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

250

REG_SET(MPCC_MCM_1DLUT_LUT_DATA[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_DATA, rgb[i].green_reg);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

251

REG_SET(MPCC_MCM_1DLUT_LUT_DATA[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_DATA, last_base_value_green);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

253

REG_SET(MPCC_MCM_1DLUT_LUT_INDEX[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_INDEX, 0);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

256

REG_SET(MPCC_MCM_1DLUT_LUT_DATA[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_DATA, rgb[i].blue_reg);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

257

REG_SET(MPCC_MCM_1DLUT_LUT_DATA[mpcc_id], 0, MPCC_MCM_1DLUT_LUT_DATA, last_base_value_blue);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

271

REG_SET(MPCC_MCM_1DLUT_CONTROL[mpcc_id], 0, MPCC_MCM_1DLUT_MODE, 0);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

339

REG_SET(MPCC_MCM_SHAPER_LUT_INDEX[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_INDEX, 0);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

674

REG_SET(MPCC_MCM_SHAPER_LUT_DATA[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_DATA, red_value);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

675

REG_SET(MPCC_MCM_SHAPER_LUT_DATA[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_DATA, green_value);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

676

REG_SET(MPCC_MCM_SHAPER_LUT_DATA[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_DATA, blue_value);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

692

REG_SET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], 0,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

723

REG_SET(MPCC_MCM_SHAPER_CONTROL[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_MODE, 0);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

74

REG_SET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], 0, MPCC_MCM_1DLUT_MEM_PWR_DIS, power_on);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

746

REG_SET(MPCC_MCM_SHAPER_CONTROL[mpcc_id], 0, MPCC_MCM_SHAPER_LUT_MODE, next_mode == LUT_RAM_A ? 1:2);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

822

REG_SET(MPCC_MCM_3DLUT_INDEX[mpcc_id], 0, MPCC_MCM_3DLUT_INDEX, 0);

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

87

REG_SET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], 0,

drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c

874

REG_SET(MPCC_MCM_3DLUT_DATA_30BIT[mpcc_id], 0, MPCC_MCM_3DLUT_DATA_30BIT, value);

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

304

REG_SET(MPCC_GAMUT_REMAP_MODE[mpcc_id], 0,

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

333

REG_SET(MPCC_GAMUT_REMAP_MODE[mpcc_id], 0, MPCC_GAMUT_REMAP_MODE, mode_select);

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

338

REG_SET(MPCC_MCM_FIRST_GAMUT_REMAP_MODE[mpcc_id], 0,

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

367

REG_SET(MPCC_MCM_FIRST_GAMUT_REMAP_MODE[mpcc_id], 0,

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

373

REG_SET(MPCC_MCM_SECOND_GAMUT_REMAP_MODE[mpcc_id], 0,

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

402

REG_SET(MPCC_MCM_SECOND_GAMUT_REMAP_MODE[mpcc_id], 0,

drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c

47

REG_SET(MPCC_MCM_3DLUT_FAST_LOAD_SELECT[mpcc_id], 0, MPCC_MCM_3DLUT_FL_SEL, hubp_idx);

drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.c

100

REG_SET(FMT_DITHER_RAND_G_SEED, 0,

drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.c

103

REG_SET(FMT_DITHER_RAND_B_SEED, 0,

drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.c

97

REG_SET(FMT_DITHER_RAND_R_SEED, 0,

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

125

REG_SET(OTG_VERTICAL_INTERRUPT1_POSITION, 0,

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

135

REG_SET(OTG_VERTICAL_INTERRUPT2_POSITION, 0,

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

192

REG_SET(OTG_H_TOTAL, 0,

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

223

REG_SET(OTG_V_TOTAL, 0,

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

675

REG_SET(OTG_GLOBAL_CONTROL0, 0,

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

677

REG_SET(OTG_MASTER_UPDATE_LOCK, 0,

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

691

REG_SET(OTG_MASTER_UPDATE_LOCK, 0,

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

745

REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0,

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

748

REG_SET(OTG_VERT_SYNC_CONTROL, 0,

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

779

REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0,

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

818

REG_SET(OTG_VERT_SYNC_CONTROL, 0,

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

822

REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0,

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

84

REG_SET(OTG_VSTARTUP_PARAM, 0,

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

892

REG_SET(OTG_GLOBAL_CONTROL2, 0,

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

91

REG_SET(OTG_VREADY_PARAM, 0,

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

910

REG_SET(OTG_MANUAL_FLOW_CONTROL, 0,

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

913

REG_SET(OTG_MANUAL_FLOW_CONTROL, 0,

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

935

REG_SET(OTG_V_TOTAL_MID, 0,

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

963

REG_SET(OTG_V_TOTAL_MAX, 0,

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

966

REG_SET(OTG_V_TOTAL_MIN, 0,

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

99

REG_SET(OTG_STEREO_CONTROL, 0,

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

142

REG_SET(OPTC_BYTES_PER_PIXEL, 0,

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

176

REG_SET(OPTC_MEMORY_CONFIG, 0,

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

205

REG_SET(OPTC_MEMORY_CONFIG, 0,

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

216

REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_BY2, 1);

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

284

REG_SET(OTG_GLOBAL_CONTROL0, 0,

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

294

REG_SET(OTG_MASTER_UPDATE_LOCK, 0,

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

322

REG_SET(OTG_MASTER_UPDATE_LOCK, 0,

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

344

REG_SET(OTG_MASTER_UPDATE_LOCK, 0,

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

368

REG_SET(OTG_MASTER_UPDATE_LOCK, 0,

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

374

REG_SET(OTG_GLOBAL_CONTROL0, 0,

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

383

REG_SET(OTG_GLOBAL_CONTROL0, 0,

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

386

REG_SET(OTG_VUPDATE_KEEPOUT, 0,

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

389

REG_SET(OTG_MASTER_UPDATE_LOCK, 0,

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

401

REG_SET(OTG_MASTER_UPDATE_LOCK, 0,

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

404

REG_SET(OTG_VUPDATE_KEEPOUT, 0,

drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c

481

REG_SET(OTG_TRIGA_MANUAL_TRIG, 0,

drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c

45

REG_SET(OTG_GLOBAL_CONTROL0, 0,

drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c

47

REG_SET(OTG_VUPDATE_KEEPOUT, 0,

drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c

49

REG_SET(OTG_MASTER_UPDATE_LOCK, 0,

drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c

61

REG_SET(OTG_MASTER_UPDATE_LOCK, 0,

drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c

63

REG_SET(OTG_VUPDATE_KEEPOUT, 0,

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

125

REG_SET(OTG_MASTER_UPDATE_LOCK, 0,

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

174

REG_SET(OTG_DRR_V_TOTAL_CHANGE, 0,

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

213

REG_SET(OPTC_MEMORY_CONFIG, 0,

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

250

REG_SET(OPTC_MEMORY_CONFIG, 0,

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

270

REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_MODE, opp_cnt - 1);

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

52

REG_SET(OTG_VUPDATE_KEEPOUT, 0,

drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c

55

REG_SET(OTG_MASTER_UPDATE_LOCK, 0,

drivers/gpu/drm/amd/display/dc/optc/dcn301/dcn301_optc.c

64

REG_SET(OTG_V_TOTAL_MID, 0,

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

191

REG_SET(OTG_V_TOTAL_MID, 0,

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

240

REG_SET(OTG_H_TIMING_CNTL, 0,

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

243

REG_SET(OPTC_MEMORY_CONFIG, 0,

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

68

REG_SET(OPTC_MEMORY_CONFIG, 0,

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

88

REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_MODE, opp_cnt - 1);

drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c

181

REG_SET(OPTC_MEMORY_CONFIG, 0,

drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c

80

REG_SET(OPTC_MEMORY_CONFIG, 0,

drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

245

REG_SET(OPTC_MEMORY_CONFIG, 0,

drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

284

REG_SET(OTG_V_TOTAL_MID, 0,

drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c

75

REG_SET(OPTC_MEMORY_CONFIG, 0,

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

411

REG_SET(OTG_V_TOTAL_MID, 0,

drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c

88

REG_SET(OPTC_MEMORY_CONFIG, 0,

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

112

REG_SET(OPTC_MEMORY_CONFIG, 0,

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

285

REG_SET(OPTC_MEMORY_CONFIG, 0,

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

349

REG_SET(OTG_V_TOTAL_MID, 0,

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

425

REG_SET(OTG_VSTARTUP_PARAM, 0,

drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c

432

REG_SET(OTG_VREADY_PARAM, 0,

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

101

REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

201

REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

278

REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

325

REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c

428

REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);

drivers/gpu/drm/mxsfb/lcdif_kms.c

396

writel(CTRL_SW_RESET, lcdif->base + LCDC_V8_CTRL + REG_SET);

drivers/gpu/drm/mxsfb/mxsfb_kms.c

169

writel(CTRL_DOTCLK_MODE, mxsfb->base + LCDC_CTRL + REG_SET);

drivers/gpu/drm/mxsfb/mxsfb_kms.c

205

writel(CTRL_RUN, mxsfb->base + LCDC_CTRL + REG_SET);

drivers/gpu/drm/mxsfb/mxsfb_kms.c

268

writel(CTRL1_FIFO_CLEAR, mxsfb->base + LCDC_CTRL1 + REG_SET);

drivers/gpu/drm/mxsfb/mxsfb_kms.c

430

writel(CTRL1_CUR_FRAME_DONE_IRQ_EN, mxsfb->base + LCDC_CTRL1 + REG_SET);

drivers/gpu/drm/radeon/cikd.h

1689

#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))

drivers/gpu/drm/radeon/evergreend.h

1541

#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))

drivers/gpu/drm/radeon/nid.h

1155

#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))

drivers/gpu/drm/radeon/r100.c

1198

tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |

drivers/gpu/drm/radeon/r100.c

1199

REG_SET(RADEON_RB_BLKSZ, rb_blksz) |

drivers/gpu/drm/radeon/r100.c

1200

REG_SET(RADEON_MAX_FETCH, max_fetch));

drivers/gpu/drm/radeon/r100.c

1231

REG_SET(RADEON_INDIRECT2_START, indirect2_start) |

drivers/gpu/drm/radeon/r100.c

1232

REG_SET(RADEON_INDIRECT1_START, indirect1_start));

drivers/gpu/drm/radeon/r100d.h

60

REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \

drivers/gpu/drm/radeon/r100d.h

61

REG_SET(PACKET0_COUNT, (n)))

drivers/gpu/drm/radeon/r100d.h

62

#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))

drivers/gpu/drm/radeon/r100d.h

64

REG_SET(PACKET3_IT_OPCODE, (op)) | \

drivers/gpu/drm/radeon/r100d.h

65

REG_SET(PACKET3_COUNT, (n)))

drivers/gpu/drm/radeon/r300d.h

61

REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \

drivers/gpu/drm/radeon/r300d.h

62

REG_SET(PACKET0_COUNT, (n)))

drivers/gpu/drm/radeon/r300d.h

63

#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))

drivers/gpu/drm/radeon/r300d.h

65

REG_SET(PACKET3_IT_OPCODE, (op)) | \

drivers/gpu/drm/radeon/r300d.h

66

REG_SET(PACKET3_COUNT, (n)))

drivers/gpu/drm/radeon/r600d.h

34

#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))

drivers/gpu/drm/radeon/rs400.c

153

tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16);

drivers/gpu/drm/radeon/rs400.c

154

tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16);

drivers/gpu/drm/radeon/rv515d.h

201

REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \

drivers/gpu/drm/radeon/rv515d.h

202

REG_SET(PACKET0_COUNT, (n)))

drivers/gpu/drm/radeon/rv515d.h

203

#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))

drivers/gpu/drm/radeon/rv515d.h

205

REG_SET(PACKET3_IT_OPCODE, (op)) | \

drivers/gpu/drm/radeon/rv515d.h

206

REG_SET(PACKET3_COUNT, (n)))

drivers/gpu/drm/radeon/sid.h

1593

#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))

drivers/misc/rp1/rp1_pci.c

47

iowrite32(value, rp1->bar1 + RP1_PCIE_APBS_BASE + REG_SET + MSIX_CFG(hwirq));

drivers/phy/freescale/phy-fsl-imx8qm-lvds-phy.c

127

regmap_write(priv->regmap, PHY_CTRL + REG_SET, val);

drivers/phy/freescale/phy-fsl-imx8qm-lvds-phy.c

403

regmap_write(priv->regmap, PHY_CTRL + REG_SET, PD);

drivers/pinctrl/pinctrl-ingenic.c

3532

reg = REG_SET(reg);

drivers/pinctrl/pinctrl-ingenic.c

3543

reg = REG_SET(reg);

drivers/pinctrl/pinctrl-ingenic.c

3833

REG_SET(reg), BIT(idx));

drivers/pinctrl/pinctrl-ingenic.c

3853

(set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx));

drivers/pinctrl/pinctrl-ingenic.c

4204

REG_SET(X1830_GPIO_PEL), bias << idxh);

drivers/pinctrl/pinctrl-ingenic.c

4209

REG_SET(X1830_GPIO_PEH), bias << idxh);

drivers/thermal/imx91_thermal.c

133

writel_relaxed(val, tmu->base + IMX91_TMU_THR_CTRL01 + REG_SET);

drivers/thermal/imx91_thermal.c

137

writel_relaxed(IMX91_TMU_CTRL0_THR1_IE, tmu->base + IMX91_TMU_CTRL0 + REG_SET);

drivers/thermal/imx91_thermal.c

215

tmu->base + IMX91_TMU_CTRL0 + REG_SET);

drivers/thermal/imx91_thermal.c

291

tmu->base + IMX91_TMU_CTRL1 + REG_SET);

drivers/thermal/imx91_thermal.c

296

tmu->base + IMX91_TMU_CTRL1 + REG_SET);

drivers/thermal/imx91_thermal.c

85

writel_relaxed(val, tmu->base + IMX91_TMU_CTRL1 + REG_SET);

drivers/thermal/imx91_thermal.c

92

reg += enable ? REG_SET : REG_CLR;

drivers/thermal/imx_thermal.c

230

regmap_write(map, soc_data->panic_alarm_ctrl + REG_SET,

drivers/thermal/imx_thermal.c

250

regmap_write(map, soc_data->high_alarm_ctrl + REG_SET,

drivers/thermal/imx_thermal.c

622

regmap_write(map, data->socdata->low_alarm_ctrl + REG_SET,

drivers/thermal/imx_thermal.c

653

regmap_write(map, IMX6_MISC0 + REG_SET,

drivers/thermal/imx_thermal.c

655

regmap_write(map, data->socdata->sensor_ctrl + REG_SET,

drivers/thermal/imx_thermal.c

705

regmap_write(map, data->socdata->measure_freq_ctrl + REG_SET,

drivers/thermal/imx_thermal.c

714

regmap_write(map, data->socdata->sensor_ctrl + REG_SET,

drivers/thermal/imx_thermal.c

811

ret = regmap_write(map, socdata->sensor_ctrl + REG_SET,

drivers/thermal/imx_thermal.c

837

ret = regmap_write(map, socdata->sensor_ctrl + REG_SET,