REGV_WR32
REGV_WR32(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, ITF_FIREWALL_VIOLATION_MASK_37XX);
REGV_WR32(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, ITF_FIREWALL_VIOLATION_MASK_40XX);
REGV_WR32(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, 0x0);
REGV_WR32(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, 0x0ul);
REGV_WR32(VPU_37XX_HOST_SS_ICB_CLEAR_0, status);
REGV_WR32(VPU_40XX_HOST_SS_ICB_CLEAR_0, status);
REGV_WR32(VPU_37XX_CPU_SS_TIM_IPC_FIFO, vpu_addr);
REGV_WR32(VPU_40XX_CPU_SS_TIM_IPC_FIFO, vpu_addr);
REGV_WR32(VPU_37XX_HOST_SS_AON_VPU_IDLE_GEN, val);
REGV_WR32(VPU_40XX_HOST_SS_AON_IDLE_GEN, val);
REGV_WR32(VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY, val);
REGV_WR32(VPU_50XX_HOST_SS_AON_PWR_ISLAND_STATUS_DLY, val);
REGV_WR32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, val);
REGV_WR32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, val);
REGV_WR32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0, val);
REGV_WR32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0, val);
REGV_WR32(VPU_37XX_HOST_SS_AON_PWR_ISO_EN0, val);
REGV_WR32(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0, val);
REGV_WR32(VPU_37XX_HOST_SS_CPR_CLK_SET, val);
REGV_WR32(VPU_40XX_HOST_SS_CPR_CLK_EN, val);
REGV_WR32(VPU_37XX_HOST_SS_CPR_RST_SET, val);
REGV_WR32(VPU_40XX_HOST_SS_CPR_RST_EN, val);
REGV_WR32(VPU_37XX_HOST_SS_NOC_QREQN, val);
REGV_WR32(VPU_40XX_HOST_SS_NOC_QREQN, val);
REGV_WR32(VPU_40XX_TOP_NOC_QREQN, val);
REGV_WR32(VPU_37XX_TOP_NOC_QREQN, val);
REGV_WR32(VPU_37XX_HOST_SS_AON_DPU_ACTIVE, val);
REGV_WR32(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES, val);
REGV_WR32(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, val);
REGV_WR32(VPU_37XX_HOST_IF_TBU_MMUSSIDV, val);
REGV_WR32(VPU_37XX_HOST_SS_CPR_RST_CLR, val);
REGV_WR32(VPU_40XX_HOST_IF_TBU_MMUSSIDV, val);
REGV_WR32(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, val);
REGV_WR32(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, val);
REGV_WR32(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, val);
REGV_WR32(VPU_37XX_HOST_SS_LOADING_ADDRESS_LO, val);
REGV_WR32(VPU_37XX_HOST_SS_LOADING_ADDRESS_LO, val);
REGV_WR32(VPU_40XX_CPU_SS_CPR_NOC_QREQN, val);
REGV_WR32(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO, val);
REGV_WR32(VPU_37XX_CPU_SS_TIM_SAFE, TIM_SAFE_ENABLE);
REGV_WR32(VPU_37XX_CPU_SS_TIM_WATCHDOG, TIM_WATCHDOG_RESET_VALUE);
REGV_WR32(VPU_37XX_CPU_SS_TIM_SAFE, TIM_SAFE_ENABLE);
REGV_WR32(VPU_37XX_CPU_SS_TIM_WDOG_EN, 0);
REGV_WR32(VPU_37XX_CPU_SS_TIM_GEN_CONFIG, val);
REGV_WR32(VPU_40XX_CPU_SS_TIM_SAFE, TIM_SAFE_ENABLE);
REGV_WR32(VPU_40XX_CPU_SS_TIM_WATCHDOG, TIM_WATCHDOG_RESET_VALUE);
REGV_WR32(VPU_40XX_CPU_SS_TIM_SAFE, TIM_SAFE_ENABLE);
REGV_WR32(VPU_40XX_CPU_SS_TIM_WDOG_EN, 0);
REGV_WR32(VPU_40XX_CPU_SS_TIM_GEN_CONFIG, val);
REGV_WR32(IVPU_MMU_REG_GERRORN, gerror_val);
REGV_WR32(IVPU_MMU_REG_CR0, val);
REGV_WR32(IVPU_MMU_REG_IRQ_CTRL, val);
REGV_WR32(IVPU_MMU_REG_CMDQ_PROD, q->prod);
REGV_WR32(IVPU_MMU_REG_CR1, val);
REGV_WR32(IVPU_MMU_REG_STRTAB_BASE_CFG, mmu->strtab.base_cfg);
REGV_WR32(IVPU_MMU_REG_CMDQ_PROD, 0);
REGV_WR32(IVPU_MMU_REG_CMDQ_CONS, 0);
REGV_WR32(IVPU_MMU_REG_EVTQ_PROD_SEC, 0);
REGV_WR32(IVPU_MMU_REG_EVTQ_CONS_SEC, 0);
REGV_WR32(IVPU_MMU_REG_CR0, val);
REGV_WR32(IVPU_MMU_REG_EVTQ_CONS_SEC, vdev->mmu->evtq.cons);