arch/x86/mm/mmio-mod.c

166

case REG_READ:

arch/x86/mm/mmio-mod.c

207

case REG_READ:

arch/x86/mm/pf_in.c

139

CHECK_OP_TYPE(opcode, reg_rop, REG_READ);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c

122

return REG_READ(MP1_SMN_C2PMSG_83);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c

90

res_val = REG_READ(MP1_SMN_C2PMSG_91);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

556

dprefclk_did = REG_READ(CLK3_CLK2_DFS_CNTL);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

560

pll_req_reg = REG_READ(CLK3_CLK_PLL_REQ);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

200

clk_mgr->base.dprefclk_khz = REG_READ(CLK4_CLK2_CURRENT_CNT);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

288

internal->CLK1_CLK3_CURRENT_CNT = REG_READ(CLK1_CLK3_CURRENT_CNT);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

289

internal->CLK1_CLK3_BYPASS_CNTL = REG_READ(CLK1_CLK3_BYPASS_CNTL);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

291

internal->CLK1_CLK3_DS_CNTL = REG_READ(CLK1_CLK3_DS_CNTL); //dcf deep sleep divider

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

292

internal->CLK1_CLK3_ALLOW_DS = REG_READ(CLK1_CLK3_ALLOW_DS);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

294

internal->CLK1_CLK1_CURRENT_CNT = REG_READ(CLK1_CLK1_CURRENT_CNT);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

295

internal->CLK1_CLK1_BYPASS_CNTL = REG_READ(CLK1_CLK1_BYPASS_CNTL);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

297

internal->CLK1_CLK2_CURRENT_CNT = REG_READ(CLK1_CLK2_CURRENT_CNT);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

298

internal->CLK1_CLK2_BYPASS_CNTL = REG_READ(CLK1_CLK2_BYPASS_CNTL);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

300

internal->CLK1_CLK0_CURRENT_CNT = REG_READ(CLK1_CLK0_CURRENT_CNT);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

301

internal->CLK1_CLK0_BYPASS_CNTL = REG_READ(CLK1_CLK0_BYPASS_CNTL);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

131

return REG_READ(MP1_SMN_C2PMSG_83);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

85

res_val = REG_READ(MP1_SMN_C2PMSG_91);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

178

uint32_t pll_req_reg = REG_READ(CLK0_CLK_PLL_REQ);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

103

*param_out = REG_READ(DAL_ARG_REG);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c

60

reg = REG_READ(DAL_RESP_REG);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr_smu_msg.c

100

*param_out = REG_READ(DAL_ARG_REG);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr_smu_msg.c

59

reg = REG_READ(DAL_RESP_REG);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

130

return REG_READ(MP1_SMN_C2PMSG_83);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

85

res_val = REG_READ(MP1_SMN_C2PMSG_91);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

220

internal->CLK1_CLK3_CURRENT_CNT = REG_READ(CLK1_0_CLK1_CLK3_CURRENT_CNT);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

221

internal->CLK1_CLK3_BYPASS_CNTL = REG_READ(CLK1_0_CLK1_CLK3_BYPASS_CNTL);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

223

internal->CLK1_CLK3_DS_CNTL = REG_READ(CLK1_0_CLK1_CLK3_DS_CNTL); //dcf deep sleep divider

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

224

internal->CLK1_CLK3_ALLOW_DS = REG_READ(CLK1_0_CLK1_CLK3_ALLOW_DS);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

226

internal->CLK1_CLK1_CURRENT_CNT = REG_READ(CLK1_0_CLK1_CLK1_CURRENT_CNT);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

227

internal->CLK1_CLK1_BYPASS_CNTL = REG_READ(CLK1_0_CLK1_CLK1_BYPASS_CNTL);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

229

internal->CLK1_CLK2_CURRENT_CNT = REG_READ(CLK1_0_CLK1_CLK2_CURRENT_CNT);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

230

internal->CLK1_CLK2_BYPASS_CNTL = REG_READ(CLK1_0_CLK1_CLK2_BYPASS_CNTL);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

232

internal->CLK1_CLK0_CURRENT_CNT = REG_READ(CLK1_0_CLK1_CLK0_CURRENT_CNT);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

233

internal->CLK1_CLK0_BYPASS_CNTL = REG_READ(CLK1_0_CLK1_CLK0_BYPASS_CNTL);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

144

return REG_READ(MP1_SMN_C2PMSG_83);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

90

res_val = REG_READ(MP1_SMN_C2PMSG_91);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

106

res_val = REG_READ(MP1_SMN_C2PMSG_91);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

163

return REG_READ(MP1_SMN_C2PMSG_83);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

119

res_val = REG_READ(MP1_SMN_C2PMSG_38);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c

174

return REG_READ(MP1_SMN_C2PMSG_37);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

105

res_val = REG_READ(MP1_SMN_C2PMSG_91);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c

149

return REG_READ(MP1_SMN_C2PMSG_83);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

530

dispclk_khz_reg = REG_READ(CLK1_CLK0_CURRENT_CNT); // DISPCLK

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

531

dppclk_khz_reg = REG_READ(CLK1_CLK1_CURRENT_CNT); // DPPCLK

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

532

dprefclk_khz_reg = REG_READ(CLK1_CLK2_CURRENT_CNT); // DPREFCLK

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

533

dcfclk_khz_reg = REG_READ(CLK1_CLK3_CURRENT_CNT); // DCFCLK

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

534

dtbclk_khz_reg = REG_READ(CLK1_CLK4_CURRENT_CNT); // DTBCLK

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

535

fclk_khz_reg = REG_READ(CLK4_CLK0_CURRENT_CNT); // FCLK

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

855

pll_req_reg = REG_READ(CLK0_CLK_PLL_REQ);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

857

pll_req_reg = REG_READ(CLK1_CLK_PLL_REQ);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

885

dispclk_did = REG_READ(CLK0_CLK0_DFS_CNTL);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

887

dppclk_did = REG_READ(CLK0_CLK1_DFS_CNTL);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

889

dprefclk_did = REG_READ(CLK0_CLK2_DFS_CNTL);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

891

dcfclk_did = REG_READ(CLK0_CLK3_DFS_CNTL);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

893

dtbclk_did = REG_READ(CLK0_CLK4_DFS_CNTL);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

896

dispclk_did = REG_READ(CLK1_CLK0_DFS_CNTL);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

898

dppclk_did = REG_READ(CLK1_CLK1_DFS_CNTL);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

900

dprefclk_did = REG_READ(CLK1_CLK2_DFS_CNTL);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

902

dcfclk_did = REG_READ(CLK1_CLK3_DFS_CNTL);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

904

dtbclk_did = REG_READ(CLK1_CLK4_DFS_CNTL);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

113

reg = REG_READ(DAL_RESP_REG);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

151

*param_out = REG_READ(DAL_ARG_REG);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

56

reg = REG_READ(DAL_RESP_REG);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c

91

*param_out = REG_READ(DAL_ARG_REG);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

436

actual_dtbclk = REG_READ(CLK1_CLK4_CURRENT_CNT);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

595

internal->CLK1_CLK4_CURRENT_CNT = REG_READ(CLK1_CLK4_CURRENT_CNT);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

596

internal->CLK1_CLK4_BYPASS_CNTL = REG_READ(CLK1_CLK4_BYPASS_CNTL);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

599

internal->CLK1_CLK3_CURRENT_CNT = REG_READ(CLK1_CLK3_CURRENT_CNT);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

600

internal->CLK1_CLK3_BYPASS_CNTL = REG_READ(CLK1_CLK3_BYPASS_CNTL);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

603

internal->CLK1_CLK3_DS_CNTL = REG_READ(CLK1_CLK3_DS_CNTL);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

604

internal->CLK1_CLK3_ALLOW_DS = REG_READ(CLK1_CLK3_ALLOW_DS);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

607

internal->CLK1_CLK1_CURRENT_CNT = REG_READ(CLK1_CLK1_CURRENT_CNT);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

608

internal->CLK1_CLK1_BYPASS_CNTL = REG_READ(CLK1_CLK1_BYPASS_CNTL);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

611

internal->CLK1_CLK2_CURRENT_CNT = REG_READ(CLK1_CLK2_CURRENT_CNT);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

612

internal->CLK1_CLK2_BYPASS_CNTL = REG_READ(CLK1_CLK2_BYPASS_CNTL);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

615

internal->CLK1_CLK0_CURRENT_CNT = REG_READ(CLK1_CLK0_CURRENT_CNT);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

616

internal->CLK1_CLK0_BYPASS_CNTL = REG_READ(CLK1_CLK0_BYPASS_CNTL);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

711

ssc_enable = REG_READ(CLK6_spll_field_8) & CLK6_spll_field_8__spll_ssc_en_MASK;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

713

ssc_enable = REG_READ(CLK5_spll_field_8) & CLK5_spll_field_8__spll_ssc_en_MASK;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

851

clock_source = REG_READ(CLK1_CLK2_BYPASS_CNTL) & CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL_MASK;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

120

res_val = REG_READ(MP1_SMN_C2PMSG_91);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

181

return REG_READ(MP1_SMN_C2PMSG_83);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1256

pll_req_reg = REG_READ(CLK0_CLK_PLL_REQ);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

346

dispclk_did = REG_READ(CLK0_CLK0_DFS_CNTL);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

348

dppclk_did = REG_READ(CLK0_CLK1_DFS_CNTL);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

350

dprefclk_did = REG_READ(CLK0_CLK2_DFS_CNTL);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

352

dcfclk_did = REG_READ(CLK0_CLK3_DFS_CNTL);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

354

dtbclk_did = REG_READ(CLK0_CLK4_DFS_CNTL);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

356

fclk_did = REG_READ(CLK2_CLK2_DFS_CNTL);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

134

*param_out = REG_READ(DAL_ARG_REG);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

42

reg = REG_READ(DAL_RESP_REG);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

74

*param_out = REG_READ(DAL_ARG_REG);

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c

98

reg = REG_READ(DAL_RESP_REG);

drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c

161

return REG_READ(MICROSECOND_TIME_BASE_DIV) == 0x00120464;

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

717

dccg_reg_state->dc_mem_global_pwr_req_cntl = REG_READ(DC_MEM_GLOBAL_PWR_REQ_CNTL);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

718

dccg_reg_state->dccg_audio_dtbclk_dto_modulo = REG_READ(DCCG_AUDIO_DTBCLK_DTO_MODULO);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

719

dccg_reg_state->dccg_audio_dtbclk_dto_phase = REG_READ(DCCG_AUDIO_DTBCLK_DTO_PHASE);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

720

dccg_reg_state->dccg_audio_dto_source = REG_READ(DCCG_AUDIO_DTO_SOURCE);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

721

dccg_reg_state->dccg_audio_dto0_module = REG_READ(DCCG_AUDIO_DTO0_MODULE);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

722

dccg_reg_state->dccg_audio_dto0_phase = REG_READ(DCCG_AUDIO_DTO0_PHASE);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

723

dccg_reg_state->dccg_audio_dto1_module = REG_READ(DCCG_AUDIO_DTO1_MODULE);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

724

dccg_reg_state->dccg_audio_dto1_phase = REG_READ(DCCG_AUDIO_DTO1_PHASE);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

725

dccg_reg_state->dccg_cac_status = REG_READ(DCCG_CAC_STATUS);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

726

dccg_reg_state->dccg_cac_status2 = REG_READ(DCCG_CAC_STATUS2);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

727

dccg_reg_state->dccg_disp_cntl_reg = REG_READ(DCCG_DISP_CNTL_REG);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

728

dccg_reg_state->dccg_ds_cntl = REG_READ(DCCG_DS_CNTL);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

729

dccg_reg_state->dccg_ds_dto_incr = REG_READ(DCCG_DS_DTO_INCR);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

730

dccg_reg_state->dccg_ds_dto_modulo = REG_READ(DCCG_DS_DTO_MODULO);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

731

dccg_reg_state->dccg_ds_hw_cal_interval = REG_READ(DCCG_DS_HW_CAL_INTERVAL);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

732

dccg_reg_state->dccg_gate_disable_cntl = REG_READ(DCCG_GATE_DISABLE_CNTL);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

733

dccg_reg_state->dccg_gate_disable_cntl2 = REG_READ(DCCG_GATE_DISABLE_CNTL2);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

734

dccg_reg_state->dccg_gate_disable_cntl3 = REG_READ(DCCG_GATE_DISABLE_CNTL3);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

735

dccg_reg_state->dccg_gate_disable_cntl4 = REG_READ(DCCG_GATE_DISABLE_CNTL4);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

736

dccg_reg_state->dccg_gate_disable_cntl5 = REG_READ(DCCG_GATE_DISABLE_CNTL5);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

737

dccg_reg_state->dccg_gate_disable_cntl6 = REG_READ(DCCG_GATE_DISABLE_CNTL6);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

738

dccg_reg_state->dccg_global_fgcg_rep_cntl = REG_READ(DCCG_GLOBAL_FGCG_REP_CNTL);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

739

dccg_reg_state->dccg_gtc_cntl = REG_READ(DCCG_GTC_CNTL);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

740

dccg_reg_state->dccg_gtc_current = REG_READ(DCCG_GTC_CURRENT);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

741

dccg_reg_state->dccg_gtc_dto_incr = REG_READ(DCCG_GTC_DTO_INCR);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

742

dccg_reg_state->dccg_gtc_dto_modulo = REG_READ(DCCG_GTC_DTO_MODULO);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

743

dccg_reg_state->dccg_perfmon_cntl = REG_READ(DCCG_PERFMON_CNTL);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

744

dccg_reg_state->dccg_perfmon_cntl2 = REG_READ(DCCG_PERFMON_CNTL2);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

745

dccg_reg_state->dccg_soft_reset = REG_READ(DCCG_SOFT_RESET);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

746

dccg_reg_state->dccg_test_clk_sel = REG_READ(DCCG_TEST_CLK_SEL);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

747

dccg_reg_state->dccg_vsync_cnt_ctrl = REG_READ(DCCG_VSYNC_CNT_CTRL);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

748

dccg_reg_state->dccg_vsync_cnt_int_ctrl = REG_READ(DCCG_VSYNC_CNT_INT_CTRL);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

749

dccg_reg_state->dccg_vsync_otg0_latch_value = REG_READ(DCCG_VSYNC_OTG0_LATCH_VALUE);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

750

dccg_reg_state->dccg_vsync_otg1_latch_value = REG_READ(DCCG_VSYNC_OTG1_LATCH_VALUE);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

751

dccg_reg_state->dccg_vsync_otg2_latch_value = REG_READ(DCCG_VSYNC_OTG2_LATCH_VALUE);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

752

dccg_reg_state->dccg_vsync_otg3_latch_value = REG_READ(DCCG_VSYNC_OTG3_LATCH_VALUE);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

753

dccg_reg_state->dccg_vsync_otg4_latch_value = REG_READ(DCCG_VSYNC_OTG4_LATCH_VALUE);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

754

dccg_reg_state->dccg_vsync_otg5_latch_value = REG_READ(DCCG_VSYNC_OTG5_LATCH_VALUE);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

755

dccg_reg_state->dispclk_cgtt_blk_ctrl_reg = REG_READ(DISPCLK_CGTT_BLK_CTRL_REG);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

756

dccg_reg_state->dispclk_freq_change_cntl = REG_READ(DISPCLK_FREQ_CHANGE_CNTL);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

757

dccg_reg_state->dp_dto_dbuf_en = REG_READ(DP_DTO_DBUF_EN);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

758

dccg_reg_state->dp_dto0_modulo = REG_READ(DP_DTO_MODULO[0]);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

759

dccg_reg_state->dp_dto0_phase = REG_READ(DP_DTO_PHASE[0]);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

760

dccg_reg_state->dp_dto1_modulo = REG_READ(DP_DTO_MODULO[1]);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

761

dccg_reg_state->dp_dto1_phase = REG_READ(DP_DTO_PHASE[1]);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

762

dccg_reg_state->dp_dto2_modulo = REG_READ(DP_DTO_MODULO[2]);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

763

dccg_reg_state->dp_dto2_phase = REG_READ(DP_DTO_PHASE[2]);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

764

dccg_reg_state->dp_dto3_modulo = REG_READ(DP_DTO_MODULO[3]);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

765

dccg_reg_state->dp_dto3_phase = REG_READ(DP_DTO_PHASE[3]);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

766

dccg_reg_state->dpiaclk_540m_dto_modulo = REG_READ(DPIACLK_540M_DTO_MODULO);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

767

dccg_reg_state->dpiaclk_540m_dto_phase = REG_READ(DPIACLK_540M_DTO_PHASE);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

768

dccg_reg_state->dpiaclk_810m_dto_modulo = REG_READ(DPIACLK_810M_DTO_MODULO);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

769

dccg_reg_state->dpiaclk_810m_dto_phase = REG_READ(DPIACLK_810M_DTO_PHASE);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

770

dccg_reg_state->dpiaclk_dto_cntl = REG_READ(DPIACLK_DTO_CNTL);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

771

dccg_reg_state->dpiasymclk_cntl = REG_READ(DPIASYMCLK_CNTL);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

772

dccg_reg_state->dppclk_cgtt_blk_ctrl_reg = REG_READ(DPPCLK_CGTT_BLK_CTRL_REG);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

773

dccg_reg_state->dppclk_ctrl = REG_READ(DPPCLK_CTRL);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

774

dccg_reg_state->dppclk_dto_ctrl = REG_READ(DPPCLK_DTO_CTRL);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

775

dccg_reg_state->dppclk0_dto_param = REG_READ(DPPCLK_DTO_PARAM[0]);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

776

dccg_reg_state->dppclk1_dto_param = REG_READ(DPPCLK_DTO_PARAM[1]);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

777

dccg_reg_state->dppclk2_dto_param = REG_READ(DPPCLK_DTO_PARAM[2]);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

778

dccg_reg_state->dppclk3_dto_param = REG_READ(DPPCLK_DTO_PARAM[3]);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

779

dccg_reg_state->dprefclk_cgtt_blk_ctrl_reg = REG_READ(DPREFCLK_CGTT_BLK_CTRL_REG);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

780

dccg_reg_state->dprefclk_cntl = REG_READ(DPREFCLK_CNTL);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

781

dccg_reg_state->dpstreamclk_cntl = REG_READ(DPSTREAMCLK_CNTL);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

782

dccg_reg_state->dscclk_dto_ctrl = REG_READ(DSCCLK_DTO_CTRL);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

783

dccg_reg_state->dscclk0_dto_param = REG_READ(DSCCLK0_DTO_PARAM);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

784

dccg_reg_state->dscclk1_dto_param = REG_READ(DSCCLK1_DTO_PARAM);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

785

dccg_reg_state->dscclk2_dto_param = REG_READ(DSCCLK2_DTO_PARAM);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

786

dccg_reg_state->dscclk3_dto_param = REG_READ(DSCCLK3_DTO_PARAM);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

787

dccg_reg_state->dtbclk_dto_dbuf_en = REG_READ(DTBCLK_DTO_DBUF_EN);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

788

dccg_reg_state->dtbclk_dto0_modulo = REG_READ(DTBCLK_DTO_MODULO[0]);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

789

dccg_reg_state->dtbclk_dto0_phase = REG_READ(DTBCLK_DTO_PHASE[0]);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

790

dccg_reg_state->dtbclk_dto1_modulo = REG_READ(DTBCLK_DTO_MODULO[1]);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

791

dccg_reg_state->dtbclk_dto1_phase = REG_READ(DTBCLK_DTO_PHASE[1]);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

792

dccg_reg_state->dtbclk_dto2_modulo = REG_READ(DTBCLK_DTO_MODULO[2]);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

793

dccg_reg_state->dtbclk_dto2_phase = REG_READ(DTBCLK_DTO_PHASE[2]);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

794

dccg_reg_state->dtbclk_dto3_modulo = REG_READ(DTBCLK_DTO_MODULO[3]);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

795

dccg_reg_state->dtbclk_dto3_phase = REG_READ(DTBCLK_DTO_PHASE[3]);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

796

dccg_reg_state->dtbclk_p_cntl = REG_READ(DTBCLK_P_CNTL);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

797

dccg_reg_state->force_symclk_disable = REG_READ(FORCE_SYMCLK_DISABLE);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

798

dccg_reg_state->hdmicharclk0_clock_cntl = REG_READ(HDMICHARCLK0_CLOCK_CNTL);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

799

dccg_reg_state->hdmistreamclk_cntl = REG_READ(HDMISTREAMCLK_CNTL);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

800

dccg_reg_state->hdmistreamclk0_dto_param = REG_READ(HDMISTREAMCLK0_DTO_PARAM);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

801

dccg_reg_state->microsecond_time_base_div = REG_READ(MICROSECOND_TIME_BASE_DIV);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

802

dccg_reg_state->millisecond_time_base_div = REG_READ(MILLISECOND_TIME_BASE_DIV);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

803

dccg_reg_state->otg_pixel_rate_div = REG_READ(OTG_PIXEL_RATE_DIV);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

804

dccg_reg_state->otg0_phypll_pixel_rate_cntl = REG_READ(OTG0_PHYPLL_PIXEL_RATE_CNTL);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

805

dccg_reg_state->otg0_pixel_rate_cntl = REG_READ(OTG0_PIXEL_RATE_CNTL);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

806

dccg_reg_state->otg1_phypll_pixel_rate_cntl = REG_READ(OTG1_PHYPLL_PIXEL_RATE_CNTL);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

807

dccg_reg_state->otg1_pixel_rate_cntl = REG_READ(OTG1_PIXEL_RATE_CNTL);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

808

dccg_reg_state->otg2_phypll_pixel_rate_cntl = REG_READ(OTG2_PHYPLL_PIXEL_RATE_CNTL);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

809

dccg_reg_state->otg2_pixel_rate_cntl = REG_READ(OTG2_PIXEL_RATE_CNTL);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

810

dccg_reg_state->otg3_phypll_pixel_rate_cntl = REG_READ(OTG3_PHYPLL_PIXEL_RATE_CNTL);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

811

dccg_reg_state->otg3_pixel_rate_cntl = REG_READ(OTG3_PIXEL_RATE_CNTL);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

812

dccg_reg_state->phyasymclk_clock_cntl = REG_READ(PHYASYMCLK_CLOCK_CNTL);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

813

dccg_reg_state->phybsymclk_clock_cntl = REG_READ(PHYBSYMCLK_CLOCK_CNTL);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

814

dccg_reg_state->phycsymclk_clock_cntl = REG_READ(PHYCSYMCLK_CLOCK_CNTL);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

815

dccg_reg_state->phydsymclk_clock_cntl = REG_READ(PHYDSYMCLK_CLOCK_CNTL);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

816

dccg_reg_state->phyesymclk_clock_cntl = REG_READ(PHYESYMCLK_CLOCK_CNTL);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

817

dccg_reg_state->phyplla_pixclk_resync_cntl = REG_READ(PHYPLLA_PIXCLK_RESYNC_CNTL);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

818

dccg_reg_state->phypllb_pixclk_resync_cntl = REG_READ(PHYPLLB_PIXCLK_RESYNC_CNTL);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

819

dccg_reg_state->phypllc_pixclk_resync_cntl = REG_READ(PHYPLLC_PIXCLK_RESYNC_CNTL);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

820

dccg_reg_state->phyplld_pixclk_resync_cntl = REG_READ(PHYPLLD_PIXCLK_RESYNC_CNTL);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

821

dccg_reg_state->phyplle_pixclk_resync_cntl = REG_READ(PHYPLLE_PIXCLK_RESYNC_CNTL);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

822

dccg_reg_state->refclk_cgtt_blk_ctrl_reg = REG_READ(REFCLK_CGTT_BLK_CTRL_REG);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

823

dccg_reg_state->socclk_cgtt_blk_ctrl_reg = REG_READ(SOCCLK_CGTT_BLK_CTRL_REG);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

824

dccg_reg_state->symclk_cgtt_blk_ctrl_reg = REG_READ(SYMCLK_CGTT_BLK_CTRL_REG);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

825

dccg_reg_state->symclk_psp_cntl = REG_READ(SYMCLK_PSP_CNTL);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

826

dccg_reg_state->symclk32_le_cntl = REG_READ(SYMCLK32_LE_CNTL);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

827

dccg_reg_state->symclk32_se_cntl = REG_READ(SYMCLK32_SE_CNTL);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

828

dccg_reg_state->symclka_clock_enable = REG_READ(SYMCLKA_CLOCK_ENABLE);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

829

dccg_reg_state->symclkb_clock_enable = REG_READ(SYMCLKB_CLOCK_ENABLE);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

830

dccg_reg_state->symclkc_clock_enable = REG_READ(SYMCLKC_CLOCK_ENABLE);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

831

dccg_reg_state->symclkd_clock_enable = REG_READ(SYMCLKD_CLOCK_ENABLE);

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c

832

dccg_reg_state->symclke_clock_enable = REG_READ(SYMCLKE_CLOCK_ENABLE);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1124

uint32_t dentist_dispclk_value = REG_READ(DENTIST_DISPCLK_CNTL);

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c

114

uint32_t dentist_dispclk_value = REG_READ(DENTIST_DISPCLK_CNTL);

drivers/gpu/drm/amd/display/dc/dce/dce_abm.c

124

s2 = REG_READ(BIOS_SCRATCH_2);

drivers/gpu/drm/amd/display/dc/dce/dce_abm.c

180

unsigned int backlight = REG_READ(BL1_PWM_CURRENT_ABM_LEVEL);

drivers/gpu/drm/amd/display/dc/dce/dce_abm.c

191

unsigned int backlight = REG_READ(BL1_PWM_TARGET_ABM_LEVEL);

drivers/gpu/drm/amd/display/dc/dce/dce_audio.c

81

value = REG_READ(AZALIA_F0_CODEC_ENDPOINT_DATA);

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

112

uint32_t value = REG_READ(AUX_ARB_CONTROL);

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

120

value = REG_READ(AUX_CONTROL);

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

165

value = REG_READ(AUX_ARB_CONTROL);

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

353

value = REG_READ(AUX_SW_STATUS);

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

99

uint32_t value = REG_READ(AUX_ARB_CONTROL);

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1203

clock_hz = REG_READ(PHASE[inst]);

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

1210

modulo_hz = REG_READ(MODULO[inst]);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

121

*state = (enum dc_psr_state)REG_READ(DMCU_IRAM_RD_DATA);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

345

dmcu->dmcu_version.interface_version = REG_READ(DMCU_IRAM_RD_DATA);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

346

dmcu->dmcu_version.abm_version = REG_READ(DMCU_IRAM_RD_DATA);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

347

dmcu->dmcu_version.psr_version = REG_READ(DMCU_IRAM_RD_DATA);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

348

dmcu->dmcu_version.build_version = ((REG_READ(DMCU_IRAM_RD_DATA) << 8) |

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

349

REG_READ(DMCU_IRAM_RD_DATA));

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

396

dmcu->dmcu_state = REG_READ(DC_DMCU_SCRATCH);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

434

dmcu->dmcu_state = REG_READ(DC_DMCU_SCRATCH);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

465

uint32_t dmcub_psp_version = REG_READ(DMCUB_SCRATCH15);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

538

*state = (enum dc_psr_state)REG_READ(DMCU_IRAM_RD_DATA);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

867

*cmd = REG_READ(SLAVE_COMM_CMD_REG);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

868

*data1 = REG_READ(SLAVE_COMM_DATA_REG1);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

869

*data2 = REG_READ(SLAVE_COMM_DATA_REG2);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

870

*data3 = REG_READ(SLAVE_COMM_DATA_REG3);

drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c

1717

REG_READ(DP_MSE_SAT_UPDATE);

drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c

328

value = REG_READ(DP_DPHY_INTERNAL_CTRL);

drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c

113

REG_READ(BL_PWM_CNTL);

drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c

115

REG_READ(BL_PWM_CNTL2);

drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c

117

REG_READ(BL_PWM_PERIOD_CNTL);

drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c

131

value = REG_READ(BIOS_SCRATCH_2);

drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c

178

REG_READ(BL_PWM_CNTL);

drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c

180

REG_READ(BL_PWM_CNTL2);

drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c

182

REG_READ(BL_PWM_PERIOD_CNTL);

drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c

57

REG_READ(BL_PWM_PERIOD_CNTL);

drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c

61

REG_READ(BL_PWM_CNTL);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

1430

value = REG_READ(DP_SEC_CNTL);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

333

misc1 = REG_READ(DP_MSA_MISC);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

868

value = REG_READ(DP_SEC_CNTL);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

894

value = REG_READ(DP_SEC_CNTL);

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

98

REG_READ(AFMT_VBI_PACKET_CONTROL);

drivers/gpu/drm/amd/display/dc/dce/dce_transform.c

228

power_ctl = REG_READ(DCFE_MEM_PWR_CTRL);

drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c

122

unsigned int backlight = REG_READ(BL1_PWM_CURRENT_ABM_LEVEL);

drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c

133

unsigned int backlight = REG_READ(BL1_PWM_TARGET_ABM_LEVEL);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

305

uint32_t wbscl_mode = REG_READ(WBSCL_MODE);

drivers/gpu/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c

128

REG_READ(BL_PWM_CNTL);

drivers/gpu/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c

130

REG_READ(BL_PWM_CNTL2);

drivers/gpu/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c

132

REG_READ(BL_PWM_PERIOD_CNTL);

drivers/gpu/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c

185

REG_READ(BL_PWM_CNTL);

drivers/gpu/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c

187

REG_READ(BL_PWM_CNTL2);

drivers/gpu/drm/amd/display/dc/dcn301/dcn301_panel_cntl.c

189

REG_READ(BL_PWM_PERIOD_CNTL);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

1338

REG_READ(DP_MSE_SAT_UPDATE);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

239

value = REG_READ(DP_DPHY_INTERNAL_CTRL);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

1421

value = REG_READ(DP_SEC_CNTL);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

306

misc1 = REG_READ(DP_MSA_MISC);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

776

value = REG_READ(DP_SEC_CNTL);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

870

value = REG_READ(DP_SEC_CNTL);

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

897

value = REG_READ(DP_SEC_CNTL);

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

506

value = REG_READ(DP_SEC_CNTL);

drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

502

misc1 = REG_READ(DP_MSA_MISC);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

113

s->gamut_remap_c11_c12 = REG_READ(CM_GAMUT_REMAP_C11_C12);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

114

s->gamut_remap_c13_c14 = REG_READ(CM_GAMUT_REMAP_C13_C14);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

115

s->gamut_remap_c21_c22 = REG_READ(CM_GAMUT_REMAP_C21_C22);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

116

s->gamut_remap_c23_c24 = REG_READ(CM_GAMUT_REMAP_C23_C24);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

117

s->gamut_remap_c31_c32 = REG_READ(CM_GAMUT_REMAP_C31_C32);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

118

s->gamut_remap_c33_c34 = REG_READ(CM_GAMUT_REMAP_C33_C34);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

334

uint32_t scl_mode = REG_READ(SCL_MODE);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

100

dpp_reg_state->mpc_size = REG_READ(MPC_SIZE);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

91

dpp_reg_state->recout_start = REG_READ(RECOUT_START);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

92

dpp_reg_state->recout_size = REG_READ(RECOUT_SIZE);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

93

dpp_reg_state->scl_horz_filter_scale_ratio = REG_READ(SCL_HORZ_FILTER_SCALE_RATIO);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

94

dpp_reg_state->scl_vert_filter_scale_ratio = REG_READ(SCL_VERT_FILTER_SCALE_RATIO);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

95

dpp_reg_state->scl_mode = REG_READ(SCL_MODE);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

96

dpp_reg_state->cm_control = REG_READ(CM_CONTROL);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

97

dpp_reg_state->dpp_control = REG_READ(DPP_CONTROL);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

98

dpp_reg_state->dscl_control = REG_READ(DSCL_CONTROL);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

99

dpp_reg_state->obuf_control = REG_READ(OBUF_CONTROL);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

338

uint32_t scl_mode = REG_READ(SCL_MODE);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

163

dccg_reg_state->dsc_top_control = REG_READ(DSC_TOP_CONTROL);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

164

dccg_reg_state->dscc_interrupt_control_status = REG_READ(DSCC_INTERRUPT_CONTROL_STATUS);

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

188

debug_data = REG_READ(DCHUBBUB_TEST_DEBUG_DATA);

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

52

s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A);

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

53

s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A);

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

55

s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A);

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

56

s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A);

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

58

s->dram_clk_change = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A);

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

62

s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B);

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

63

s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B);

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

65

s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B);

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

66

s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B);

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

68

s->dram_clk_change = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B);

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

72

s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C);

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

73

s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C);

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

75

s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C);

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

76

s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C);

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

78

s->dram_clk_change = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C);

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

82

s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D);

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

83

s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D);

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

85

s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D);

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

86

s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D);

drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c

88

s->dram_clk_change = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D);

drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

517

s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A);

drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

519

s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A);

drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

521

s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A);

drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

522

s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A);

drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

524

s->dram_clk_change = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A);

drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

528

s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B);

drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

530

s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B);

drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

532

s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B);

drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

533

s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B);

drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

535

s->dram_clk_change = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B);

drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

539

s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C);

drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

541

s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C);

drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

543

s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C);

drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

544

s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C);

drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

546

s->dram_clk_change = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C);

drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

550

s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D);

drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

552

s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D);

drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

554

s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D);

drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

555

s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D);

drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

557

s->dram_clk_change = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D);

drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

635

hubbub_state->vm_fault_addr_msb = REG_READ(DCN_VM_FAULT_ADDR_MSB);

drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

638

hubbub_state->vm_fault_addr_msb = REG_READ(DCN_VM_FAULT_ADDR_LSB);

drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

651

hubbub_state->test_debug_data = REG_READ(DCHUBBUB_TEST_DEBUG_DATA);

drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

655

hubbub_state->watermark_change_cntl = REG_READ(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL);

drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c

658

hubbub_state->dram_state_cntl = REG_READ(DCHUBBUB_ARB_DRAM_STATE_CNTL);

drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c

688

prog_wm_value = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A);

drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

407

reg = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A);

drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

412

reg = REG_READ(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A);

drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

417

reg = REG_READ(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A);

drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

422

reg = REG_READ(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A);

drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

427

reg = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A);

drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

432

reg = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A);

drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

437

reg = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A);

drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

447

hubbub_reg_state->det0_ctrl = REG_READ(DCHUBBUB_DET0_CTRL);

drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

448

hubbub_reg_state->det1_ctrl = REG_READ(DCHUBBUB_DET1_CTRL);

drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

449

hubbub_reg_state->det2_ctrl = REG_READ(DCHUBBUB_DET2_CTRL);

drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

450

hubbub_reg_state->det3_ctrl = REG_READ(DCHUBBUB_DET3_CTRL);

drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

451

hubbub_reg_state->compbuf_ctrl = REG_READ(DCHUBBUB_COMPBUF_CTRL);

drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

1010

debug_data = REG_READ(DCHUBBUB_TEST_DEBUG_DATA);

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

832

reg = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A);

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

837

reg = REG_READ(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A);

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

842

reg = REG_READ(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A);

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

847

reg = REG_READ(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A);

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

852

reg = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A);

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

857

reg = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A);

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

862

reg = REG_READ(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A);

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

867

reg = REG_READ(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A);

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

872

reg = REG_READ(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A);

drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

343

reg = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A);

drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

348

reg = REG_READ(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A);

drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

353

reg = REG_READ(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A);

drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

358

reg = REG_READ(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A);

drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

363

reg = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A);

drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

368

reg = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A);

drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

373

reg = REG_READ(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A);

drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

378

reg = REG_READ(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A);

drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

383

reg = REG_READ(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A);

drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

388

reg = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A);

drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

393

reg = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A);

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

502

reg = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A);

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

505

reg = REG_READ(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A);

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

508

reg = REG_READ(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A);

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

511

reg = REG_READ(DCHUBBUB_ARB_FRAC_URG_BW_MALL_A);

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

514

reg = REG_READ(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A);

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

517

reg = REG_READ(DCHUBBUB_ARB_REFCYC_PER_META_TRIP_A);

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

520

reg = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A);

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

529

reg = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A);

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

538

reg = REG_READ(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A);

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

541

reg = REG_READ(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A);

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

543

reg = REG_READ(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK1_A);

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

546

reg = REG_READ(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A);

drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c

548

reg = REG_READ(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK1_A);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

125

value = REG_READ(HUBPREQ_DEBUG_DB);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

1272

if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0)

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

51

uint32_t reg_val = REG_READ(DCHUBP_CNTL);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1359

s->hubp_cntl = REG_READ(DCHUBP_CNTL);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

1362

s->flip_control = REG_READ(DCSURF_FLIP_CONTROL);

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

969

uint32_t reg_val = REG_READ(DCHUBP_CNTL);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

469

s->uclk_pstate_force = REG_READ(UCLK_PSTATE_FORCE);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

472

s->hubp_cntl = REG_READ(DCHUBP_CNTL);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

475

s->flip_control = REG_READ(DCSURF_FLIP_CONTROL);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

483

reg_state->hubp_cntl = REG_READ(DCHUBP_CNTL);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

484

reg_state->mall_config = REG_READ(DCHUBP_MALL_CONFIG);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

485

reg_state->mall_sub_vp = REG_READ(DCHUBP_MALL_SUB_VP);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

486

reg_state->hubp_req_size_config = REG_READ(DCHUBP_REQ_SIZE_CONFIG);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

487

reg_state->hubp_req_size_config_c = REG_READ(DCHUBP_REQ_SIZE_CONFIG_C);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

488

reg_state->vmpg_config = REG_READ(DCHUBP_VMPG_CONFIG);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

489

reg_state->addr_config = REG_READ(DCSURF_ADDR_CONFIG);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

490

reg_state->pri_viewport_dimension = REG_READ(DCSURF_PRI_VIEWPORT_DIMENSION);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

491

reg_state->pri_viewport_dimension_c = REG_READ(DCSURF_PRI_VIEWPORT_DIMENSION_C);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

492

reg_state->pri_viewport_start = REG_READ(DCSURF_PRI_VIEWPORT_START);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

493

reg_state->pri_viewport_start_c = REG_READ(DCSURF_PRI_VIEWPORT_START_C);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

494

reg_state->sec_viewport_dimension = REG_READ(DCSURF_SEC_VIEWPORT_DIMENSION);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

495

reg_state->sec_viewport_dimension_c = REG_READ(DCSURF_SEC_VIEWPORT_DIMENSION_C);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

496

reg_state->sec_viewport_start = REG_READ(DCSURF_SEC_VIEWPORT_START);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

497

reg_state->sec_viewport_start_c = REG_READ(DCSURF_SEC_VIEWPORT_START_C);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

498

reg_state->surface_config = REG_READ(DCSURF_SURFACE_CONFIG);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

499

reg_state->tiling_config = REG_READ(DCSURF_TILING_CONFIG);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

500

reg_state->clk_cntl = REG_READ(HUBP_CLK_CNTL);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

501

reg_state->mall_status = REG_READ(HUBP_MALL_STATUS);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

502

reg_state->measure_win_ctrl_dcfclk = REG_READ(HUBP_MEASURE_WIN_CTRL_DCFCLK);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

503

reg_state->measure_win_ctrl_dppclk = REG_READ(HUBP_MEASURE_WIN_CTRL_DPPCLK);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

505

reg_state->blank_offset_0 = REG_READ(BLANK_OFFSET_0);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

506

reg_state->blank_offset_1 = REG_READ(BLANK_OFFSET_1);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

507

reg_state->cursor_settings = REG_READ(CURSOR_SETTINGS);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

508

reg_state->dcn_cur0_ttu_cntl0 = REG_READ(DCN_CUR0_TTU_CNTL0);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

509

reg_state->dcn_cur0_ttu_cntl1 = REG_READ(DCN_CUR0_TTU_CNTL1);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

510

reg_state->dcn_cur1_ttu_cntl0 = REG_READ(DCN_CUR1_TTU_CNTL0);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

511

reg_state->dcn_cur1_ttu_cntl1 = REG_READ(DCN_CUR1_TTU_CNTL1);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

512

reg_state->dcn_dmdat_vm_cntl = REG_READ(DCN_DMDATA_VM_CNTL);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

513

reg_state->dcn_expansion_mode = REG_READ(DCN_EXPANSION_MODE);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

514

reg_state->dcn_global_ttu_cntl = REG_READ(DCN_GLOBAL_TTU_CNTL);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

515

reg_state->dcn_surf0_ttu_cntl0 = REG_READ(DCN_SURF0_TTU_CNTL0);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

516

reg_state->dcn_surf0_ttu_cntl1 = REG_READ(DCN_SURF0_TTU_CNTL1);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

517

reg_state->dcn_surf1_ttu_cntl0 = REG_READ(DCN_SURF1_TTU_CNTL0);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

518

reg_state->dcn_surf1_ttu_cntl1 = REG_READ(DCN_SURF1_TTU_CNTL1);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

519

reg_state->dcn_ttu_qos_wm = REG_READ(DCN_TTU_QOS_WM);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

520

reg_state->dcn_vm_mx_l1_tlb_cntl = REG_READ(DCN_VM_MX_L1_TLB_CNTL);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

521

reg_state->dcn_vm_system_aperture_high_addr = REG_READ(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

522

reg_state->dcn_vm_system_aperture_low_addr = REG_READ(DCN_VM_SYSTEM_APERTURE_LOW_ADDR);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

523

reg_state->dcsurf_flip_control = REG_READ(DCSURF_FLIP_CONTROL);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

524

reg_state->dcsurf_flip_control2 = REG_READ(DCSURF_FLIP_CONTROL2);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

525

reg_state->dcsurf_primary_meta_surface_address = REG_READ(DCSURF_PRIMARY_META_SURFACE_ADDRESS);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

526

reg_state->dcsurf_primary_meta_surface_address_c = REG_READ(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

527

reg_state->dcsurf_primary_meta_surface_address_high = REG_READ(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

528

reg_state->dcsurf_primary_meta_surface_address_high_c = REG_READ(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

529

reg_state->dcsurf_primary_surface_address = REG_READ(DCSURF_PRIMARY_SURFACE_ADDRESS);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

530

reg_state->dcsurf_primary_surface_address_c = REG_READ(DCSURF_PRIMARY_SURFACE_ADDRESS_C);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

531

reg_state->dcsurf_primary_surface_address_high = REG_READ(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

532

reg_state->dcsurf_primary_surface_address_high_c = REG_READ(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

533

reg_state->dcsurf_secondary_meta_surface_address = REG_READ(DCSURF_SECONDARY_META_SURFACE_ADDRESS);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

534

reg_state->dcsurf_secondary_meta_surface_address_c = REG_READ(DCSURF_SECONDARY_META_SURFACE_ADDRESS_C);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

535

reg_state->dcsurf_secondary_meta_surface_address_high = REG_READ(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

536

reg_state->dcsurf_secondary_meta_surface_address_high_c = REG_READ(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

537

reg_state->dcsurf_secondary_surface_address = REG_READ(DCSURF_SECONDARY_SURFACE_ADDRESS);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

538

reg_state->dcsurf_secondary_surface_address_c = REG_READ(DCSURF_SECONDARY_SURFACE_ADDRESS_C);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

539

reg_state->dcsurf_secondary_surface_address_high = REG_READ(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

540

reg_state->dcsurf_secondary_surface_address_high_c = REG_READ(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

541

reg_state->dcsurf_surface_control = REG_READ(DCSURF_SURFACE_CONTROL);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

542

reg_state->dcsurf_surface_earliest_inuse = REG_READ(DCSURF_SURFACE_EARLIEST_INUSE);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

543

reg_state->dcsurf_surface_earliest_inuse_c = REG_READ(DCSURF_SURFACE_EARLIEST_INUSE_C);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

544

reg_state->dcsurf_surface_earliest_inuse_high = REG_READ(DCSURF_SURFACE_EARLIEST_INUSE_HIGH);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

545

reg_state->dcsurf_surface_earliest_inuse_high_c = REG_READ(DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

546

reg_state->dcsurf_surface_flip_interrupt = REG_READ(DCSURF_SURFACE_FLIP_INTERRUPT);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

547

reg_state->dcsurf_surface_inuse = REG_READ(DCSURF_SURFACE_INUSE);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

548

reg_state->dcsurf_surface_inuse_c = REG_READ(DCSURF_SURFACE_INUSE_C);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

549

reg_state->dcsurf_surface_inuse_high = REG_READ(DCSURF_SURFACE_INUSE_HIGH);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

550

reg_state->dcsurf_surface_inuse_high_c = REG_READ(DCSURF_SURFACE_INUSE_HIGH_C);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

551

reg_state->dcsurf_surface_pitch = REG_READ(DCSURF_SURFACE_PITCH);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

552

reg_state->dcsurf_surface_pitch_c = REG_READ(DCSURF_SURFACE_PITCH_C);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

553

reg_state->dst_after_scaler = REG_READ(DST_AFTER_SCALER);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

554

reg_state->dst_dimensions = REG_READ(DST_DIMENSIONS);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

555

reg_state->dst_y_delta_drq_limit = REG_READ(DST_Y_DELTA_DRQ_LIMIT);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

556

reg_state->flip_parameters_0 = REG_READ(FLIP_PARAMETERS_0);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

557

reg_state->flip_parameters_1 = REG_READ(FLIP_PARAMETERS_1);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

558

reg_state->flip_parameters_2 = REG_READ(FLIP_PARAMETERS_2);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

559

reg_state->flip_parameters_3 = REG_READ(FLIP_PARAMETERS_3);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

560

reg_state->flip_parameters_4 = REG_READ(FLIP_PARAMETERS_4);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

561

reg_state->flip_parameters_5 = REG_READ(FLIP_PARAMETERS_5);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

562

reg_state->flip_parameters_6 = REG_READ(FLIP_PARAMETERS_6);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

563

reg_state->hubpreq_mem_pwr_ctrl = REG_READ(HUBPREQ_MEM_PWR_CTRL);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

564

reg_state->hubpreq_mem_pwr_status = REG_READ(HUBPREQ_MEM_PWR_STATUS);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

565

reg_state->nom_parameters_0 = REG_READ(NOM_PARAMETERS_0);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

566

reg_state->nom_parameters_1 = REG_READ(NOM_PARAMETERS_1);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

567

reg_state->nom_parameters_2 = REG_READ(NOM_PARAMETERS_2);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

568

reg_state->nom_parameters_3 = REG_READ(NOM_PARAMETERS_3);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

569

reg_state->nom_parameters_4 = REG_READ(NOM_PARAMETERS_4);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

570

reg_state->nom_parameters_5 = REG_READ(NOM_PARAMETERS_5);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

571

reg_state->nom_parameters_6 = REG_READ(NOM_PARAMETERS_6);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

572

reg_state->nom_parameters_7 = REG_READ(NOM_PARAMETERS_7);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

573

reg_state->per_line_delivery = REG_READ(PER_LINE_DELIVERY);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

574

reg_state->per_line_delivery_pre = REG_READ(PER_LINE_DELIVERY_PRE);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

575

reg_state->prefetch_settings = REG_READ(PREFETCH_SETTINGS);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

576

reg_state->prefetch_settings_c = REG_READ(PREFETCH_SETTINGS_C);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

577

reg_state->ref_freq_to_pix_freq = REG_READ(REF_FREQ_TO_PIX_FREQ);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

578

reg_state->uclk_pstate_force = REG_READ(UCLK_PSTATE_FORCE);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

579

reg_state->vblank_parameters_0 = REG_READ(VBLANK_PARAMETERS_0);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

580

reg_state->vblank_parameters_1 = REG_READ(VBLANK_PARAMETERS_1);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

581

reg_state->vblank_parameters_2 = REG_READ(VBLANK_PARAMETERS_2);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

582

reg_state->vblank_parameters_3 = REG_READ(VBLANK_PARAMETERS_3);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

583

reg_state->vblank_parameters_4 = REG_READ(VBLANK_PARAMETERS_4);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

584

reg_state->vblank_parameters_5 = REG_READ(VBLANK_PARAMETERS_5);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

585

reg_state->vblank_parameters_6 = REG_READ(VBLANK_PARAMETERS_6);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

586

reg_state->vmid_settings_0 = REG_READ(VMID_SETTINGS_0);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

587

reg_state->hubpret_control = REG_READ(HUBPRET_CONTROL);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

588

reg_state->hubpret_interrupt = REG_READ(HUBPRET_INTERRUPT);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

589

reg_state->hubpret_mem_pwr_ctrl = REG_READ(HUBPRET_MEM_PWR_CTRL);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

590

reg_state->hubpret_mem_pwr_status = REG_READ(HUBPRET_MEM_PWR_STATUS);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

591

reg_state->hubpret_read_line_ctrl0 = REG_READ(HUBPRET_READ_LINE_CTRL0);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

592

reg_state->hubpret_read_line_ctrl1 = REG_READ(HUBPRET_READ_LINE_CTRL1);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

593

reg_state->hubpret_read_line_status = REG_READ(HUBPRET_READ_LINE_STATUS);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

594

reg_state->hubpret_read_line_value = REG_READ(HUBPRET_READ_LINE_VALUE);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

595

reg_state->hubpret_read_line0 = REG_READ(HUBPRET_READ_LINE0);

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

596

reg_state->hubpret_read_line1 = REG_READ(HUBPRET_READ_LINE1);

drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c

94

reg_val = REG_READ(DCHUBP_CNTL);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

1008

s->uclk_pstate_force = REG_READ(UCLK_PSTATE_FORCE);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

1010

s->hubp_cntl = REG_READ(DCHUBP_CNTL);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

1011

s->flip_control = REG_READ(DCSURF_FLIP_CONTROL);

drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c

781

if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0)

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.c

82

uint32_t value = REG_READ(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst]);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

260

REG_READ(MPC_CRC_RESULT_GB), REG_READ(MPC_CRC_RESULT_C), REG_READ(MPC_CRC_RESULT_AR));

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

263

REG_READ(DPP_TOP0_DPP_CRC_VAL_B_A), REG_READ(DPP_TOP0_DPP_CRC_VAL_R_G));

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

207

uint32_t fb_base = REG_READ(MC_VM_FB_LOCATION_BASE);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

208

uint32_t fb_top = REG_READ(MC_VM_FB_LOCATION_TOP);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

209

uint32_t fb_offset = REG_READ(MC_VM_FB_OFFSET);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1523

mpc_reg_state->mpcc_bot_sel = REG_READ(MPCC_BOT_SEL[mpcc_inst]);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1524

mpc_reg_state->mpcc_control = REG_READ(MPCC_CONTROL[mpcc_inst]);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1525

mpc_reg_state->mpcc_ogam_control = REG_READ(MPCC_OGAM_CONTROL[mpcc_inst]);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1526

mpc_reg_state->mpcc_opp_id = REG_READ(MPCC_OPP_ID[mpcc_inst]);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1527

mpc_reg_state->mpcc_status = REG_READ(MPCC_STATUS[mpcc_inst]);

drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c

1528

mpc_reg_state->mpcc_top_sel = REG_READ(MPCC_TOP_SEL[mpcc_inst]);

drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.c

380

opp_reg_state->fmt_control = REG_READ(FMT_CONTROL);

drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.c

381

opp_reg_state->opp_pipe_control = REG_READ(OPP_PIPE_CONTROL);

drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.c

382

opp_reg_state->opp_pipe_crc_control = REG_READ(OPP_PIPE_CRC_CONTROL);

drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.c

383

opp_reg_state->oppbuf_control = REG_READ(OPPBUF_CONTROL);

drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c

384

opp_reg_state->dpg_control = REG_READ(DPG_CONTROL);

drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c

385

opp_reg_state->fmt_control = REG_READ(FMT_CONTROL);

drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c

386

opp_reg_state->opp_pipe_control = REG_READ(OPP_PIPE_CONTROL);

drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c

387

opp_reg_state->opp_pipe_crc_control = REG_READ(OPP_PIPE_CRC_CONTROL);

drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c

388

opp_reg_state->oppbuf_control = REG_READ(OPPBUF_CONTROL);

drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c

389

opp_reg_state->dscrm_dsc_forward_config = REG_READ(DSCRM_DSC_FORWARD_CONFIG);

drivers/gpu/drm/amd/display/dc/opp/dcn35/dcn35_opp.c

59

opp_reg_state->dpg_control = REG_READ(DPG_CONTROL);

drivers/gpu/drm/amd/display/dc/opp/dcn35/dcn35_opp.c

60

opp_reg_state->fmt_control = REG_READ(FMT_CONTROL);

drivers/gpu/drm/amd/display/dc/opp/dcn35/dcn35_opp.c

61

opp_reg_state->opp_abm_control = REG_READ(OPP_ABM_CONTROL);

drivers/gpu/drm/amd/display/dc/opp/dcn35/dcn35_opp.c

62

opp_reg_state->opp_pipe_control = REG_READ(OPP_PIPE_CONTROL);

drivers/gpu/drm/amd/display/dc/opp/dcn35/dcn35_opp.c

63

opp_reg_state->opp_pipe_crc_control = REG_READ(OPP_PIPE_CRC_CONTROL);

drivers/gpu/drm/amd/display/dc/opp/dcn35/dcn35_opp.c

64

opp_reg_state->oppbuf_control = REG_READ(OPPBUF_CONTROL);

drivers/gpu/drm/amd/display/dc/opp/dcn35/dcn35_opp.c

65

opp_reg_state->dscrm_dsc_forward_config = REG_READ(DSCRM_DSC_FORWARD_CONFIG);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1394

s->otg_master_update_lock = REG_READ(OTG_MASTER_UPDATE_LOCK);

drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

1395

s->otg_double_buffer_control = REG_READ(OTG_DOUBLE_BUFFER_CONTROL);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

314

s->otg_master_update_lock = REG_READ(OTG_MASTER_UPDATE_LOCK);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

315

s->otg_double_buffer_control = REG_READ(OTG_DOUBLE_BUFFER_CONTROL);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

322

optc_reg_state->optc_bytes_per_pixel = REG_READ(OPTC_BYTES_PER_PIXEL);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

323

optc_reg_state->optc_data_format_control = REG_READ(OPTC_DATA_FORMAT_CONTROL);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

324

optc_reg_state->optc_data_source_select = REG_READ(OPTC_DATA_SOURCE_SELECT);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

325

optc_reg_state->optc_input_clock_control = REG_READ(OPTC_INPUT_CLOCK_CONTROL);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

326

optc_reg_state->optc_input_global_control = REG_READ(OPTC_INPUT_GLOBAL_CONTROL);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

327

optc_reg_state->optc_input_spare_register = REG_READ(OPTC_INPUT_SPARE_REGISTER);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

328

optc_reg_state->optc_memory_config = REG_READ(OPTC_MEMORY_CONFIG);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

329

optc_reg_state->optc_rsmu_underflow = REG_READ(OPTC_RSMU_UNDERFLOW);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

330

optc_reg_state->optc_underflow_threshold = REG_READ(OPTC_UNDERFLOW_THRESHOLD);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

331

optc_reg_state->optc_width_control = REG_READ(OPTC_WIDTH_CONTROL);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

332

optc_reg_state->otg_3d_structure_control = REG_READ(OTG_3D_STRUCTURE_CONTROL);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

333

optc_reg_state->otg_clock_control = REG_READ(OTG_CLOCK_CONTROL);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

334

optc_reg_state->otg_control = REG_READ(OTG_CONTROL);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

335

optc_reg_state->otg_count_control = REG_READ(OTG_COUNT_CONTROL);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

336

optc_reg_state->otg_count_reset = REG_READ(OTG_COUNT_RESET);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

337

optc_reg_state->otg_crc_cntl = REG_READ(OTG_CRC_CNTL);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

338

optc_reg_state->otg_crc_sig_blue_control_mask = REG_READ(OTG_CRC_SIG_BLUE_CONTROL_MASK);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

339

optc_reg_state->otg_crc_sig_red_green_mask = REG_READ(OTG_CRC_SIG_RED_GREEN_MASK);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

340

optc_reg_state->otg_crc0_data_b = REG_READ(OTG_CRC0_DATA_B);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

341

optc_reg_state->otg_crc0_data_rg = REG_READ(OTG_CRC0_DATA_RG);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

342

optc_reg_state->otg_crc0_windowa_x_control = REG_READ(OTG_CRC0_WINDOWA_X_CONTROL);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

343

optc_reg_state->otg_crc0_windowa_x_control_readback = REG_READ(OTG_CRC0_WINDOWA_X_CONTROL_READBACK);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

344

optc_reg_state->otg_crc0_windowa_y_control = REG_READ(OTG_CRC0_WINDOWA_Y_CONTROL);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

345

optc_reg_state->otg_crc0_windowa_y_control_readback = REG_READ(OTG_CRC0_WINDOWA_Y_CONTROL_READBACK);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

346

optc_reg_state->otg_crc0_windowb_x_control = REG_READ(OTG_CRC0_WINDOWB_X_CONTROL);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

347

optc_reg_state->otg_crc0_windowb_x_control_readback = REG_READ(OTG_CRC0_WINDOWB_X_CONTROL_READBACK);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

348

optc_reg_state->otg_crc0_windowb_y_control = REG_READ(OTG_CRC0_WINDOWB_Y_CONTROL);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

349

optc_reg_state->otg_crc0_windowb_y_control_readback = REG_READ(OTG_CRC0_WINDOWB_Y_CONTROL_READBACK);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

350

optc_reg_state->otg_crc1_data_b = REG_READ(OTG_CRC1_DATA_B);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

351

optc_reg_state->otg_crc1_data_rg = REG_READ(OTG_CRC1_DATA_RG);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

352

optc_reg_state->otg_crc1_windowa_x_control = REG_READ(OTG_CRC1_WINDOWA_X_CONTROL);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

353

optc_reg_state->otg_crc1_windowa_x_control_readback = REG_READ(OTG_CRC1_WINDOWA_X_CONTROL_READBACK);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

354

optc_reg_state->otg_crc1_windowa_y_control = REG_READ(OTG_CRC1_WINDOWA_Y_CONTROL);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

355

optc_reg_state->otg_crc1_windowa_y_control_readback = REG_READ(OTG_CRC1_WINDOWA_Y_CONTROL_READBACK);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

356

optc_reg_state->otg_crc1_windowb_x_control = REG_READ(OTG_CRC1_WINDOWB_X_CONTROL);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

357

optc_reg_state->otg_crc1_windowb_x_control_readback = REG_READ(OTG_CRC1_WINDOWB_X_CONTROL_READBACK);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

358

optc_reg_state->otg_crc1_windowb_y_control = REG_READ(OTG_CRC1_WINDOWB_Y_CONTROL);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

359

optc_reg_state->otg_crc1_windowb_y_control_readback = REG_READ(OTG_CRC1_WINDOWB_Y_CONTROL_READBACK);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

360

optc_reg_state->otg_crc2_data_b = REG_READ(OTG_CRC2_DATA_B);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

361

optc_reg_state->otg_crc2_data_rg = REG_READ(OTG_CRC2_DATA_RG);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

362

optc_reg_state->otg_crc3_data_b = REG_READ(OTG_CRC3_DATA_B);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

363

optc_reg_state->otg_crc3_data_rg = REG_READ(OTG_CRC3_DATA_RG);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

364

optc_reg_state->otg_dlpc_control = REG_READ(OTG_DLPC_CONTROL);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

365

optc_reg_state->otg_double_buffer_control = REG_READ(OTG_DOUBLE_BUFFER_CONTROL);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

366

optc_reg_state->otg_drr_control2 = REG_READ(OTG_DRR_CONTROL2);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

367

optc_reg_state->otg_drr_control = REG_READ(OTG_DRR_CONTROL);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

368

optc_reg_state->otg_drr_timing_int_status = REG_READ(OTG_DRR_TIMING_INT_STATUS);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

369

optc_reg_state->otg_drr_trigger_window = REG_READ(OTG_DRR_TRIGGER_WINDOW);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

370

optc_reg_state->otg_drr_v_total_change = REG_READ(OTG_DRR_V_TOTAL_CHANGE);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

371

optc_reg_state->otg_dsc_start_position = REG_READ(OTG_DSC_START_POSITION);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

372

optc_reg_state->otg_force_count_now_cntl = REG_READ(OTG_FORCE_COUNT_NOW_CNTL);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

373

optc_reg_state->otg_global_control0 = REG_READ(OTG_GLOBAL_CONTROL0);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

374

optc_reg_state->otg_global_control1 = REG_READ(OTG_GLOBAL_CONTROL1);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

375

optc_reg_state->otg_global_control2 = REG_READ(OTG_GLOBAL_CONTROL2);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

376

optc_reg_state->otg_global_control3 = REG_READ(OTG_GLOBAL_CONTROL3);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

377

optc_reg_state->otg_global_control4 = REG_READ(OTG_GLOBAL_CONTROL4);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

378

optc_reg_state->otg_global_sync_status = REG_READ(OTG_GLOBAL_SYNC_STATUS);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

379

optc_reg_state->otg_gsl_control = REG_READ(OTG_GSL_CONTROL);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

380

optc_reg_state->otg_gsl_vsync_gap = REG_READ(OTG_GSL_VSYNC_GAP);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

381

optc_reg_state->otg_gsl_window_x = REG_READ(OTG_GSL_WINDOW_X);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

382

optc_reg_state->otg_gsl_window_y = REG_READ(OTG_GSL_WINDOW_Y);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

383

optc_reg_state->otg_h_blank_start_end = REG_READ(OTG_H_BLANK_START_END);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

384

optc_reg_state->otg_h_sync_a = REG_READ(OTG_H_SYNC_A);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

385

optc_reg_state->otg_h_sync_a_cntl = REG_READ(OTG_H_SYNC_A_CNTL);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

386

optc_reg_state->otg_h_timing_cntl = REG_READ(OTG_H_TIMING_CNTL);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

387

optc_reg_state->otg_h_total = REG_READ(OTG_H_TOTAL);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

388

optc_reg_state->otg_interlace_control = REG_READ(OTG_INTERLACE_CONTROL);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

389

optc_reg_state->otg_interlace_status = REG_READ(OTG_INTERLACE_STATUS);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

390

optc_reg_state->otg_interrupt_control = REG_READ(OTG_INTERRUPT_CONTROL);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

391

optc_reg_state->otg_long_vblank_status = REG_READ(OTG_LONG_VBLANK_STATUS);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

392

optc_reg_state->otg_m_const_dto0 = REG_READ(OTG_M_CONST_DTO0);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

393

optc_reg_state->otg_m_const_dto1 = REG_READ(OTG_M_CONST_DTO1);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

394

optc_reg_state->otg_manual_force_vsync_next_line = REG_READ(OTG_MANUAL_FORCE_VSYNC_NEXT_LINE);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

395

optc_reg_state->otg_master_en = REG_READ(OTG_MASTER_EN);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

396

optc_reg_state->otg_master_update_lock = REG_READ(OTG_MASTER_UPDATE_LOCK);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

397

optc_reg_state->otg_master_update_mode = REG_READ(OTG_MASTER_UPDATE_MODE);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

398

optc_reg_state->otg_nom_vert_position = REG_READ(OTG_NOM_VERT_POSITION);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

399

optc_reg_state->otg_pipe_update_status = REG_READ(OTG_PIPE_UPDATE_STATUS);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

400

optc_reg_state->otg_pixel_data_readback0 = REG_READ(OTG_PIXEL_DATA_READBACK0);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

401

optc_reg_state->otg_pixel_data_readback1 = REG_READ(OTG_PIXEL_DATA_READBACK1);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

402

optc_reg_state->otg_request_control = REG_READ(OTG_REQUEST_CONTROL);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

403

optc_reg_state->otg_snapshot_control = REG_READ(OTG_SNAPSHOT_CONTROL);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

404

optc_reg_state->otg_snapshot_frame = REG_READ(OTG_SNAPSHOT_FRAME);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

405

optc_reg_state->otg_snapshot_position = REG_READ(OTG_SNAPSHOT_POSITION);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

406

optc_reg_state->otg_snapshot_status = REG_READ(OTG_SNAPSHOT_STATUS);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

407

optc_reg_state->otg_spare_register = REG_READ(OTG_SPARE_REGISTER);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

408

optc_reg_state->otg_static_screen_control = REG_READ(OTG_STATIC_SCREEN_CONTROL);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

409

optc_reg_state->otg_status = REG_READ(OTG_STATUS);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

410

optc_reg_state->otg_status_frame_count = REG_READ(OTG_STATUS_FRAME_COUNT);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

411

optc_reg_state->otg_status_hv_count = REG_READ(OTG_STATUS_HV_COUNT);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

412

optc_reg_state->otg_status_position = REG_READ(OTG_STATUS_POSITION);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

413

optc_reg_state->otg_status_vf_count = REG_READ(OTG_STATUS_VF_COUNT);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

414

optc_reg_state->otg_stereo_control = REG_READ(OTG_STEREO_CONTROL);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

415

optc_reg_state->otg_stereo_force_next_eye = REG_READ(OTG_STEREO_FORCE_NEXT_EYE);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

416

optc_reg_state->otg_stereo_status = REG_READ(OTG_STEREO_STATUS);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

417

optc_reg_state->otg_trig_manual_control = REG_READ(OTG_TRIG_MANUAL_CONTROL);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

418

optc_reg_state->otg_triga_cntl = REG_READ(OTG_TRIGA_CNTL);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

419

optc_reg_state->otg_triga_manual_trig = REG_READ(OTG_TRIGA_MANUAL_TRIG);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

420

optc_reg_state->otg_trigb_cntl = REG_READ(OTG_TRIGB_CNTL);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

421

optc_reg_state->otg_trigb_manual_trig = REG_READ(OTG_TRIGB_MANUAL_TRIG);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

422

optc_reg_state->otg_update_lock = REG_READ(OTG_UPDATE_LOCK);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

423

optc_reg_state->otg_v_blank_start_end = REG_READ(OTG_V_BLANK_START_END);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

424

optc_reg_state->otg_v_count_stop_control = REG_READ(OTG_V_COUNT_STOP_CONTROL);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

425

optc_reg_state->otg_v_count_stop_control2 = REG_READ(OTG_V_COUNT_STOP_CONTROL2);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

426

optc_reg_state->otg_v_sync_a = REG_READ(OTG_V_SYNC_A);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

427

optc_reg_state->otg_v_sync_a_cntl = REG_READ(OTG_V_SYNC_A_CNTL);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

428

optc_reg_state->otg_v_total = REG_READ(OTG_V_TOTAL);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

429

optc_reg_state->otg_v_total_control = REG_READ(OTG_V_TOTAL_CONTROL);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

430

optc_reg_state->otg_v_total_int_status = REG_READ(OTG_V_TOTAL_INT_STATUS);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

431

optc_reg_state->otg_v_total_max = REG_READ(OTG_V_TOTAL_MAX);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

432

optc_reg_state->otg_v_total_mid = REG_READ(OTG_V_TOTAL_MID);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

433

optc_reg_state->otg_v_total_min = REG_READ(OTG_V_TOTAL_MIN);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

434

optc_reg_state->otg_vert_sync_control = REG_READ(OTG_VERT_SYNC_CONTROL);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

435

optc_reg_state->otg_vertical_interrupt0_control = REG_READ(OTG_VERTICAL_INTERRUPT0_CONTROL);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

436

optc_reg_state->otg_vertical_interrupt0_position = REG_READ(OTG_VERTICAL_INTERRUPT0_POSITION);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

437

optc_reg_state->otg_vertical_interrupt1_control = REG_READ(OTG_VERTICAL_INTERRUPT1_CONTROL);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

438

optc_reg_state->otg_vertical_interrupt1_position = REG_READ(OTG_VERTICAL_INTERRUPT1_POSITION);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

439

optc_reg_state->otg_vertical_interrupt2_control = REG_READ(OTG_VERTICAL_INTERRUPT2_CONTROL);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

440

optc_reg_state->otg_vertical_interrupt2_position = REG_READ(OTG_VERTICAL_INTERRUPT2_POSITION);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

441

optc_reg_state->otg_vready_param = REG_READ(OTG_VREADY_PARAM);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

442

optc_reg_state->otg_vstartup_param = REG_READ(OTG_VSTARTUP_PARAM);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

443

optc_reg_state->otg_vsync_nom_int_status = REG_READ(OTG_VSYNC_NOM_INT_STATUS);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

444

optc_reg_state->otg_vupdate_keepout = REG_READ(OTG_VUPDATE_KEEPOUT);

drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c

445

optc_reg_state->otg_vupdate_param = REG_READ(OTG_VUPDATE_PARAM);

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1373

uint32_t value = REG_READ(CC_DC_PIPE_DIS);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2295

uint32_t value = REG_READ(CC_DC_PIPE_DIS);

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

954

uint32_t value = REG_READ(CC_DC_PIPE_DIS);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2158

uint32_t value = REG_READ(CC_DC_PIPE_DIS);

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1661

uint32_t value = REG_READ(CC_DC_PIPE_DIS);

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1847

uint32_t value = REG_READ(CC_DC_PIPE_DIS);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

288

return REG_READ(DMCUB_INBOX1_WPTR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

293

return REG_READ(DMCUB_INBOX1_RPTR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

319

return REG_READ(DMCUB_OUTBOX1_WPTR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

341

return REG_READ(DMCUB_OUTBOX0_WPTR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

379

test.all = REG_READ(DMCUB_GPINT_DATAIN1);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

386

return REG_READ(DMCUB_SCRATCH7);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

393

status.all = REG_READ(DMCUB_SCRATCH0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

407

boot_options.all = REG_READ(DMCUB_SCRATCH14);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

414

return REG_READ(DMCUB_TIMER_CURRENT);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

433

dmub->debug.scratch[0] = REG_READ(DMCUB_SCRATCH0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

434

dmub->debug.scratch[1] = REG_READ(DMCUB_SCRATCH1);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

435

dmub->debug.scratch[2] = REG_READ(DMCUB_SCRATCH2);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

436

dmub->debug.scratch[3] = REG_READ(DMCUB_SCRATCH3);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

437

dmub->debug.scratch[4] = REG_READ(DMCUB_SCRATCH4);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

438

dmub->debug.scratch[5] = REG_READ(DMCUB_SCRATCH5);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

439

dmub->debug.scratch[6] = REG_READ(DMCUB_SCRATCH6);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

440

dmub->debug.scratch[7] = REG_READ(DMCUB_SCRATCH7);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

441

dmub->debug.scratch[8] = REG_READ(DMCUB_SCRATCH8);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

442

dmub->debug.scratch[9] = REG_READ(DMCUB_SCRATCH9);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

443

dmub->debug.scratch[10] = REG_READ(DMCUB_SCRATCH10);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

444

dmub->debug.scratch[11] = REG_READ(DMCUB_SCRATCH11);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

445

dmub->debug.scratch[12] = REG_READ(DMCUB_SCRATCH12);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

446

dmub->debug.scratch[13] = REG_READ(DMCUB_SCRATCH13);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

447

dmub->debug.scratch[14] = REG_READ(DMCUB_SCRATCH14);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

448

dmub->debug.scratch[15] = REG_READ(DMCUB_SCRATCH15);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

450

dmub->debug.undefined_address_fault_addr = REG_READ(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

451

dmub->debug.inst_fetch_fault_addr = REG_READ(DMCUB_INST_FETCH_FAULT_ADDR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

452

dmub->debug.data_write_fault_addr = REG_READ(DMCUB_DATA_WRITE_FAULT_ADDR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

454

dmub->debug.inbox1_rptr = REG_READ(DMCUB_INBOX1_RPTR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

455

dmub->debug.inbox1_wptr = REG_READ(DMCUB_INBOX1_WPTR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

456

dmub->debug.inbox1_size = REG_READ(DMCUB_INBOX1_SIZE);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

458

dmub->debug.inbox0_rptr = REG_READ(DMCUB_INBOX0_RPTR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

459

dmub->debug.inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

460

dmub->debug.inbox0_size = REG_READ(DMCUB_INBOX0_SIZE);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

111

scratch = REG_READ(DMCUB_SCRATCH7);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

253

return REG_READ(DMCUB_INBOX1_WPTR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

258

return REG_READ(DMCUB_INBOX1_RPTR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

279

return REG_READ(DMCUB_OUTBOX1_WPTR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

296

status.all = REG_READ(DMCUB_SCRATCH0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

328

test.all = REG_READ(DMCUB_GPINT_DATAIN1);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

335

return REG_READ(DMCUB_SCRATCH7);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

340

uint32_t dataout = REG_READ(DMCUB_GPINT_DATAOUT);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

357

status.all = REG_READ(DMCUB_SCRATCH0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

365

option.all = REG_READ(DMCUB_SCRATCH14);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

391

boot_options.all = REG_READ(DMCUB_SCRATCH14);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

406

return REG_READ(DMCUB_OUTBOX0_WPTR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

416

return REG_READ(DMCUB_TIMER_CURRENT);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

435

dmub->debug.scratch[0] = REG_READ(DMCUB_SCRATCH0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

436

dmub->debug.scratch[1] = REG_READ(DMCUB_SCRATCH1);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

437

dmub->debug.scratch[2] = REG_READ(DMCUB_SCRATCH2);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

438

dmub->debug.scratch[3] = REG_READ(DMCUB_SCRATCH3);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

439

dmub->debug.scratch[4] = REG_READ(DMCUB_SCRATCH4);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

440

dmub->debug.scratch[5] = REG_READ(DMCUB_SCRATCH5);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

441

dmub->debug.scratch[6] = REG_READ(DMCUB_SCRATCH6);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

442

dmub->debug.scratch[7] = REG_READ(DMCUB_SCRATCH7);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

443

dmub->debug.scratch[8] = REG_READ(DMCUB_SCRATCH8);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

444

dmub->debug.scratch[9] = REG_READ(DMCUB_SCRATCH9);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

445

dmub->debug.scratch[10] = REG_READ(DMCUB_SCRATCH10);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

446

dmub->debug.scratch[11] = REG_READ(DMCUB_SCRATCH11);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

447

dmub->debug.scratch[12] = REG_READ(DMCUB_SCRATCH12);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

448

dmub->debug.scratch[13] = REG_READ(DMCUB_SCRATCH13);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

449

dmub->debug.scratch[14] = REG_READ(DMCUB_SCRATCH14);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

450

dmub->debug.scratch[15] = REG_READ(DMCUB_SCRATCH15);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

452

dmub->debug.undefined_address_fault_addr = REG_READ(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

453

dmub->debug.inst_fetch_fault_addr = REG_READ(DMCUB_INST_FETCH_FAULT_ADDR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

454

dmub->debug.data_write_fault_addr = REG_READ(DMCUB_DATA_WRITE_FAULT_ADDR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

456

dmub->debug.inbox1_rptr = REG_READ(DMCUB_INBOX1_RPTR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

457

dmub->debug.inbox1_wptr = REG_READ(DMCUB_INBOX1_WPTR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

458

dmub->debug.inbox1_size = REG_READ(DMCUB_INBOX1_SIZE);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

460

dmub->debug.inbox0_rptr = REG_READ(DMCUB_INBOX0_RPTR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

461

dmub->debug.inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

462

dmub->debug.inbox0_size = REG_READ(DMCUB_INBOX0_SIZE);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

464

dmub->debug.outbox1_rptr = REG_READ(DMCUB_OUTBOX1_RPTR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

465

dmub->debug.outbox1_wptr = REG_READ(DMCUB_OUTBOX1_WPTR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

466

dmub->debug.outbox1_size = REG_READ(DMCUB_OUTBOX1_SIZE);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

492

uint32_t fw_boot_status = REG_READ(DMCUB_SCRATCH0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

110

scratch = REG_READ(DMCUB_SCRATCH7);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

295

return REG_READ(DMCUB_INBOX1_WPTR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

300

return REG_READ(DMCUB_INBOX1_RPTR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

321

return REG_READ(DMCUB_OUTBOX1_WPTR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

338

status.all = REG_READ(DMCUB_SCRATCH0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

365

test.all = REG_READ(DMCUB_GPINT_DATAIN1);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

372

return REG_READ(DMCUB_SCRATCH7);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

377

uint32_t dataout = REG_READ(DMCUB_GPINT_DATAOUT);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

394

status.all = REG_READ(DMCUB_SCRATCH0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

410

boot_options.all = REG_READ(DMCUB_SCRATCH14);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

425

return REG_READ(DMCUB_OUTBOX0_WPTR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

435

return REG_READ(DMCUB_TIMER_CURRENT);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

454

dmub->debug.scratch[0] = REG_READ(DMCUB_SCRATCH0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

455

dmub->debug.scratch[1] = REG_READ(DMCUB_SCRATCH1);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

456

dmub->debug.scratch[2] = REG_READ(DMCUB_SCRATCH2);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

457

dmub->debug.scratch[3] = REG_READ(DMCUB_SCRATCH3);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

458

dmub->debug.scratch[4] = REG_READ(DMCUB_SCRATCH4);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

459

dmub->debug.scratch[5] = REG_READ(DMCUB_SCRATCH5);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

460

dmub->debug.scratch[6] = REG_READ(DMCUB_SCRATCH6);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

461

dmub->debug.scratch[7] = REG_READ(DMCUB_SCRATCH7);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

462

dmub->debug.scratch[8] = REG_READ(DMCUB_SCRATCH8);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

463

dmub->debug.scratch[9] = REG_READ(DMCUB_SCRATCH9);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

464

dmub->debug.scratch[10] = REG_READ(DMCUB_SCRATCH10);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

465

dmub->debug.scratch[11] = REG_READ(DMCUB_SCRATCH11);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

466

dmub->debug.scratch[12] = REG_READ(DMCUB_SCRATCH12);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

467

dmub->debug.scratch[13] = REG_READ(DMCUB_SCRATCH13);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

468

dmub->debug.scratch[14] = REG_READ(DMCUB_SCRATCH14);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

469

dmub->debug.scratch[15] = REG_READ(DMCUB_SCRATCH15);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

470

dmub->debug.scratch[16] = REG_READ(DMCUB_SCRATCH16);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

472

dmub->debug.undefined_address_fault_addr = REG_READ(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

473

dmub->debug.inst_fetch_fault_addr = REG_READ(DMCUB_INST_FETCH_FAULT_ADDR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

474

dmub->debug.data_write_fault_addr = REG_READ(DMCUB_DATA_WRITE_FAULT_ADDR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

476

dmub->debug.inbox1_rptr = REG_READ(DMCUB_INBOX1_RPTR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

477

dmub->debug.inbox1_wptr = REG_READ(DMCUB_INBOX1_WPTR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

478

dmub->debug.inbox1_size = REG_READ(DMCUB_INBOX1_SIZE);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

480

dmub->debug.inbox0_rptr = REG_READ(DMCUB_INBOX0_RPTR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

481

dmub->debug.inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

482

dmub->debug.inbox0_size = REG_READ(DMCUB_INBOX0_SIZE);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

484

dmub->debug.outbox1_rptr = REG_READ(DMCUB_OUTBOX1_RPTR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

485

dmub->debug.outbox1_wptr = REG_READ(DMCUB_OUTBOX1_WPTR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

486

dmub->debug.outbox1_size = REG_READ(DMCUB_OUTBOX1_SIZE);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

503

dmub->debug.gpint_datain0 = REG_READ(DMCUB_GPINT_DATAIN0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

530

return REG_READ(DMCUB_SCRATCH17);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

538

index = REG_READ(DMCUB_SCRATCH15);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

548

index = REG_READ(DMCUB_SCRATCH23);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

112

scratch = REG_READ(DMCUB_SCRATCH7);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

289

return REG_READ(DMCUB_INBOX1_WPTR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

294

return REG_READ(DMCUB_INBOX1_RPTR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

315

return REG_READ(DMCUB_OUTBOX1_WPTR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

332

status.all = REG_READ(DMCUB_SCRATCH0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

359

test.all = REG_READ(DMCUB_GPINT_DATAIN1);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

366

return REG_READ(DMCUB_SCRATCH7);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

371

uint32_t dataout = REG_READ(DMCUB_GPINT_DATAOUT);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

388

status.all = REG_READ(DMCUB_SCRATCH0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

396

option.all = REG_READ(DMCUB_SCRATCH14);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

432

boot_options.all = REG_READ(DMCUB_SCRATCH14);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

447

return REG_READ(DMCUB_OUTBOX0_WPTR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

457

return REG_READ(DMCUB_TIMER_CURRENT);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

476

dmub->debug.scratch[0] = REG_READ(DMCUB_SCRATCH0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

477

dmub->debug.scratch[1] = REG_READ(DMCUB_SCRATCH1);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

478

dmub->debug.scratch[2] = REG_READ(DMCUB_SCRATCH2);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

479

dmub->debug.scratch[3] = REG_READ(DMCUB_SCRATCH3);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

480

dmub->debug.scratch[4] = REG_READ(DMCUB_SCRATCH4);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

481

dmub->debug.scratch[5] = REG_READ(DMCUB_SCRATCH5);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

482

dmub->debug.scratch[6] = REG_READ(DMCUB_SCRATCH6);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

483

dmub->debug.scratch[7] = REG_READ(DMCUB_SCRATCH7);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

484

dmub->debug.scratch[8] = REG_READ(DMCUB_SCRATCH8);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

485

dmub->debug.scratch[9] = REG_READ(DMCUB_SCRATCH9);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

486

dmub->debug.scratch[10] = REG_READ(DMCUB_SCRATCH10);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

487

dmub->debug.scratch[11] = REG_READ(DMCUB_SCRATCH11);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

488

dmub->debug.scratch[12] = REG_READ(DMCUB_SCRATCH12);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

489

dmub->debug.scratch[13] = REG_READ(DMCUB_SCRATCH13);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

490

dmub->debug.scratch[14] = REG_READ(DMCUB_SCRATCH14);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

491

dmub->debug.scratch[15] = REG_READ(DMCUB_SCRATCH15);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

492

dmub->debug.scratch[16] = REG_READ(DMCUB_SCRATCH16);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

494

dmub->debug.undefined_address_fault_addr = REG_READ(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

495

dmub->debug.inst_fetch_fault_addr = REG_READ(DMCUB_INST_FETCH_FAULT_ADDR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

496

dmub->debug.data_write_fault_addr = REG_READ(DMCUB_DATA_WRITE_FAULT_ADDR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

498

dmub->debug.inbox1_rptr = REG_READ(DMCUB_INBOX1_RPTR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

499

dmub->debug.inbox1_wptr = REG_READ(DMCUB_INBOX1_WPTR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

500

dmub->debug.inbox1_size = REG_READ(DMCUB_INBOX1_SIZE);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

502

dmub->debug.inbox0_rptr = REG_READ(DMCUB_INBOX0_RPTR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

503

dmub->debug.inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

504

dmub->debug.inbox0_size = REG_READ(DMCUB_INBOX0_SIZE);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

506

dmub->debug.outbox1_rptr = REG_READ(DMCUB_OUTBOX1_RPTR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

507

dmub->debug.outbox1_wptr = REG_READ(DMCUB_OUTBOX1_WPTR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

508

dmub->debug.outbox1_size = REG_READ(DMCUB_OUTBOX1_SIZE);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

525

dmub->debug.gpint_datain0 = REG_READ(DMCUB_GPINT_DATAIN0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

537

fw_version = REG_READ(DMCUB_SCRATCH1);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

542

dmub->preos_info.boot_status = REG_READ(DMCUB_SCRATCH0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

543

dmub->preos_info.fw_version = REG_READ(DMCUB_SCRATCH1);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

544

dmub->preos_info.boot_options = REG_READ(DMCUB_SCRATCH14);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

550

offset_low = REG_READ(DMCUB_REGION3_CW5_OFFSET);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

551

offset_high = REG_READ(DMCUB_REGION3_CW5_OFFSET_HIGH);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

558

base_addr = REG_READ(DMCUB_REGION3_CW5_BASE_ADDRESS) & 0x1FFFFFFF;

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

581

uint32_t fw_boot_status = REG_READ(DMCUB_SCRATCH0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

598

return REG_READ(DMCUB_SCRATCH17);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

610

status.all = REG_READ(DMCUB_SCRATCH0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

280

return REG_READ(DMCUB_INBOX1_WPTR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

285

return REG_READ(DMCUB_INBOX1_RPTR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

306

return REG_READ(DMCUB_OUTBOX1_WPTR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

323

status.all = REG_READ(DMCUB_SCRATCH0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

350

test.all = REG_READ(DMCUB_GPINT_DATAIN1);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

357

return REG_READ(DMCUB_SCRATCH7);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

362

uint32_t dataout = REG_READ(DMCUB_GPINT_DATAOUT);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

379

status.all = REG_READ(DMCUB_SCRATCH0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

397

boot_options.all = REG_READ(DMCUB_SCRATCH14);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

412

return REG_READ(DMCUB_OUTBOX0_WPTR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

422

return REG_READ(DMCUB_TIMER_CURRENT);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

441

dmub->debug.scratch[0] = REG_READ(DMCUB_SCRATCH0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

442

dmub->debug.scratch[1] = REG_READ(DMCUB_SCRATCH1);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

443

dmub->debug.scratch[2] = REG_READ(DMCUB_SCRATCH2);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

444

dmub->debug.scratch[3] = REG_READ(DMCUB_SCRATCH3);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

445

dmub->debug.scratch[4] = REG_READ(DMCUB_SCRATCH4);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

446

dmub->debug.scratch[5] = REG_READ(DMCUB_SCRATCH5);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

447

dmub->debug.scratch[6] = REG_READ(DMCUB_SCRATCH6);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

448

dmub->debug.scratch[7] = REG_READ(DMCUB_SCRATCH7);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

449

dmub->debug.scratch[8] = REG_READ(DMCUB_SCRATCH8);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

450

dmub->debug.scratch[9] = REG_READ(DMCUB_SCRATCH9);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

451

dmub->debug.scratch[10] = REG_READ(DMCUB_SCRATCH10);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

452

dmub->debug.scratch[11] = REG_READ(DMCUB_SCRATCH11);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

453

dmub->debug.scratch[12] = REG_READ(DMCUB_SCRATCH12);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

454

dmub->debug.scratch[13] = REG_READ(DMCUB_SCRATCH13);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

455

dmub->debug.scratch[14] = REG_READ(DMCUB_SCRATCH14);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

456

dmub->debug.scratch[15] = REG_READ(DMCUB_SCRATCH15);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

457

dmub->debug.scratch[16] = REG_READ(DMCUB_SCRATCH16);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

459

dmub->debug.undefined_address_fault_addr = REG_READ(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

460

dmub->debug.inst_fetch_fault_addr = REG_READ(DMCUB_INST_FETCH_FAULT_ADDR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

461

dmub->debug.data_write_fault_addr = REG_READ(DMCUB_DATA_WRITE_FAULT_ADDR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

463

dmub->debug.inbox1_rptr = REG_READ(DMCUB_INBOX1_RPTR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

464

dmub->debug.inbox1_wptr = REG_READ(DMCUB_INBOX1_WPTR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

465

dmub->debug.inbox1_size = REG_READ(DMCUB_INBOX1_SIZE);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

467

dmub->debug.inbox0_rptr = REG_READ(DMCUB_INBOX0_RPTR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

468

dmub->debug.inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

469

dmub->debug.inbox0_size = REG_READ(DMCUB_INBOX0_SIZE);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

471

dmub->debug.outbox1_rptr = REG_READ(DMCUB_OUTBOX1_RPTR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

472

dmub->debug.outbox1_wptr = REG_READ(DMCUB_OUTBOX1_WPTR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

473

dmub->debug.outbox1_size = REG_READ(DMCUB_OUTBOX1_SIZE);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

496

dmub->debug.gpint_datain0 = REG_READ(DMCUB_GPINT_DATAIN0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

523

return REG_READ(DMCUB_SCRATCH17);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

610

dwords[0] = REG_READ(DMCUB_REG_INBOX0_RSP);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

611

dwords[1] = REG_READ(DMCUB_REG_INBOX0_MSG0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

612

dwords[2] = REG_READ(DMCUB_REG_INBOX0_MSG1);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

613

dwords[3] = REG_READ(DMCUB_REG_INBOX0_MSG2);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

614

dwords[4] = REG_READ(DMCUB_REG_INBOX0_MSG3);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

615

dwords[5] = REG_READ(DMCUB_REG_INBOX0_MSG4);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

616

dwords[6] = REG_READ(DMCUB_REG_INBOX0_MSG5);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

617

dwords[7] = REG_READ(DMCUB_REG_INBOX0_MSG6);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

618

dwords[8] = REG_READ(DMCUB_REG_INBOX0_MSG7);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

619

dwords[9] = REG_READ(DMCUB_REG_INBOX0_MSG8);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

620

dwords[10] = REG_READ(DMCUB_REG_INBOX0_MSG9);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

621

dwords[11] = REG_READ(DMCUB_REG_INBOX0_MSG10);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

622

dwords[12] = REG_READ(DMCUB_REG_INBOX0_MSG11);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

623

dwords[13] = REG_READ(DMCUB_REG_INBOX0_MSG12);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

624

dwords[14] = REG_READ(DMCUB_REG_INBOX0_MSG13);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

625

dwords[15] = REG_READ(DMCUB_REG_INBOX0_MSG14);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

651

*msg = REG_READ(DMCUB_REG_OUTBOX0_MSG0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

84

scratch = REG_READ(DMCUB_SCRATCH7);

drivers/gpu/drm/gma500/cdv_device.c

125

blc_pwm_ctl = REG_READ(BLC_PWM_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK;

drivers/gpu/drm/gma500/cdv_device.c

241

regs->cdv.saveDSPCLK_GATE_D = REG_READ(DSPCLK_GATE_D);

drivers/gpu/drm/gma500/cdv_device.c

242

regs->cdv.saveRAMCLK_GATE_D = REG_READ(RAMCLK_GATE_D);

drivers/gpu/drm/gma500/cdv_device.c

244

regs->cdv.saveDSPARB = REG_READ(DSPARB);

drivers/gpu/drm/gma500/cdv_device.c

245

regs->cdv.saveDSPFW[0] = REG_READ(DSPFW1);

drivers/gpu/drm/gma500/cdv_device.c

246

regs->cdv.saveDSPFW[1] = REG_READ(DSPFW2);

drivers/gpu/drm/gma500/cdv_device.c

247

regs->cdv.saveDSPFW[2] = REG_READ(DSPFW3);

drivers/gpu/drm/gma500/cdv_device.c

248

regs->cdv.saveDSPFW[3] = REG_READ(DSPFW4);

drivers/gpu/drm/gma500/cdv_device.c

249

regs->cdv.saveDSPFW[4] = REG_READ(DSPFW5);

drivers/gpu/drm/gma500/cdv_device.c

250

regs->cdv.saveDSPFW[5] = REG_READ(DSPFW6);

drivers/gpu/drm/gma500/cdv_device.c

252

regs->cdv.saveADPA = REG_READ(ADPA);

drivers/gpu/drm/gma500/cdv_device.c

254

regs->cdv.savePP_CONTROL = REG_READ(PP_CONTROL);

drivers/gpu/drm/gma500/cdv_device.c

255

regs->cdv.savePFIT_PGM_RATIOS = REG_READ(PFIT_PGM_RATIOS);

drivers/gpu/drm/gma500/cdv_device.c

256

regs->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL);

drivers/gpu/drm/gma500/cdv_device.c

257

regs->saveBLC_PWM_CTL2 = REG_READ(BLC_PWM_CTL2);

drivers/gpu/drm/gma500/cdv_device.c

258

regs->cdv.saveLVDS = REG_READ(LVDS);

drivers/gpu/drm/gma500/cdv_device.c

260

regs->cdv.savePFIT_CONTROL = REG_READ(PFIT_CONTROL);

drivers/gpu/drm/gma500/cdv_device.c

262

regs->cdv.savePP_ON_DELAYS = REG_READ(PP_ON_DELAYS);

drivers/gpu/drm/gma500/cdv_device.c

263

regs->cdv.savePP_OFF_DELAYS = REG_READ(PP_OFF_DELAYS);

drivers/gpu/drm/gma500/cdv_device.c

264

regs->cdv.savePP_CYCLE = REG_READ(PP_CYCLE);

drivers/gpu/drm/gma500/cdv_device.c

266

regs->cdv.saveVGACNTRL = REG_READ(VGACNTRL);

drivers/gpu/drm/gma500/cdv_device.c

268

regs->cdv.saveIER = REG_READ(PSB_INT_ENABLE_R);

drivers/gpu/drm/gma500/cdv_device.c

269

regs->cdv.saveIMR = REG_READ(PSB_INT_MASK_R);

drivers/gpu/drm/gma500/cdv_device.c

305

temp = REG_READ(DPLL_A);

drivers/gpu/drm/gma500/cdv_device.c

308

REG_READ(DPLL_A);

drivers/gpu/drm/gma500/cdv_device.c

311

temp = REG_READ(DPLL_B);

drivers/gpu/drm/gma500/cdv_device.c

314

REG_READ(DPLL_B);

drivers/gpu/drm/gma500/cdv_device.c

37

REG_READ(vga_reg);

drivers/gpu/drm/gma500/cdv_device.c

420

REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT));

drivers/gpu/drm/gma500/cdv_device.c

427

u32 hotplug = REG_READ(PORT_HOTPLUG_EN);

drivers/gpu/drm/gma500/cdv_device.c

433

REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT));

drivers/gpu/drm/gma500/cdv_device.c

52

if (REG_READ(SDVOB) & SDVO_DETECTED) {

drivers/gpu/drm/gma500/cdv_device.c

54

if (REG_READ(DP_B) & DP_DETECTED)

drivers/gpu/drm/gma500/cdv_device.c

58

if (REG_READ(SDVOC) & SDVO_DETECTED) {

drivers/gpu/drm/gma500/cdv_device.c

60

if (REG_READ(DP_C) & DP_DETECTED)

drivers/gpu/drm/gma500/cdv_device.c

72

return REG_READ(BLC_PWM_CTL2) & PWM_LEGACY_MODE;

drivers/gpu/drm/gma500/cdv_device.c

77

u32 max = REG_READ(BLC_PWM_CTL);

drivers/gpu/drm/gma500/cdv_device.c

95

u32 val = REG_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;

drivers/gpu/drm/gma500/cdv_intel_crt.c

112

dpll_md = REG_READ(dpll_md_reg);

drivers/gpu/drm/gma500/cdv_intel_crt.c

152

orig = hotplug_en = REG_READ(PORT_HOTPLUG_EN);

drivers/gpu/drm/gma500/cdv_intel_crt.c

166

if (!(REG_READ(PORT_HOTPLUG_EN) &

drivers/gpu/drm/gma500/cdv_intel_crt.c

173

if ((REG_READ(PORT_HOTPLUG_STAT) & CRT_HOTPLUG_MONITOR_MASK) !=

drivers/gpu/drm/gma500/cdv_intel_crt.c

49

temp = REG_READ(reg);

drivers/gpu/drm/gma500/cdv_intel_display.c

135

ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);

drivers/gpu/drm/gma500/cdv_intel_display.c

147

ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);

drivers/gpu/drm/gma500/cdv_intel_display.c

153

*val = REG_READ(SB_DATA);

drivers/gpu/drm/gma500/cdv_intel_display.c

170

ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);

drivers/gpu/drm/gma500/cdv_intel_display.c

183

ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);

drivers/gpu/drm/gma500/cdv_intel_display.c

204

REG_READ(DPIO_CFG);

drivers/gpu/drm/gma500/cdv_intel_display.c

473

if (REG_READ(FW_BLC_SELF) & FW_BLC_SELF_EN) {

drivers/gpu/drm/gma500/cdv_intel_display.c

476

REG_WRITE(FW_BLC_SELF, (REG_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN));

drivers/gpu/drm/gma500/cdv_intel_display.c

477

REG_READ(FW_BLC_SELF);

drivers/gpu/drm/gma500/cdv_intel_display.c

485

REG_READ(OV_OVADD);

drivers/gpu/drm/gma500/cdv_intel_display.c

501

fw = REG_READ(DSPFW1);

drivers/gpu/drm/gma500/cdv_intel_display.c

508

fw = REG_READ(DSPFW2);

drivers/gpu/drm/gma500/cdv_intel_display.c

537

REG_READ(FW_BLC_SELF);

drivers/gpu/drm/gma500/cdv_intel_display.c

564

pfit_control = REG_READ(PFIT_CONTROL);

drivers/gpu/drm/gma500/cdv_intel_display.c

685

pipeconf = REG_READ(map->conf);

drivers/gpu/drm/gma500/cdv_intel_display.c

705

if ((REG_READ(LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)

drivers/gpu/drm/gma500/cdv_intel_display.c

724

REG_READ(map->dpll);

drivers/gpu/drm/gma500/cdv_intel_display.c

736

u32 lvds = REG_READ(LVDS);

drivers/gpu/drm/gma500/cdv_intel_display.c

756

REG_READ(LVDS);

drivers/gpu/drm/gma500/cdv_intel_display.c

769

(REG_READ(map->dpll) & ~DPLL_LOCK) | DPLL_VCO_ENABLE);

drivers/gpu/drm/gma500/cdv_intel_display.c

770

REG_READ(map->dpll);

drivers/gpu/drm/gma500/cdv_intel_display.c

774

if (!(REG_READ(map->dpll) & DPLL_LOCK)) {

drivers/gpu/drm/gma500/cdv_intel_display.c

805

REG_READ(map->conf);

drivers/gpu/drm/gma500/cdv_intel_display.c

850

dpll = REG_READ(map->dpll);

drivers/gpu/drm/gma500/cdv_intel_display.c

852

fp = REG_READ(map->fp0);

drivers/gpu/drm/gma500/cdv_intel_display.c

854

fp = REG_READ(map->fp1);

drivers/gpu/drm/gma500/cdv_intel_display.c

855

is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN);

drivers/gpu/drm/gma500/cdv_intel_display.c

930

htot = REG_READ(map->htotal);

drivers/gpu/drm/gma500/cdv_intel_display.c

931

hsync = REG_READ(map->hsync);

drivers/gpu/drm/gma500/cdv_intel_display.c

932

vtot = REG_READ(map->vtotal);

drivers/gpu/drm/gma500/cdv_intel_display.c

933

vsync = REG_READ(map->vsync);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1171

uint32_t dp_reg = REG_READ(intel_dp->output_reg);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1361

REG_READ(intel_dp->output_reg);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1482

REG_READ(intel_dp->output_reg);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1634

REG_READ(intel_dp->output_reg);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1646

if ((REG_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)

drivers/gpu/drm/gma500/cdv_intel_dp.c

1656

REG_READ(intel_dp->output_reg);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1661

REG_READ(intel_dp->output_reg);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1931

reg_value = REG_READ(DSPCLK_GATE_D);

drivers/gpu/drm/gma500/cdv_intel_dp.c

2018

pp_on = REG_READ(PP_CONTROL);

drivers/gpu/drm/gma500/cdv_intel_dp.c

2024

pwm_ctrl = REG_READ(BLC_PWM_CTL2);

drivers/gpu/drm/gma500/cdv_intel_dp.c

2028

pp_on = REG_READ(PP_ON_DELAYS);

drivers/gpu/drm/gma500/cdv_intel_dp.c

2029

pp_off = REG_READ(PP_OFF_DELAYS);

drivers/gpu/drm/gma500/cdv_intel_dp.c

2030

pp_div = REG_READ(PP_DIVISOR);

drivers/gpu/drm/gma500/cdv_intel_dp.c

389

pp = REG_READ(PP_CONTROL);

drivers/gpu/drm/gma500/cdv_intel_dp.c

393

REG_READ(PP_CONTROL);

drivers/gpu/drm/gma500/cdv_intel_dp.c

403

pp = REG_READ(PP_CONTROL);

drivers/gpu/drm/gma500/cdv_intel_dp.c

407

REG_READ(PP_CONTROL);

drivers/gpu/drm/gma500/cdv_intel_dp.c

422

pp = REG_READ(PP_CONTROL);

drivers/gpu/drm/gma500/cdv_intel_dp.c

427

REG_READ(PP_CONTROL);

drivers/gpu/drm/gma500/cdv_intel_dp.c

429

if (wait_for(((REG_READ(PP_STATUS) & idle_on_mask) == idle_on_mask), 1000)) {

drivers/gpu/drm/gma500/cdv_intel_dp.c

430

DRM_DEBUG_KMS("Error in Powering up eDP panel, status %x\n", REG_READ(PP_STATUS));

drivers/gpu/drm/gma500/cdv_intel_dp.c

447

pp = REG_READ(PP_CONTROL);

drivers/gpu/drm/gma500/cdv_intel_dp.c

460

REG_READ(PP_CONTROL);

drivers/gpu/drm/gma500/cdv_intel_dp.c

461

DRM_DEBUG_KMS("PP_STATUS %x\n", REG_READ(PP_STATUS));

drivers/gpu/drm/gma500/cdv_intel_dp.c

463

if (wait_for((REG_READ(PP_STATUS) & idle_off_mask) == 0, 1000)) {

drivers/gpu/drm/gma500/cdv_intel_dp.c

484

pp = REG_READ(PP_CONTROL);

drivers/gpu/drm/gma500/cdv_intel_dp.c

500

pp = REG_READ(PP_CONTROL);

drivers/gpu/drm/gma500/cdv_intel_dp.c

594

if (REG_READ(ch_ctl) & DP_AUX_CH_CTL_SEND_BUSY) {

drivers/gpu/drm/gma500/cdv_intel_dp.c

596

REG_READ(ch_ctl));

drivers/gpu/drm/gma500/cdv_intel_dp.c

618

status = REG_READ(ch_ctl);

drivers/gpu/drm/gma500/cdv_intel_dp.c

661

unpack_aux(REG_READ(ch_data + i),

drivers/gpu/drm/gma500/cdv_intel_hdmi.c

105

REG_READ(hdmi_priv->hdmi_reg);

drivers/gpu/drm/gma500/cdv_intel_hdmi.c

114

hdmi_priv->save_HDMIB = REG_READ(hdmi_priv->hdmi_reg);

drivers/gpu/drm/gma500/cdv_intel_hdmi.c

124

REG_READ(hdmi_priv->hdmi_reg);

drivers/gpu/drm/gma500/cdv_intel_hdmi.c

89

REG_READ(hdmi_priv->hdmi_reg);

drivers/gpu/drm/gma500/cdv_intel_hdmi.c

99

hdmib = REG_READ(hdmi_priv->hdmi_reg);

drivers/gpu/drm/gma500/cdv_intel_lvds.c

118

REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) |

drivers/gpu/drm/gma500/cdv_intel_lvds.c

121

pp_status = REG_READ(PP_STATUS);

drivers/gpu/drm/gma500/cdv_intel_lvds.c

129

REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) &

drivers/gpu/drm/gma500/cdv_intel_lvds.c

132

pp_status = REG_READ(PP_STATUS);

drivers/gpu/drm/gma500/cdv_intel_lvds.c

239

mode_dev->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL);

drivers/gpu/drm/gma500/cdv_intel_lvds.c

613

lvds = REG_READ(LVDS);

drivers/gpu/drm/gma500/cdv_intel_lvds.c

638

pwm = REG_READ(BLC_PWM_CTL2);

drivers/gpu/drm/gma500/cdv_intel_lvds.c

67

retval = ((REG_READ(BLC_PWM_CTL) &

drivers/gpu/drm/gma500/cdv_intel_lvds.c

92

REG_READ(BLC_PWM_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK;

drivers/gpu/drm/gma500/gma_display.c

125

REG_READ(map->base);

drivers/gpu/drm/gma500/gma_display.c

128

REG_READ(map->base);

drivers/gpu/drm/gma500/gma_display.c

130

REG_READ(map->surf);

drivers/gpu/drm/gma500/gma_display.c

223

temp = REG_READ(map->dpll);

drivers/gpu/drm/gma500/gma_display.c

226

REG_READ(map->dpll);

drivers/gpu/drm/gma500/gma_display.c

230

REG_READ(map->dpll);

drivers/gpu/drm/gma500/gma_display.c

234

REG_READ(map->dpll);

drivers/gpu/drm/gma500/gma_display.c

240

temp = REG_READ(map->cntr);

drivers/gpu/drm/gma500/gma_display.c

245

REG_WRITE(map->base, REG_READ(map->base));

drivers/gpu/drm/gma500/gma_display.c

251

temp = REG_READ(map->conf);

drivers/gpu/drm/gma500/gma_display.c

255

temp = REG_READ(map->status);

drivers/gpu/drm/gma500/gma_display.c

259

REG_READ(map->status);

drivers/gpu/drm/gma500/gma_display.c

289

temp = REG_READ(map->cntr);

drivers/gpu/drm/gma500/gma_display.c

294

REG_WRITE(map->base, REG_READ(map->base));

drivers/gpu/drm/gma500/gma_display.c

295

REG_READ(map->base);

drivers/gpu/drm/gma500/gma_display.c

299

temp = REG_READ(map->conf);

drivers/gpu/drm/gma500/gma_display.c

302

REG_READ(map->conf);

drivers/gpu/drm/gma500/gma_display.c

311

temp = REG_READ(map->dpll);

drivers/gpu/drm/gma500/gma_display.c

314

REG_READ(map->dpll);

drivers/gpu/drm/gma500/gma_display.c

590

crtc_state->saveDSPCNTR = REG_READ(map->cntr);

drivers/gpu/drm/gma500/gma_display.c

591

crtc_state->savePIPECONF = REG_READ(map->conf);

drivers/gpu/drm/gma500/gma_display.c

592

crtc_state->savePIPESRC = REG_READ(map->src);

drivers/gpu/drm/gma500/gma_display.c

593

crtc_state->saveFP0 = REG_READ(map->fp0);

drivers/gpu/drm/gma500/gma_display.c

594

crtc_state->saveFP1 = REG_READ(map->fp1);

drivers/gpu/drm/gma500/gma_display.c

595

crtc_state->saveDPLL = REG_READ(map->dpll);

drivers/gpu/drm/gma500/gma_display.c

596

crtc_state->saveHTOTAL = REG_READ(map->htotal);

drivers/gpu/drm/gma500/gma_display.c

597

crtc_state->saveHBLANK = REG_READ(map->hblank);

drivers/gpu/drm/gma500/gma_display.c

598

crtc_state->saveHSYNC = REG_READ(map->hsync);

drivers/gpu/drm/gma500/gma_display.c

599

crtc_state->saveVTOTAL = REG_READ(map->vtotal);

drivers/gpu/drm/gma500/gma_display.c

600

crtc_state->saveVBLANK = REG_READ(map->vblank);

drivers/gpu/drm/gma500/gma_display.c

601

crtc_state->saveVSYNC = REG_READ(map->vsync);

drivers/gpu/drm/gma500/gma_display.c

602

crtc_state->saveDSPSTRIDE = REG_READ(map->stride);

drivers/gpu/drm/gma500/gma_display.c

605

crtc_state->saveDSPSIZE = REG_READ(map->size);

drivers/gpu/drm/gma500/gma_display.c

606

crtc_state->saveDSPPOS = REG_READ(map->pos);

drivers/gpu/drm/gma500/gma_display.c

608

crtc_state->saveDSPBASE = REG_READ(map->base);

drivers/gpu/drm/gma500/gma_display.c

612

crtc_state->savePalette[i] = REG_READ(palette_reg + (i << 2));

drivers/gpu/drm/gma500/gma_display.c

636

REG_READ(map->dpll);

drivers/gpu/drm/gma500/gma_display.c

641

REG_READ(map->fp0);

drivers/gpu/drm/gma500/gma_display.c

644

REG_READ(map->fp1);

drivers/gpu/drm/gma500/gma_display.c

647

REG_READ(map->dpll);

drivers/gpu/drm/gma500/gma_display.c

761

(REG_READ(LVDS) & LVDS_PORT_EN) != 0) {

drivers/gpu/drm/gma500/gma_display.c

768

if ((REG_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==

drivers/gpu/drm/gma500/gma_display.c

93

dspcntr = REG_READ(map->cntr);

drivers/gpu/drm/gma500/intel_i2c.c

29

val = REG_READ(chan->reg);

drivers/gpu/drm/gma500/intel_i2c.c

39

val = REG_READ(chan->reg);

drivers/gpu/drm/gma500/intel_i2c.c

51

REG_READ(chan->reg) & (GPIO_DATA_PULLUP_DISABLE |

drivers/gpu/drm/gma500/intel_i2c.c

71

REG_READ(chan->reg) & (GPIO_DATA_PULLUP_DISABLE |

drivers/gpu/drm/gma500/oaktrail_crtc.c

304

REG_READ(map->base), i);

drivers/gpu/drm/gma500/oaktrail_crtc.c

339

REG_WRITE(DSPCHICKENBIT, REG_READ(DSPCHICKENBIT) | 0xc040);

drivers/gpu/drm/gma500/oaktrail_crtc.c

352

pfit_control = REG_READ(PFIT_CONTROL);

drivers/gpu/drm/gma500/oaktrail_crtc.c

489

pipeconf = REG_READ(map->conf);

drivers/gpu/drm/gma500/oaktrail_crtc.c

492

dspcntr = REG_READ(map->cntr);

drivers/gpu/drm/gma500/oaktrail_crtc.c

621

dspcntr = REG_READ(map->cntr);

drivers/gpu/drm/gma500/oaktrail_crtc.c

646

REG_READ(map->base);

drivers/gpu/drm/gma500/oaktrail_crtc.c

648

REG_READ(map->surf);

drivers/gpu/drm/gma500/oaktrail_device.c

100

REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2)));

drivers/gpu/drm/gma500/oaktrail_device.c

53

max_pwm_blc = REG_READ(BLC_PWM_CTL) >> 16;

drivers/gpu/drm/gma500/oaktrail_device.c

69

REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2)));

drivers/gpu/drm/gma500/oaktrail_hdmi.c

296

dpll = REG_READ(DPLL_CTRL);

drivers/gpu/drm/gma500/oaktrail_hdmi.c

312

dpll = REG_READ(DPLL_CTRL);

drivers/gpu/drm/gma500/oaktrail_hdmi.c

360

dspcntr = REG_READ(dspcntr_reg);

drivers/gpu/drm/gma500/oaktrail_hdmi.c

366

pipeconf = REG_READ(pipeconf_reg);

drivers/gpu/drm/gma500/oaktrail_hdmi.c

370

REG_READ(pipeconf_reg);

drivers/gpu/drm/gma500/oaktrail_hdmi.c

373

REG_READ(PCH_PIPEBCONF);

drivers/gpu/drm/gma500/oaktrail_hdmi.c

396

temp = REG_READ(DSPBCNTR);

drivers/gpu/drm/gma500/oaktrail_hdmi.c

399

REG_READ(DSPBCNTR);

drivers/gpu/drm/gma500/oaktrail_hdmi.c

401

REG_WRITE(DSPBSURF, REG_READ(DSPBSURF));

drivers/gpu/drm/gma500/oaktrail_hdmi.c

402

REG_READ(DSPBSURF);

drivers/gpu/drm/gma500/oaktrail_hdmi.c

406

temp = REG_READ(PIPEBCONF);

drivers/gpu/drm/gma500/oaktrail_hdmi.c

409

REG_READ(PIPEBCONF);

drivers/gpu/drm/gma500/oaktrail_hdmi.c

413

temp = REG_READ(PCH_PIPEBCONF);

drivers/gpu/drm/gma500/oaktrail_hdmi.c

416

REG_READ(PCH_PIPEBCONF);

drivers/gpu/drm/gma500/oaktrail_hdmi.c

423

temp = REG_READ(DPLL_CTRL);

drivers/gpu/drm/gma500/oaktrail_hdmi.c

437

temp = REG_READ(DPLL_CTRL);

drivers/gpu/drm/gma500/oaktrail_hdmi.c

440

temp = REG_READ(DPLL_CLK_ENABLE);

drivers/gpu/drm/gma500/oaktrail_hdmi.c

442

REG_READ(DPLL_CLK_ENABLE);

drivers/gpu/drm/gma500/oaktrail_hdmi.c

448

temp = REG_READ(PIPEBCONF);

drivers/gpu/drm/gma500/oaktrail_hdmi.c

451

REG_READ(PIPEBCONF);

drivers/gpu/drm/gma500/oaktrail_hdmi.c

455

temp = REG_READ(PCH_PIPEBCONF);

drivers/gpu/drm/gma500/oaktrail_hdmi.c

458

REG_READ(PCH_PIPEBCONF);

drivers/gpu/drm/gma500/oaktrail_hdmi.c

464

temp = REG_READ(DSPBCNTR);

drivers/gpu/drm/gma500/oaktrail_hdmi.c

468

REG_WRITE(DSPBSURF, REG_READ(DSPBSURF));

drivers/gpu/drm/gma500/oaktrail_hdmi.c

469

REG_READ(DSPBSURF);

drivers/gpu/drm/gma500/oaktrail_lvds.c

102

lvds_port = (REG_READ(LVDS) &

drivers/gpu/drm/gma500/oaktrail_lvds.c

166

mode_dev->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL);

drivers/gpu/drm/gma500/oaktrail_lvds.c

179

ret = ((REG_READ(BLC_PWM_CTL) &

drivers/gpu/drm/gma500/oaktrail_lvds.c

47

REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) |

drivers/gpu/drm/gma500/oaktrail_lvds.c

50

pp_status = REG_READ(PP_STATUS);

drivers/gpu/drm/gma500/oaktrail_lvds.c

58

REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) &

drivers/gpu/drm/gma500/oaktrail_lvds.c

61

pp_status = REG_READ(PP_STATUS);

drivers/gpu/drm/gma500/psb_drv.h

672

val = REG_READ(reg);

drivers/gpu/drm/gma500/psb_intel_display.c

198

pipeconf = REG_READ(map->conf);

drivers/gpu/drm/gma500/psb_intel_display.c

222

REG_READ(map->dpll);

drivers/gpu/drm/gma500/psb_intel_display.c

231

u32 lvds = REG_READ(LVDS);

drivers/gpu/drm/gma500/psb_intel_display.c

252

REG_READ(LVDS);

drivers/gpu/drm/gma500/psb_intel_display.c

257

REG_READ(map->dpll);

drivers/gpu/drm/gma500/psb_intel_display.c

264

REG_READ(map->dpll);

drivers/gpu/drm/gma500/psb_intel_display.c

289

REG_READ(map->conf);

drivers/gpu/drm/gma500/psb_intel_display.c

318

dpll = REG_READ(map->dpll);

drivers/gpu/drm/gma500/psb_intel_display.c

320

fp = REG_READ(map->fp0);

drivers/gpu/drm/gma500/psb_intel_display.c

322

fp = REG_READ(map->fp1);

drivers/gpu/drm/gma500/psb_intel_display.c

323

is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN);

drivers/gpu/drm/gma500/psb_intel_display.c

395

htot = REG_READ(map->htotal);

drivers/gpu/drm/gma500/psb_intel_display.c

396

hsync = REG_READ(map->hsync);

drivers/gpu/drm/gma500/psb_intel_display.c

397

vtot = REG_READ(map->vtotal);

drivers/gpu/drm/gma500/psb_intel_display.c

398

vsync = REG_READ(map->vsync);

drivers/gpu/drm/gma500/psb_intel_display.c

85

pfit_control = REG_READ(PFIT_CONTROL);

drivers/gpu/drm/gma500/psb_intel_lvds.c

190

blc_pwm_ctl = REG_READ(BLC_PWM_CTL);

drivers/gpu/drm/gma500/psb_intel_lvds.c

221

REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) |

drivers/gpu/drm/gma500/psb_intel_lvds.c

224

pp_status = REG_READ(PP_STATUS);

drivers/gpu/drm/gma500/psb_intel_lvds.c

232

REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) &

drivers/gpu/drm/gma500/psb_intel_lvds.c

235

pp_status = REG_READ(PP_STATUS);

drivers/gpu/drm/gma500/psb_intel_lvds.c

262

lvds_priv->savePP_ON = REG_READ(LVDSPP_ON);

drivers/gpu/drm/gma500/psb_intel_lvds.c

263

lvds_priv->savePP_OFF = REG_READ(LVDSPP_OFF);

drivers/gpu/drm/gma500/psb_intel_lvds.c

264

lvds_priv->saveLVDS = REG_READ(LVDS);

drivers/gpu/drm/gma500/psb_intel_lvds.c

265

lvds_priv->savePP_CONTROL = REG_READ(PP_CONTROL);

drivers/gpu/drm/gma500/psb_intel_lvds.c

266

lvds_priv->savePP_CYCLE = REG_READ(PP_CYCLE);

drivers/gpu/drm/gma500/psb_intel_lvds.c

268

lvds_priv->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL);

drivers/gpu/drm/gma500/psb_intel_lvds.c

269

lvds_priv->savePFIT_CONTROL = REG_READ(PFIT_CONTROL);

drivers/gpu/drm/gma500/psb_intel_lvds.c

270

lvds_priv->savePFIT_PGM_RATIOS = REG_READ(PFIT_PGM_RATIOS);

drivers/gpu/drm/gma500/psb_intel_lvds.c

320

REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) |

drivers/gpu/drm/gma500/psb_intel_lvds.c

323

pp_status = REG_READ(PP_STATUS);

drivers/gpu/drm/gma500/psb_intel_lvds.c

326

REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) &

drivers/gpu/drm/gma500/psb_intel_lvds.c

329

pp_status = REG_READ(PP_STATUS);

drivers/gpu/drm/gma500/psb_intel_lvds.c

434

mode_dev->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL);

drivers/gpu/drm/gma500/psb_intel_lvds.c

68

ret = REG_READ(BLC_PWM_CTL);

drivers/gpu/drm/gma500/psb_intel_lvds.c

761

lvds = REG_READ(LVDS);

drivers/gpu/drm/gma500/psb_intel_lvds.c

80

REG_READ(BLC_PWM_CTL), dev_priv->regs.saveBLC_PWM_CTL);

drivers/gpu/drm/gma500/psb_intel_sdvo.c

1070

sdvox = REG_READ(psb_intel_sdvo->sdvo_reg);

drivers/gpu/drm/gma500/psb_intel_sdvo.c

1124

temp = REG_READ(psb_intel_sdvo->sdvo_reg);

drivers/gpu/drm/gma500/psb_intel_sdvo.c

1137

temp = REG_READ(psb_intel_sdvo->sdvo_reg);

drivers/gpu/drm/gma500/psb_intel_sdvo.c

1744

sdvo->saveSDVO = REG_READ(sdvo->sdvo_reg);

drivers/gpu/drm/gma500/psb_irq.c

237

REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT));

drivers/gpu/drm/gma500/psb_irq.c

387

reg_val = REG_READ(pipeconf_reg);

drivers/gpu/drm/gma500/psb_irq.c

465

reg_val = REG_READ(pipeconf_reg);

drivers/gpu/drm/gma500/psb_irq.c

479

high1 = ((REG_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>

drivers/gpu/drm/gma500/psb_irq.c

481

low = ((REG_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>

drivers/gpu/drm/gma500/psb_irq.c

483

high2 = ((REG_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>

drivers/input/keyboard/goldfish_events.c

41

type = __raw_readl(edev->addr + REG_READ);

drivers/input/keyboard/goldfish_events.c

42

code = __raw_readl(edev->addr + REG_READ);

drivers/input/keyboard/goldfish_events.c

43

value = __raw_readl(edev->addr + REG_READ);

drivers/media/usb/dvb-usb-v2/ce6230.c

29

case REG_READ:

drivers/net/wireless/ath/ath9k/ani.c

389

phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);

drivers/net/wireless/ath/ath9k/ani.c

390

phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);

drivers/net/wireless/ath/ath9k/ar5008_phy.c

1142

nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR);

drivers/net/wireless/ath/ath9k/ar5008_phy.c

1145

nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR_PHY_CH1_MINCCA_PWR);

drivers/net/wireless/ath/ath9k/ar5008_phy.c

1148

nf = MS(REG_READ(ah, AR_PHY_CH2_CCA), AR_PHY_CH2_MINCCA_PWR);

drivers/net/wireless/ath/ath9k/ar5008_phy.c

1154

nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR);

drivers/net/wireless/ath/ath9k/ar5008_phy.c

1157

nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR_PHY_CH1_EXT_MINCCA_PWR);

drivers/net/wireless/ath/ath9k/ar5008_phy.c

1160

nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA), AR_PHY_CH2_EXT_MINCCA_PWR);

drivers/net/wireless/ath/ath9k/ar5008_phy.c

1185

val = REG_READ(ah, AR_PHY_SFCORR);

drivers/net/wireless/ath/ath9k/ar5008_phy.c

1190

val = REG_READ(ah, AR_PHY_SFCORR_LOW);

drivers/net/wireless/ath/ath9k/ar5008_phy.c

1195

val = REG_READ(ah, AR_PHY_SFCORR_EXT);

drivers/net/wireless/ath/ath9k/ar5008_phy.c

1247

radar_1 = REG_READ(ah, AR_PHY_RADAR_1);

drivers/net/wireless/ath/ath9k/ar5008_phy.c

233

txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);

drivers/net/wireless/ath/ath9k/ar5008_phy.c

462

tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));

drivers/net/wireless/ath/ath9k/ar5008_phy.c

583

synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;

drivers/net/wireless/ath/ath9k/ar5008_phy.c

632

REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);

drivers/net/wireless/ath/ath9k/ar5008_phy.c

655

val = REG_READ(ah, AR_PCU_MISC_MODE2) &

drivers/net/wireless/ath/ath9k/ar5008_phy.c

682

val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS);

drivers/net/wireless/ath/ath9k/ar5008_phy.c

695

enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &

drivers/net/wireless/ath/ath9k/ar5008_phy.c

896

u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;

drivers/net/wireless/ath/ath9k/ar9002_calib.c

131

REG_READ(ah, AR_PHY_CAL_MEAS_0(i));

drivers/net/wireless/ath/ath9k/ar9002_calib.c

133

REG_READ(ah, AR_PHY_CAL_MEAS_1(i));

drivers/net/wireless/ath/ath9k/ar9002_calib.c

135

(int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));

drivers/net/wireless/ath/ath9k/ar9002_calib.c

150

REG_READ(ah, AR_PHY_CAL_MEAS_0(i));

drivers/net/wireless/ath/ath9k/ar9002_calib.c

152

REG_READ(ah, AR_PHY_CAL_MEAS_1(i));

drivers/net/wireless/ath/ath9k/ar9002_calib.c

154

REG_READ(ah, AR_PHY_CAL_MEAS_2(i));

drivers/net/wireless/ath/ath9k/ar9002_calib.c

156

REG_READ(ah, AR_PHY_CAL_MEAS_3(i));

drivers/net/wireless/ath/ath9k/ar9002_calib.c

174

(int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i));

drivers/net/wireless/ath/ath9k/ar9002_calib.c

176

(int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i));

drivers/net/wireless/ath/ath9k/ar9002_calib.c

178

(int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));

drivers/net/wireless/ath/ath9k/ar9002_calib.c

180

(int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i));

drivers/net/wireless/ath/ath9k/ar9002_calib.c

308

val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));

drivers/net/wireless/ath/ath9k/ar9002_calib.c

319

REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |

drivers/net/wireless/ath/ath9k/ar9002_calib.c

363

val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));

drivers/net/wireless/ath/ath9k/ar9002_calib.c

373

REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |

drivers/net/wireless/ath/ath9k/ar9002_calib.c

382

rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4);

drivers/net/wireless/ath/ath9k/ar9002_calib.c

412

rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4);

drivers/net/wireless/ath/ath9k/ar9002_calib.c

500

regVal = REG_READ(ah, AR9285_AN_RF2G6);

drivers/net/wireless/ath/ath9k/ar9002_calib.c

506

regVal |= (MS(REG_READ(ah, AR9285_AN_RF2G9),

drivers/net/wireless/ath/ath9k/ar9002_calib.c

565

regList[i][1] = REG_READ(ah, regList[i][0]);

drivers/net/wireless/ath/ath9k/ar9002_calib.c

567

regVal = REG_READ(ah, 0x7834);

drivers/net/wireless/ath/ath9k/ar9002_calib.c

570

regVal = REG_READ(ah, 0x9808);

drivers/net/wireless/ath/ath9k/ar9002_calib.c

586

ccomp_org = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_CCOMP);

drivers/net/wireless/ath/ath9k/ar9002_calib.c

595

regVal = REG_READ(ah, 0x7834);

drivers/net/wireless/ath/ath9k/ar9002_calib.c

599

regVal = REG_READ(ah, 0x7834);

drivers/net/wireless/ath/ath9k/ar9002_calib.c

601

reg_field = MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9);

drivers/net/wireless/ath/ath9k/ar9002_calib.c

608

reg_field = MS(REG_READ(ah, AR9285_AN_RF2G9), AR9285_AN_RXTXBB1_SPARE9);

drivers/net/wireless/ath/ath9k/ar9002_calib.c

610

offs_6_1 = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_OFFS);

drivers/net/wireless/ath/ath9k/ar9002_calib.c

611

offs_0 = MS(REG_READ(ah, AR9285_AN_RF2G3), AR9285_AN_RF2G3_PDVCCOMP);

drivers/net/wireless/ath/ath9k/ar9002_calib.c

632

regVal = REG_READ(ah, 0x7834);

drivers/net/wireless/ath/ath9k/ar9002_calib.c

635

regVal = REG_READ(ah, 0x9808);

drivers/net/wireless/ath/ath9k/ar9002_calib.c

675

nfcal = !!(REG_READ(ah, AR_PHY_AGC_CONTROL(ah)) & AR_PHY_AGC_CONTROL_NF);

drivers/net/wireless/ath/ath9k/ar9002_calib.c

804

txgain_max = MS(REG_READ(ah, AR_PHY_TX_PWRCTRL7),

drivers/net/wireless/ath/ath9k/ar9002_calib.c

808

clc_gain = (REG_READ(ah, (AR_PHY_TX_GAIN_TBL1+(i<<2))) &

drivers/net/wireless/ath/ath9k/ar9002_calib.c

817

reg_clc_I0 = (REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2)))

drivers/net/wireless/ath/ath9k/ar9002_calib.c

819

reg_clc_Q0 = (REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2)))

drivers/net/wireless/ath/ath9k/ar9002_calib.c

829

reg_rf2g5_org = REG_READ(ah, AR9285_RF2G5);

drivers/net/wireless/ath/ath9k/ar9002_calib.c

866

REG_READ(ah, AR_PHY_AGC_CONTROL(ah)) |

drivers/net/wireless/ath/ath9k/ar9002_calib.c

88

if (!(REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) &

drivers/net/wireless/ath/ath9k/ar9002_hw.c

254

val = REG_READ(ah, AR_WA(ah));

drivers/net/wireless/ath/ath9k/ar9002_hw.c

337

val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;

drivers/net/wireless/ath/ath9k/ar9002_hw.c

444

val_orig = REG_READ(ah, reg);

drivers/net/wireless/ath/ath9k/ar9002_mac.c

109

s0_s = REG_READ(ah, AR_ISR_S0_S);

drivers/net/wireless/ath/ath9k/ar9002_mac.c

110

s1_s = REG_READ(ah, AR_ISR_S1_S);

drivers/net/wireless/ath/ath9k/ar9002_mac.c

112

s0_s = REG_READ(ah, AR_ISR_S0);

drivers/net/wireless/ath/ath9k/ar9002_mac.c

114

s1_s = REG_READ(ah, AR_ISR_S1);

drivers/net/wireless/ath/ath9k/ar9002_mac.c

141

s5_s = REG_READ(ah, AR_ISR_S5_S(ah));

drivers/net/wireless/ath/ath9k/ar9002_mac.c

143

s5_s = REG_READ(ah, AR_ISR_S5);

drivers/net/wireless/ath/ath9k/ar9002_mac.c

167

REG_READ(ah, AR_ISR);

drivers/net/wireless/ath/ath9k/ar9002_mac.c

205

(void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR(ah));

drivers/net/wireless/ath/ath9k/ar9002_mac.c

43

if (REG_READ(ah, AR_INTR_ASYNC_CAUSE(ah)) & AR_INTR_MAC_IRQ) {

drivers/net/wireless/ath/ath9k/ar9002_mac.c

44

if ((REG_READ(ah, AR_RTC_STATUS(ah)) & AR_RTC_STATUS_M(ah))

drivers/net/wireless/ath/ath9k/ar9002_mac.c

46

isr = REG_READ(ah, AR_ISR);

drivers/net/wireless/ath/ath9k/ar9002_mac.c

50

sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE(ah)) &

drivers/net/wireless/ath/ath9k/ar9002_mac.c

59

isr = REG_READ(ah, AR_ISR);

drivers/net/wireless/ath/ath9k/ar9002_mac.c

65

isr2 = REG_READ(ah, AR_ISR_S2);

drivers/net/wireless/ath/ath9k/ar9002_mac.c

88

isr = REG_READ(ah, AR_ISR_RAC);

drivers/net/wireless/ath/ath9k/ar9002_phy.c

225

tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));

drivers/net/wireless/ath/ath9k/ar9002_phy.c

298

MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),

drivers/net/wireless/ath/ath9k/ar9002_phy.c

336

nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR);

drivers/net/wireless/ath/ath9k/ar9002_phy.c

339

nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR9280_PHY_EXT_MINCCA_PWR);

drivers/net/wireless/ath/ath9k/ar9002_phy.c

346

nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR9280_PHY_CH1_MINCCA_PWR);

drivers/net/wireless/ath/ath9k/ar9002_phy.c

349

nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR9280_PHY_CH1_EXT_MINCCA_PWR);

drivers/net/wireless/ath/ath9k/ar9002_phy.c

383

regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);

drivers/net/wireless/ath/ath9k/ar9002_phy.c

400

regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);

drivers/net/wireless/ath/ath9k/ar9002_phy.c

455

regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);

drivers/net/wireless/ath/ath9k/ar9002_phy.c

469

regval = REG_READ(ah, AR_PHY_CCK_DETECT);

drivers/net/wireless/ath/ath9k/ar9002_phy.c

76

reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL);

drivers/net/wireless/ath/ath9k/ar9002_phy.c

98

txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);

drivers/net/wireless/ath/ath9k/ar9003_aic.c

248

(REG_READ(ah, ATH_AIC_BT_JUPITER_CTRL) |

drivers/net/wireless/ath/ath9k/ar9003_aic.c

251

aic->aic_cal_start_time = REG_READ(ah, AR_TSF_L32);

drivers/net/wireless/ath/ath9k/ar9003_aic.c

441

(REG_READ(ah, ATH_AIC_BT_JUPITER_CTRL) &

drivers/net/wireless/ath/ath9k/ar9003_aic.c

466

if ((REG_READ(ah, AR_PHY_AIC_CTRL_0_B1) &

drivers/net/wireless/ath/ath9k/ar9003_aic.c

478

if ((REG_READ(ah, AR_PHY_AIC_CTRL_0_B1) &

drivers/net/wireless/ath/ath9k/ar9003_aic.c

490

value = REG_READ(ah, AR_PHY_AIC_SRAM_DATA_B1);

drivers/net/wireless/ath/ath9k/ar9003_calib.c

1088

if (REG_READ(ah, txiqcal_status[i]) &

drivers/net/wireless/ath/ath9k/ar9003_calib.c

1104

iq_res[idx] = REG_READ(ah,

drivers/net/wireless/ath/ath9k/ar9003_calib.c

1114

iq_res[idx + 1] = 0xffff & REG_READ(ah,

drivers/net/wireless/ath/ath9k/ar9003_calib.c

1349

txclcal_done = !!(REG_READ(ah, AR_PHY_AGC_CONTROL(ah)) &

drivers/net/wireless/ath/ath9k/ar9003_calib.c

1366

REG_READ(ah, CL_TAB_ENTRY(cl_idx[i]));

drivers/net/wireless/ath/ath9k/ar9003_calib.c

1427

agc_ctrl = REG_READ(ah, AR_PHY_AGC_CONTROL(ah));

drivers/net/wireless/ath/ath9k/ar9003_calib.c

1477

if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE) {

drivers/net/wireless/ath/ath9k/ar9003_calib.c

1478

rx_delay = REG_READ(ah, AR_PHY_RX_DELAY);

drivers/net/wireless/ath/ath9k/ar9003_calib.c

1489

REG_READ(ah, AR_PHY_AGC_CONTROL(ah)) |

drivers/net/wireless/ath/ath9k/ar9003_calib.c

1500

if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE) {

drivers/net/wireless/ath/ath9k/ar9003_calib.c

1562

REG_READ(ah, AR_PHY_AGC_CONTROL(ah)) |

drivers/net/wireless/ath/ath9k/ar9003_calib.c

183

REG_READ(ah, AR_PHY_CAL_MEAS_0(i));

drivers/net/wireless/ath/ath9k/ar9003_calib.c

185

REG_READ(ah, AR_PHY_CAL_MEAS_1(i));

drivers/net/wireless/ath/ath9k/ar9003_calib.c

187

(int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));

drivers/net/wireless/ath/ath9k/ar9003_calib.c

271

REG_READ(ah, offset_array[i]));

drivers/net/wireless/ath/ath9k/ar9003_calib.c

288

REG_READ(ah, offset_array[i]));

drivers/net/wireless/ath/ath9k/ar9003_calib.c

293

REG_READ(ah, offset_array[i]));

drivers/net/wireless/ath/ath9k/ar9003_calib.c

306

REG_READ(ah, AR_PHY_RX_IQCAL_CORR_B0));

drivers/net/wireless/ath/ath9k/ar9003_calib.c

354

REG_READ(ah, AR_PHY_AGC_CONTROL(ah)) | AR_PHY_AGC_CONTROL_CAL);

drivers/net/wireless/ath/ath9k/ar9003_calib.c

384

osdac_ch0 = (REG_READ(ah, AR_PHY_65NM_CH0_BB1) >> 30) & 0x3;

drivers/net/wireless/ath/ath9k/ar9003_calib.c

385

osdac_ch1 = (REG_READ(ah, AR_PHY_65NM_CH1_BB1) >> 30) & 0x3;

drivers/net/wireless/ath/ath9k/ar9003_calib.c

386

osdac_ch2 = (REG_READ(ah, AR_PHY_65NM_CH2_BB1) >> 30) & 0x3;

drivers/net/wireless/ath/ath9k/ar9003_calib.c

391

REG_READ(ah, AR_PHY_AGC_CONTROL(ah)) | AR_PHY_AGC_CONTROL_CAL);

drivers/net/wireless/ath/ath9k/ar9003_calib.c

408

((REG_READ(ah, AR_PHY_65NM_CH0_BB3) & 0xfffffcff) | (1 << 8)));

drivers/net/wireless/ath/ath9k/ar9003_calib.c

410

((REG_READ(ah, AR_PHY_65NM_CH1_BB3) & 0xfffffcff) | (1 << 8)));

drivers/net/wireless/ath/ath9k/ar9003_calib.c

412

((REG_READ(ah, AR_PHY_65NM_CH2_BB3) & 0xfffffcff) | (1 << 8)));

drivers/net/wireless/ath/ath9k/ar9003_calib.c

414

temp = REG_READ(ah, AR_PHY_65NM_CH0_BB3);

drivers/net/wireless/ath/ath9k/ar9003_calib.c

418

temp = REG_READ(ah, AR_PHY_65NM_CH1_BB3);

drivers/net/wireless/ath/ath9k/ar9003_calib.c

422

temp = REG_READ(ah, AR_PHY_65NM_CH2_BB3);

drivers/net/wireless/ath/ath9k/ar9003_calib.c

430

((REG_READ(ah, AR_PHY_65NM_CH0_BB3) & 0xfffffcff) | (2 << 8)));

drivers/net/wireless/ath/ath9k/ar9003_calib.c

432

((REG_READ(ah, AR_PHY_65NM_CH1_BB3) & 0xfffffcff) | (2 << 8)));

drivers/net/wireless/ath/ath9k/ar9003_calib.c

434

((REG_READ(ah, AR_PHY_65NM_CH2_BB3) & 0xfffffcff) | (2 << 8)));

drivers/net/wireless/ath/ath9k/ar9003_calib.c

436

temp = REG_READ(ah, AR_PHY_65NM_CH0_BB3);

drivers/net/wireless/ath/ath9k/ar9003_calib.c

440

temp = REG_READ(ah, AR_PHY_65NM_CH1_BB3);

drivers/net/wireless/ath/ath9k/ar9003_calib.c

444

temp = REG_READ(ah, AR_PHY_65NM_CH2_BB3);

drivers/net/wireless/ath/ath9k/ar9003_calib.c

452

((REG_READ(ah, AR_PHY_65NM_CH0_BB3) & 0xfffffcff) | (3 << 8)));

drivers/net/wireless/ath/ath9k/ar9003_calib.c

454

((REG_READ(ah, AR_PHY_65NM_CH1_BB3) & 0xfffffcff) | (3 << 8)));

drivers/net/wireless/ath/ath9k/ar9003_calib.c

456

((REG_READ(ah, AR_PHY_65NM_CH2_BB3) & 0xfffffcff) | (3 << 8)));

drivers/net/wireless/ath/ath9k/ar9003_calib.c

458

temp = REG_READ(ah, AR_PHY_65NM_CH0_BB3);

drivers/net/wireless/ath/ath9k/ar9003_calib.c

462

temp = REG_READ(ah, AR_PHY_65NM_CH1_BB3);

drivers/net/wireless/ath/ath9k/ar9003_calib.c

466

temp = REG_READ(ah, AR_PHY_65NM_CH2_BB3);

drivers/net/wireless/ath/ath9k/ar9003_calib.c

481

val = REG_READ(ah, AR_PHY_65NM_CH0_BB1) & 0x3fffffff;

drivers/net/wireless/ath/ath9k/ar9003_calib.c

502

val = REG_READ(ah, AR_PHY_65NM_CH1_BB1) & 0x3fffffff;

drivers/net/wireless/ath/ath9k/ar9003_calib.c

523

val = REG_READ(ah, AR_PHY_65NM_CH2_BB1) & 0x3fffffff;

drivers/net/wireless/ath/ath9k/ar9003_calib.c

83

if (REG_READ(ah, AR_PHY_TIMING4) & AR_PHY_TIMING4_DO_CAL)

drivers/net/wireless/ath/ath9k/ar9003_eeprom.c

3087

REG_READ(ah, AR9300_OTP_BASE(ah) + (4 * addr));

drivers/net/wireless/ath/ath9k/ar9003_eeprom.c

3093

*data = REG_READ(ah, AR9300_OTP_READ_DATA(ah));

drivers/net/wireless/ath/ath9k/ar9003_eeprom.c

3730

regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);

drivers/net/wireless/ath/ath9k/ar9003_eeprom.c

3766

regval = REG_READ(ah, AR_PHY_CCK_DETECT);

drivers/net/wireless/ath/ath9k/ar9003_eeprom.c

3777

regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);

drivers/net/wireless/ath/ath9k/ar9003_eeprom.c

3807

reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS1);

drivers/net/wireless/ath/ath9k/ar9003_eeprom.c

3817

reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS2);

drivers/net/wireless/ath/ath9k/ar9003_eeprom.c

3830

reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS4);

drivers/net/wireless/ath/ath9k/ar9003_eeprom.c

3943

while (pmu_set != REG_READ(ah, pmu_reg)) {

drivers/net/wireless/ath/ath9k/ar9003_eeprom.c

3963

reg_pmu_set = REG_READ(ah, AR_PHY_PMU2(ah)) & ~AR_PHY_PMU2_PGM;

drivers/net/wireless/ath/ath9k/ar9003_eeprom.c

3991

reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2(ah)) & ~0xFFC00000)

drivers/net/wireless/ath/ath9k/ar9003_eeprom.c

3997

reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2(ah)) & ~0x00200000)

drivers/net/wireless/ath/ath9k/ar9003_eeprom.c

4013

REG_READ(ah, AR_RTC_REG_CONTROL1) &

drivers/net/wireless/ath/ath9k/ar9003_eeprom.c

4018

REG_READ(ah,

drivers/net/wireless/ath/ath9k/ar9003_eeprom.c

4040

reg_val = REG_READ(ah, AR_RTC_SLEEP_CLK(ah)) |

drivers/net/wireless/ath/ath9k/ar9003_eeprom.c

5546

val = REG_READ(ah, AR_PHY_POWER_TX_SUB);

drivers/net/wireless/ath/ath9k/ar9003_hw.c

1114

dma_dbg_chain = REG_READ(ah, dbg_reg);

drivers/net/wireless/ath/ath9k/ar9003_hw.c

1115

dma_dbg_complete = REG_READ(ah, AR_DMADBG_6);

drivers/net/wireless/ath/ath9k/ar9003_hw.c

1139

dma_dbg_4 = REG_READ(ah, AR_DMADBG_4);

drivers/net/wireless/ath/ath9k/ar9003_hw.c

1140

dma_dbg_5 = REG_READ(ah, AR_DMADBG_5);

drivers/net/wireless/ath/ath9k/ar9003_hw.c

1141

dma_dbg_6 = REG_READ(ah, AR_DMADBG_6);

drivers/net/wireless/ath/ath9k/ar9003_mac.c

196

async_cause = REG_READ(ah, AR_INTR_ASYNC_CAUSE(ah));

drivers/net/wireless/ath/ath9k/ar9003_mac.c

199

if ((REG_READ(ah, AR_RTC_STATUS(ah)) & AR_RTC_STATUS_M(ah))

drivers/net/wireless/ath/ath9k/ar9003_mac.c

201

isr = REG_READ(ah, AR_ISR);

drivers/net/wireless/ath/ath9k/ar9003_mac.c

205

sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE(ah)) & AR_INTR_SYNC_DEFAULT;

drivers/net/wireless/ath/ath9k/ar9003_mac.c

215

isr2 = REG_READ(ah, AR_ISR_S2);

drivers/net/wireless/ath/ath9k/ar9003_mac.c

241

isr = REG_READ(ah, AR_ISR_RAC);

drivers/net/wireless/ath/ath9k/ar9003_mac.c

269

s0 = REG_READ(ah, AR_ISR_S0);

drivers/net/wireless/ath/ath9k/ar9003_mac.c

271

s1 = REG_READ(ah, AR_ISR_S1);

drivers/net/wireless/ath/ath9k/ar9003_mac.c

283

s5 = REG_READ(ah, AR_ISR_S5_S(ah));

drivers/net/wireless/ath/ath9k/ar9003_mac.c

285

s5 = REG_READ(ah, AR_ISR_S5);

drivers/net/wireless/ath/ath9k/ar9003_mac.c

308

(void) REG_READ(ah, AR_ISR);

drivers/net/wireless/ath/ath9k/ar9003_mac.c

349

(void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR(ah));

drivers/net/wireless/ath/ath9k/ar9003_mci.c

1176

saved_mci_int_en = REG_READ(ah, AR_MCI_INTERRUPT_EN);

drivers/net/wireless/ath/ath9k/ar9003_mci.c

1177

regval = REG_READ(ah, AR_BTCOEX_CTRL);

drivers/net/wireless/ath/ath9k/ar9003_mci.c

1298

value = REG_READ(ah, AR_BTCOEX_CTRL);

drivers/net/wireless/ath/ath9k/ar9003_mci.c

1306

value = MS(REG_READ(ah, AR_MCI_GPM_1), AR_MCI_GPM_WRITE_PTR);

drivers/net/wireless/ath/ath9k/ar9003_mci.c

1314

value = MS(REG_READ(ah, AR_MCI_RX_STATUS),

drivers/net/wireless/ath/ath9k/ar9003_mci.c

1320

value = MS(REG_READ(ah, AR_MCI_RX_STATUS),

drivers/net/wireless/ath/ath9k/ar9003_mci.c

1340

if ((REG_READ(ah, AR_GLB_GPIO_CONTROL) &

drivers/net/wireless/ath/ath9k/ar9003_mci.c

1429

btcoex_ctrl2 = REG_READ(ah, AR_BTCOEX_CTRL2);

drivers/net/wireless/ath/ath9k/ar9003_mci.c

1437

diag_sw = REG_READ(ah, AR_DIAG_SW);

drivers/net/wireless/ath/ath9k/ar9003_mci.c

1443

lna_ctrl = REG_READ(ah, AR_OBS_BUS_CTRL) & 0x3;

drivers/net/wireless/ath/ath9k/ar9003_mci.c

1444

bt_sleep = MS(REG_READ(ah, AR_MCI_RX_STATUS), AR_MCI_RX_REMOTE_SLEEP);

drivers/net/wireless/ath/ath9k/ar9003_mci.c

1465

offset = MS(REG_READ(ah, AR_MCI_GPM_1), AR_MCI_GPM_WRITE_PTR);

drivers/net/wireless/ath/ath9k/ar9003_mci.c

1492

gpm_ptr = MS(REG_READ(ah, AR_MCI_GPM_1), AR_MCI_GPM_WRITE_PTR);

drivers/net/wireless/ath/ath9k/ar9003_mci.c

232

saved_mci_int_en = REG_READ(ah, AR_MCI_INTERRUPT_EN);

drivers/net/wireless/ath/ath9k/ar9003_mci.c

236

REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW));

drivers/net/wireless/ath/ath9k/ar9003_mci.c

238

REG_READ(ah, AR_MCI_INTERRUPT_RAW));

drivers/net/wireless/ath/ath9k/ar9003_mci.c

351

intr = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW);

drivers/net/wireless/ath/ath9k/ar9003_mci.c

375

rx_msg_intr = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW);

drivers/net/wireless/ath/ath9k/ar9003_mci.c

376

raw_intr = REG_READ(ah, AR_MCI_INTERRUPT_RAW);

drivers/net/wireless/ath/ath9k/ar9003_mci.c

387

mci->cont_status = REG_READ(ah, AR_MCI_CONT_STATUS);

drivers/net/wireless/ath/ath9k/ar9003_mci.c

39

if (!(REG_READ(ah, address) & bit_position)) {

drivers/net/wireless/ath/ath9k/ar9003_mci.c

71

REG_READ(ah, AR_MCI_INTERRUPT_RAW),

drivers/net/wireless/ath/ath9k/ar9003_mci.c

72

REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW));

drivers/net/wireless/ath/ath9k/ar9003_mci.c

928

if (REG_READ(ah, AR_BTCOEX_CTRL) == 0xdeadbeef) {

drivers/net/wireless/ath/ath9k/ar9003_mci.c

986

regval = REG_READ(ah, AR_MCI_COMMAND2);

drivers/net/wireless/ath/ath9k/ar9003_paprd.c

299

entry[i] = REG_READ(ah, reg);

drivers/net/wireless/ath/ath9k/ar9003_paprd.c

940

data_L[i] = REG_READ(ah, reg + (i << 2));

drivers/net/wireless/ath/ath9k/ar9003_paprd.c

946

data_U[i] = REG_READ(ah, reg + (i << 2));

drivers/net/wireless/ath/ath9k/ar9003_phy.c

1055

u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;

drivers/net/wireless/ath/ath9k/ar9003_phy.c

1349

nf = MS(REG_READ(ah, ah->nf_regs[i]),

drivers/net/wireless/ath/ath9k/ar9003_phy.c

1356

nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]),

drivers/net/wireless/ath/ath9k/ar9003_phy.c

1406

val = REG_READ(ah, AR_PHY_SFCORR);

drivers/net/wireless/ath/ath9k/ar9003_phy.c

1411

val = REG_READ(ah, AR_PHY_SFCORR_LOW);

drivers/net/wireless/ath/ath9k/ar9003_phy.c

1416

val = REG_READ(ah, AR_PHY_SFCORR_EXT);

drivers/net/wireless/ath/ath9k/ar9003_phy.c

1459

radar_1 = REG_READ(ah, AR_PHY_RADAR_1);

drivers/net/wireless/ath/ath9k/ar9003_phy.c

1500

regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);

drivers/net/wireless/ath/ath9k/ar9003_phy.c

1532

regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);

drivers/net/wireless/ath/ath9k/ar9003_phy.c

1580

regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);

drivers/net/wireless/ath/ath9k/ar9003_phy.c

1589

regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);

drivers/net/wireless/ath/ath9k/ar9003_phy.c

1600

regval = REG_READ(ah, AR_PHY_CCK_DETECT);

drivers/net/wireless/ath/ath9k/ar9003_phy.c

1609

regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);

drivers/net/wireless/ath/ath9k/ar9003_phy.c

1648

regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);

drivers/net/wireless/ath/ath9k/ar9003_phy.c

2004

val = REG_READ(ah, AR_PHY_RADAR_0);

drivers/net/wireless/ath/ath9k/ar9003_phy.c

2009

val = REG_READ(ah, AR_PHY_RADAR_0);

drivers/net/wireless/ath/ath9k/ar9003_phy.c

2044

REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) &

drivers/net/wireless/ath/ath9k/ar9003_phy.c

2050

REG_READ(ah, AR_PHY_WATCHDOG_CTL_1) &

drivers/net/wireless/ath/ath9k/ar9003_phy.c

2059

val = REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & AR_PHY_WATCHDOG_CNTL2_MASK;

drivers/net/wireless/ath/ath9k/ar9003_phy.c

2100

ah->bb_watchdog_last_status = REG_READ(ah, AR_PHY_WATCHDOG_STATUS);

drivers/net/wireless/ath/ath9k/ar9003_phy.c

2134

REG_READ(ah, AR_PHY_WATCHDOG_CTL_1),

drivers/net/wireless/ath/ath9k/ar9003_phy.c

2135

REG_READ(ah, AR_PHY_WATCHDOG_CTL_2));

drivers/net/wireless/ath/ath9k/ar9003_phy.c

2137

REG_READ(ah, AR_PHY_GEN_CTRL));

drivers/net/wireless/ath/ath9k/ar9003_phy.c

2163

val = REG_READ(ah, AR_PHY_RESTART);

drivers/net/wireless/ath/ath9k/ar9003_phy.c

617

(REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO);

drivers/net/wireless/ath/ath9k/ar9003_phy.c

635

phymode |= REG_READ(ah, AR_PHY_GEN_CTRL);

drivers/net/wireless/ath/ath9k/ar9003_phy.c

660

synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;

drivers/net/wireless/ath/ath9k/ar9003_phy.c

703

val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE);

drivers/net/wireless/ath/ath9k/ar9003_phy.c

721

if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE)

drivers/net/wireless/ath/ath9k/ar9003_rtt.c

162

val = MS(REG_READ(ah, AR_PHY_RTT_TABLE_SW_INTF_1_B(chain)),

drivers/net/wireless/ath/ath9k/ar9003_wow.c

192

rval = REG_READ(ah, AR_WOW_PATTERN);

drivers/net/wireless/ath/ath9k/ar9003_wow.c

213

rval = REG_READ(ah, AR_MAC_PCU_WOW4);

drivers/net/wireless/ath/ath9k/ar9003_wow.c

236

AR_WOW_CLEAR_EVENTS(REG_READ(ah, AR_WOW_PATTERN)));

drivers/net/wireless/ath/ath9k/ar9003_wow.c

238

AR_WOW_CLEAR_EVENTS2(REG_READ(ah, AR_MAC_PCU_WOW4)));

drivers/net/wireless/ath/ath9k/ar9003_wow.c

256

u32 dc = REG_READ(ah, AR_DIRECT_CONNECT);

drivers/net/wireless/ath/ath9k/ar9003_wow.c

281

wa_reg = REG_READ(ah, AR_WA(ah));

drivers/net/wireless/ath/ath9k/ar9003_wow.c

364

keep_alive = REG_READ(ah, AR_WOW_KEEP_ALIVE);

drivers/net/wireless/ath/ath9k/ar9003_wow.c

395

magic_pattern = REG_READ(ah, AR_WOW_PATTERN);

drivers/net/wireless/ath/ath9k/ar9003_wow.c

417

host_pm_ctrl = REG_READ(ah, AR_PCIE_PM_CTRL(ah));

drivers/net/wireless/ath/ath9k/ar9003_wow.c

48

REG_READ(ah, AR_CR), REG_READ(ah, AR_DIAG_SW));

drivers/net/wireless/ath/ath9k/ar9003_wow.c

53

if (!REG_READ(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL))

drivers/net/wireless/ath/ath9k/ar9003_wow.c

56

if (!(REG_READ(ah, AR_NDP2_TIMER_MODE) &

drivers/net/wireless/ath/ath9k/btcoex.c

339

val = REG_READ(ah, 0x50040);

drivers/net/wireless/ath/ath9k/calib.c

247

u32 bb_agc_ctl = REG_READ(ah, AR_PHY_AGC_CONTROL(ah));

drivers/net/wireless/ath/ath9k/calib.c

305

if ((REG_READ(ah, AR_PHY_AGC_CONTROL(ah)) &

drivers/net/wireless/ath/ath9k/calib.c

338

REG_READ(ah, AR_PHY_AGC_CONTROL(ah)));

drivers/net/wireless/ath/ath9k/calib.c

406

if (REG_READ(ah, AR_PHY_AGC_CONTROL(ah)) & AR_PHY_AGC_CONTROL_NF) {

drivers/net/wireless/ath/ath9k/calib.c

474

else if (!(REG_READ(ah, AR_PHY_AGC_CONTROL(ah)) & AR_PHY_AGC_CONTROL_NF))

drivers/net/wireless/ath/ath9k/channel.c

577

sc->sched.next_tbtt = REG_READ(ah, AR_NEXT_TBTT_TIMER);

drivers/net/wireless/ath/ath9k/debug.c

967

"0x%06x 0x%08x\n", i << 2, REG_READ(sc->sc_ah, i << 2));

drivers/net/wireless/ath/ath9k/eeprom_4k.c

304

pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),

drivers/net/wireless/ath/ath9k/eeprom_4k.c

782

regVal = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);

drivers/net/wireless/ath/ath9k/eeprom_4k.c

798

regVal = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);

drivers/net/wireless/ath/ath9k/eeprom_4k.c

799

regVal = REG_READ(ah, AR_PHY_CCK_DETECT);

drivers/net/wireless/ath/ath9k/eeprom_4k.c

805

regVal = REG_READ(ah, AR_PHY_CCK_DETECT);

drivers/net/wireless/ath/ath9k/eeprom_4k.c

812

regVal = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);

drivers/net/wireless/ath/ath9k/eeprom_9287.c

320

tmpVal = REG_READ(ah, 0xa270);

drivers/net/wireless/ath/ath9k/eeprom_9287.c

327

tmpVal = REG_READ(ah, 0xb270);

drivers/net/wireless/ath/ath9k/eeprom_9287.c

335

tmpVal = REG_READ(ah, 0xa398);

drivers/net/wireless/ath/ath9k/eeprom_9287.c

345

tmpVal = REG_READ(ah, 0xb398);

drivers/net/wireless/ath/ath9k/eeprom_9287.c

374

pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),

drivers/net/wireless/ath/ath9k/eeprom_9287.c

869

(REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset)

drivers/net/wireless/ath/ath9k/eeprom_9287.c

918

regval = REG_READ(ah, AR9287_AN_RF2G3_CH0);

drivers/net/wireless/ath/ath9k/eeprom_9287.c

934

regval = REG_READ(ah, AR9287_AN_RF2G3_CH1);

drivers/net/wireless/ath/ath9k/eeprom_def.c

496

(REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) &

drivers/net/wireless/ath/ath9k/eeprom_def.c

791

pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),

drivers/net/wireless/ath/ath9k/htc_drv_init.c

498

val = REG_READ(ah, reg_offset);

drivers/net/wireless/ath/ath9k/htc_drv_init.c

523

(void)REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));

drivers/net/wireless/ath/ath9k/htc_drv_init.c

532

*data = MS(REG_READ(ah, AR_EEPROM_STATUS_DATA(ah)),

drivers/net/wireless/ath/ath9k/hw.c

1105

eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/

drivers/net/wireless/ath/ath9k/hw.c

1107

reg = REG_READ(ah, AR_USEC);

drivers/net/wireless/ath/ath9k/hw.c

1359

(void)REG_READ(ah, AR_RTC_DERIVED_CLK(ah));

drivers/net/wireless/ath/ath9k/hw.c

1376

tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE(ah));

drivers/net/wireless/ath/ath9k/hw.c

1524

} else if (ah->chip_fullsleep || REG_READ(ah, AR_Q_TXE) ||

drivers/net/wireless/ath/ath9k/hw.c

1525

(REG_READ(ah, AR_CR) & AR_CR_RXE(ah)))

drivers/net/wireless/ath/ath9k/hw.c

1633

val = REG_READ(ah, AR_NAV);

drivers/net/wireless/ath/ath9k/hw.c

1647

if (REG_READ(ah, AR_CFG) == 0xdeadbeef)

drivers/net/wireless/ath/ath9k/hw.c

1656

last_val = REG_READ(ah, AR_OBS_BUS_1);

drivers/net/wireless/ath/ath9k/hw.c

1658

reg = REG_READ(ah, AR_OBS_BUS_1);

drivers/net/wireless/ath/ath9k/hw.c

1755

mask = REG_READ(ah, AR_CFG);

drivers/net/wireless/ath/ath9k/hw.c

1763

REG_READ(ah, AR_CFG));

drivers/net/wireless/ath/ath9k/hw.c

1905

saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);

drivers/net/wireless/ath/ath9k/hw.c

1909

macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;

drivers/net/wireless/ath/ath9k/hw.c

1915

saveLedState = REG_READ(ah, AR_CFG_LED) &

drivers/net/wireless/ath/ath9k/hw.c

2180

if ((REG_READ(ah, AR_RTC_STATUS(ah)) &

drivers/net/wireless/ath/ath9k/hw.c

2200

val = REG_READ(ah, AR_RTC_STATUS(ah)) & AR_RTC_STATUS_M(ah);

drivers/net/wireless/ath/ath9k/hw.c

2620

ah->ent_mode = REG_READ(ah, AR_ENT_OTP);

drivers/net/wireless/ath/ath9k/hw.c

270

val = REG_READ(ah, AR_SREV(ah));

drivers/net/wireless/ath/ath9k/hw.c

2709

tmp = REG_READ(ah, addr);

drivers/net/wireless/ath/ath9k/hw.c

2806

(MS(REG_READ(ah, AR_GPIO_IN_OUT(ah)), x##_GPIO_IN_VAL) & BIT(y))

drivers/net/wireless/ath/ath9k/hw.c

2820

val = REG_READ(ah, AR7010_GPIO_IN) & BIT(gpio);

drivers/net/wireless/ath/ath9k/hw.c

2822

val = REG_READ(ah, AR_GPIO_IN(ah)) & BIT(gpio);

drivers/net/wireless/ath/ath9k/hw.c

2869

u32 bits = REG_READ(ah, AR_RX_FILTER);

drivers/net/wireless/ath/ath9k/hw.c

2870

u32 phybits = REG_READ(ah, AR_PHY_ERR);

drivers/net/wireless/ath/ath9k/hw.c

288

srev = REG_READ(ah, AR_SREV(ah));

drivers/net/wireless/ath/ath9k/hw.c

3013

tsf_upper1 = REG_READ(ah, AR_TSF_U32);

drivers/net/wireless/ath/ath9k/hw.c

3015

tsf_lower = REG_READ(ah, AR_TSF_L32);

drivers/net/wireless/ath/ath9k/hw.c

3016

tsf_upper2 = REG_READ(ah, AR_TSF_U32);

drivers/net/wireless/ath/ath9k/hw.c

3100

return REG_READ(ah, AR_TSF_L32);

drivers/net/wireless/ath/ath9k/hw.c

365

regHold[i] = REG_READ(ah, addr);

drivers/net/wireless/ath/ath9k/hw.c

369

rdData = REG_READ(ah, addr);

drivers/net/wireless/ath/ath9k/hw.c

380

rdData = REG_READ(ah, addr);

drivers/net/wireless/ath/ath9k/hw.c

610

ah->WARegVal = REG_READ(ah, AR_WA(ah));

drivers/net/wireless/ath/ath9k/hw.c

641

ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);

drivers/net/wireless/ath/ath9k/hw.c

745

while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) {

drivers/net/wireless/ath/ath9k/hw.c

757

return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;

drivers/net/wireless/ath/ath9k/hw.c

84

if ((REG_READ(ah, reg) & mask) == val)

drivers/net/wireless/ath/ath9k/hw.c

867

regval = REG_READ(ah, AR_PHY_PLL_MODE);

drivers/net/wireless/ath/ath9k/hw.c

879

regval = REG_READ(ah, AR_PHY_PLL_MODE);

drivers/net/wireless/ath/ath9k/hw.c

905

REG_READ(ah, AR_PHY_PLL_MODE) & 0xffbfffff);

drivers/net/wireless/ath/ath9k/hw.c

908

REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);

drivers/net/wireless/ath/ath9k/hw.c

92

timeout, reg, REG_READ(ah, reg), mask, val);

drivers/net/wireless/ath/ath9k/hw.c

981

ah->msi_reg = REG_READ(ah, AR_PCIE_MSI(ah));

drivers/net/wireless/ath/ath9k/hw.c

987

REG_READ(ah, AR_INTCFG), msi_cfg);

drivers/net/wireless/ath/ath9k/hw.h

126

(((REG_READ(_a, _r) & _f) >> _f##_S))

drivers/net/wireless/ath/ath9k/mac.c

114

txcfg = REG_READ(ah, AR_TXCFG);

drivers/net/wireless/ath/ath9k/mac.c

48

return REG_READ(ah, AR_QTXDP(q));

drivers/net/wireless/ath/ath9k/mac.c

653

reg = REG_READ(ah, AR_OBS_BUS_1);

drivers/net/wireless/ath/ath9k/mac.c

69

npend = REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT;

drivers/net/wireless/ath/ath9k/mac.c

710

if ((REG_READ(ah, AR_CR) & AR_CR_RXE(ah)) == 0)

drivers/net/wireless/ath/ath9k/mac.c

714

mac_status = REG_READ(ah, AR_DMADBG_7) & 0x7f0;

drivers/net/wireless/ath/ath9k/mac.c

72

if (REG_READ(ah, AR_Q_TXE) & (1 << q))

drivers/net/wireless/ath/ath9k/mac.c

730

REG_READ(ah, AR_CR),

drivers/net/wireless/ath/ath9k/mac.c

731

REG_READ(ah, AR_DIAG_SW),

drivers/net/wireless/ath/ath9k/mac.c

732

REG_READ(ah, AR_DMADBG_7));

drivers/net/wireless/ath/ath9k/mac.c

765

host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE(ah));

drivers/net/wireless/ath/ath9k/mac.c

772

host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE(ah));

drivers/net/wireless/ath/ath9k/mac.c

787

(void) REG_READ(ah, AR_IER);

drivers/net/wireless/ath/ath9k/mac.c

790

(void) REG_READ(ah, AR_INTR_ASYNC_ENABLE(ah));

drivers/net/wireless/ath/ath9k/mac.c

793

(void) REG_READ(ah, AR_INTR_SYNC_ENABLE(ah));

drivers/net/wireless/ath/ath9k/mac.c

834

REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));

drivers/net/wireless/ath/ath9k/mac.c

848

REG_READ(ah, AR_INTR_PRIO_ASYNC_ENABLE(ah)),

drivers/net/wireless/ath/ath9k/mac.c

849

REG_READ(ah, AR_INTR_PRIO_ASYNC_MASK(ah)));

drivers/net/wireless/ath/ath9k/mac.c

852

ah->msi_reg = REG_READ(ah, AR_PCIE_MSI(ah));

drivers/net/wireless/ath/ath9k/mac.c

863

_msi_reg = REG_READ(ah, AR_PCIE_MSI(ah));

drivers/net/wireless/ath/ath9k/mac.c

922

REG_READ(ah, AR_INTR_PRIO_ASYNC_ENABLE(ah));

drivers/net/wireless/ath/ath9k/reg.h

941

((REG_READ(_ah, AR_AN_SYNTH9) & 0x7) == 0x1))

drivers/net/wireless/ath/ath9k/rng.c

37

v1 = REG_READ(ah, AR_PHY_TST_ADC) & 0xffff;

drivers/net/wireless/ath/ath9k/rng.c

38

v2 = REG_READ(ah, AR_PHY_TST_ADC) & 0xffff;

drivers/net/wireless/ath/hw.c

124

id1 = REG_READ(ah, AR_STA_ID1) & ~AR_STA_ID1_SADH_MASK;

drivers/net/wireless/ath/hw.c

151

cycles = REG_READ(ah, AR_CCCNT);

drivers/net/wireless/ath/hw.c

152

busy = REG_READ(ah, AR_RCCNT);

drivers/net/wireless/ath/hw.c

153

rx = REG_READ(ah, AR_RFCNT);

drivers/net/wireless/ath/hw.c

154

tx = REG_READ(ah, AR_TFCNT);

drivers/net/wireless/ath/key.c

53

keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));

drivers/net/wireless/mediatek/mt76/mt7615/mcu.c

171

} else if (cmd == MCU_CE_QUERY(REG_READ)) {

drivers/net/wireless/mediatek/mt76/mt76_connac_mcu.c

2666

return mt76_mcu_send_msg(dev, MCU_CE_QUERY(REG_READ), &req,

drivers/net/wireless/mediatek/mt76/mt7921/mcu.c

58

} else if (cmd == MCU_CE_QUERY(REG_READ)) {

drivers/net/wireless/st/cw1200/fwio.c

136

REG_READ(ST90TDS_CONFIG_REG_ID, val32);