REG_PLL_G2_SSC_SYN_CTRL
.en = CV1800_CLK_BIT(REG_PLL_G2_SSC_SYN_CTRL, 2),
.clk_half = CV1800_CLK_BIT(REG_PLL_G2_SSC_SYN_CTRL, 0),
.en = CV1800_CLK_BIT(REG_PLL_G2_SSC_SYN_CTRL, 3),
.clk_half = CV1800_CLK_BIT(REG_PLL_G2_SSC_SYN_CTRL, 0),
.en = CV1800_CLK_BIT(REG_PLL_G2_SSC_SYN_CTRL, 4),
.clk_half = CV1800_CLK_BIT(REG_PLL_G2_SSC_SYN_CTRL, 0),
.en = CV1800_CLK_BIT(REG_PLL_G2_SSC_SYN_CTRL, 5),
.clk_half = CV1800_CLK_BIT(REG_PLL_G2_SSC_SYN_CTRL, 0),