arch/riscv/include/asm/insn.h

404

((ulong *)((ulong)(regs) + REG_OFFSET(insn, pos)))

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

42

#define DMUB_SR(reg) REG_OFFSET(reg),

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.c

41

#define DMUB_SR(reg) REG_OFFSET(reg),

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c

42

#define DMUB_SR(reg) REG_OFFSET(reg),

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn301.c

41

#define DMUB_SR(reg) REG_OFFSET(reg),

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn302.c

41

#define DMUB_SR(reg) REG_OFFSET(reg),

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn303.c

42

#define DMUB_SR(reg) REG_OFFSET(reg),

drivers/pci/controller/pcie-brcmstb.c

1326

const unsigned int REG_OFFSET = PCIE_RGR1_SW_INIT_1(pcie) - 8;

drivers/pci/controller/pcie-brcmstb.c

1334

writel(216 * timeout_us, pcie->base + REG_OFFSET);

drivers/pinctrl/spear/pinctrl-plgpio.c

106

u32 reg_off = REG_OFFSET(0, reg, pin);

drivers/pinctrl/spear/pinctrl-plgpio.c

350

reg_off = REG_OFFSET(0, plgpio->regs.eit, offset);

drivers/pinctrl/spear/pinctrl-plgpio.c

85

u32 reg_off = REG_OFFSET(0, reg, pin);

drivers/pinctrl/spear/pinctrl-plgpio.c

96

u32 reg_off = REG_OFFSET(0, reg, pin);

sound/soc/renesas/siu_dai.c

763

info->reg = devm_ioremap(&pdev->dev, res->start + REG_OFFSET,

sound/soc/renesas/siu_dai.c

764

resource_size(res) - REG_OFFSET);

tools/testing/selftests/kvm/arm64/vgic_init.c

44

REG_OFFSET(vcpu, offset), &ignored_val);

tools/testing/selftests/kvm/arm64/vgic_init.c

55

REG_OFFSET(vcpu, offset), &val);