REG_MISC_AB
value = readl(meson->base + REG_MISC_AB);
writel(value, meson->base + REG_MISC_AB);
value = readl(meson->base + REG_MISC_AB);
writel(value, meson->base + REG_MISC_AB);
value = readl(meson->base + REG_MISC_AB);
channel->mux.reg = meson->base + REG_MISC_AB;
channel->div.reg = meson->base + REG_MISC_AB;
channel->gate.reg = meson->base + REG_MISC_AB;