drivers/gpu/drm/i915/display/intel_cx0_phy.c

3176

disables = REG_GENMASK8(3, 0) >> lane_count;

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3178

disables = REG_GENMASK8(3, 0) << lane_count;

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3181

disables &= ~REG_GENMASK8(1, 0);

drivers/gpu/drm/i915/display/intel_cx0_phy.c

3182

disables |= REG_FIELD_PREP8(REG_GENMASK8(1, 0), 0x1);

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

239

#define C10_PLL0_ANA_FREQ_VCO_MASK REG_GENMASK8(7, 6)

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

240

#define C10_PLL1_DIV_MULTIPLIER_MASK REG_GENMASK8(7, 0)

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

241

#define C10_PLL2_MULTIPLIERL_MASK REG_GENMASK8(7, 0)

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

242

#define C10_PLL3_MULTIPLIERH_MASK REG_GENMASK8(3, 0)

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

244

#define C10_PLL9_FRACN_DENL_MASK REG_GENMASK8(7, 0)

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

245

#define C10_PLL10_FRACN_DENH_MASK REG_GENMASK8(7, 0)

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

246

#define C10_PLL11_FRACN_QUOT_L_MASK REG_GENMASK8(7, 0)

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

247

#define C10_PLL12_FRACN_QUOT_H_MASK REG_GENMASK8(7, 0)

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

248

#define C10_PLL13_FRACN_REM_L_MASK REG_GENMASK8(7, 0)

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

249

#define C10_PLL14_FRACN_REM_H_MASK REG_GENMASK8(7, 0)

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

250

#define C10_PLL15_TXCLKDIV_MASK REG_GENMASK8(2, 0)

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

251

#define C10_PLL15_HDMIDIV_MASK REG_GENMASK8(5, 3)

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

252

#define C10_PLL15_PIXELCLKDIV_MASK REG_GENMASK8(7, 6)

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

253

#define C10_PLL16_ANA_CPINT REG_GENMASK8(6, 0)

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

255

#define C10_PLL17_ANA_CPINTGS_H_MASK REG_GENMASK8(5, 0)

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

256

#define C10_PLL17_ANA_CPPROP_L_MASK REG_GENMASK8(7, 6)

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

257

#define C10_PLL18_ANA_CPPROP_H_MASK REG_GENMASK8(4, 0)

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

258

#define C10_PLL18_ANA_CPPROPGS_L_MASK REG_GENMASK8(7, 5)

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

259

#define C10_PLL19_ANA_CPPROPGS_H_MASK REG_GENMASK8(3, 0)

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

260

#define C10_PLL19_ANA_V2I_MASK REG_GENMASK8(5, 4)

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

265

#define C10_CMN3_TXVBOOST_MASK REG_GENMASK8(7, 5)

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

269

#define C10_TX1_TERMCTL_MASK REG_GENMASK8(7, 5)

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

282

#define C10_PHY_OVRD_LEVEL_MASK REG_GENMASK8(5, 0)

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

307

#define PHY_C20_DP_RATE_MASK REG_GENMASK8(4, 1)

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

311

#define PHY_C20_HDMI_RATE_MASK REG_GENMASK8(1, 0)

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

375

#define C20_PHY_VSWING_PREEMPH_MASK REG_GENMASK8(5, 0)

drivers/gpu/drm/i915/display/intel_lt_phy.c

1876

transmitter_mask = lane_reversal ? REG_GENMASK8(3, 2) : REG_GENMASK8(1, 0);

drivers/gpu/drm/i915/display/intel_lt_phy.c

1878

transmitter_mask = REG_GENMASK8(1, 0);

drivers/gpu/drm/i915/display/intel_lt_phy.c

1881

transmitter_mask = lane_reversal ? REG_GENMASK8(3, 1) : REG_GENMASK8(2, 0);

drivers/gpu/drm/i915/display/intel_lt_phy.c

1883

transmitter_mask = REG_GENMASK8(2, 0);

drivers/gpu/drm/i915/display/intel_lt_phy.c

1886

transmitter_mask = REG_GENMASK8(3, 0);

drivers/gpu/drm/i915/display/intel_lt_phy.c

1890

transmitter_mask = REG_GENMASK8(3, 0);

drivers/gpu/drm/i915/display/intel_lt_phy_regs.h

23

#define LT_PHY_TX_SWING_LEVEL_MASK REG_GENMASK8(7, 4)

drivers/gpu/drm/i915/display/intel_lt_phy_regs.h

31

#define LT_PHY_TX_CURSOR_MASK REG_GENMASK8(5, 0)

drivers/gpu/drm/i915/display/intel_lt_phy_regs.h

42

#define LT_PHY_VDR_RATE_ENCODING_MASK REG_GENMASK8(6, 3)

drivers/gpu/drm/i915/display/intel_lt_phy_regs.h

43

#define LT_PHY_VDR_MODE_ENCODING_MASK REG_GENMASK8(2, 0)